High Speed Multipliers and Complex Summers

Download Full-Text PDF Cite this Publication

Text Only Version

High Speed Multipliers and Complex Summers

Rahul R Nadig

Department of Electronics and Communication K S Institute of technology,

Bangalore India

Aruna Rao B P

Pavan Prasad

Department of Electronics and communication K S Institute of technology,

Bangalore India

Department of Electronics and Communication K S Institute of technology,

Bangalore India

Abstract-Adders are basic digital circuits that perform binary addition. There are wide range of applications of adders depending upon the way they are implemented. Considering the fact that multiplication is successive addition, a multiplier is synthesised by multiplication of least significant bit (LSB) of multiplier with the multiplicand, binary addition of the product gives the result. Complex summers are designed by adding individual terms (real & imaginary) separately to give out the sum in terms of real and imaginary.

Keywords- Adders, multiplier, summer, Xilinx tool

  1. INTRODUCTION

    Adders are of two kinds. Half adders and full adders, half adders are used when there are two inputs are of single bit. Full adders are used when there are three inputs of single bit. The truth table of half adder is shown in table1.

    A

    B

    Sum

    Carry

    0

    0

    0

    0

    0

    1

    1

    0

    1

    0

    1

    0

    1

    1

    0

    1

    Table 1: Half adder truth table

    Figure 1: Half Adder circuit

    The truth table of full adder is shown in table2.

    A

    B

    C

    Sum

    Carry

    0

    0

    0

    0

    0

    0

    0

    1

    1

    0

    0

    1

    0

    1

    0

    0

    1

    1

    0

    1

    1

    0

    0

    1

    0

    1

    0

    1

    0

    1

    1

    1

    0

    0

    1

    1

    1

    1

    1

    1

    Table 2: Full adder truth table

    Figure 2: Full adder circuit

    When the number of inputs increases the speed of calculation decreases. To improve the speed Carry Look Ahead adders are considered wherein the amount of time required to calculate the carry bit is less. A carry look adder uses the concept of generator and propagator. Its advantage is wide variety of applications (multiplier and complex summer) that can be realised and implemented on a suitable hardware. The major disadvantage is as the number of variables increases the complexity of the circuit increases. The circuit is costlier as it involves a greater number of hardware. Multiplication is considered as successive addition, based on this logic a multiplier is designed using a carry look ahead adder.

    1. Carry look ahead adder

      A carry look ahead adder circuit consists of full adders in cascade and carry generation circuit. Each full adder generates a sum, generator and propagator expression simultaneously without a delay. The generator and propagator of each full adder is taken for the calculation the carry bit. A generator and propagator are given by, Consider two inputs A, B of size 1 bit. A generator is given by G (A, B) =A&B.

      A propagator is given by P (A, B) =A^B.

      These two equations are used for the calculation of the carry bit given by the formula –

      C i+1 = Gi +(Pi * Ci ).

      Consider i=0 then, C1=G0+(P0*C0) i=1 then, C2=G1+(P1*C1)

      i=2 then, C3=G2+(P2*C2)

      i=3 then, C4=G3+(P3*C0) i=4 then, C5=G4+(P4*C4) i=5 then, C6=G5+(P5*C5) i=6 then, C7=G6+(P6*C6) i=7 then, C8=G7+(P7*C7) i=8 then, C9=G8+(P8*C8)

      Figure 3 shows the block diagram of Carry Look Ahead Adder.

      Figure 3: Block diagram of Carry Look AheadAdder

      In carry look ahead adders carry-in(C0) is always initialised to zero.

      Past findings- Carry look ahead adders were implemented for 4-bits, 8-bits, 16-bits, 32-bits and 64-bits. Multipliers were implemented for 8-bits, 16-bits, 32-bits using different adders. [1] [4] [5] [6] [8] [10] [12] [14] [15].

      Based on this concept carry look ahead adders are implemented of 128-bits. A Verilog code is written to simulate carry look ahead adder. The Verilog code is written based on dataflow modelling. The sum and carry are calculated using the formulas specified. The Register Transfer Level (RTL) view of carry look ahead adders is shown in figure 4.

      Figure 4: RTL view of Carry Look Ahead Adder

      Simulation result is shown in figure 5.

      Figure 5: Simulation result of 128-bit carry look ahead adder

      Example: 1] Consider two inputs, 0001 (this is binary equivalent of 1)

      + 0010 (this is binary equivalent of 2)

      0011 (this is binary equivalent of 3)

      2] consider two inputs of 128-bits,

      32d FFFF (this is binary equivalent of 128)

      + 32d 0000

      32d FFFF (this is binary equivalent of 128)

      3] consider two inputs,

      32d FFFF (this is binary equivalent of 128)

      + 32d FFFF ( this is binary equivalent of 128) 32d FFFE (this is binary equivalent of 256)

    2. Carry look ahead Multiplier

      A multiplier is a digital circuit that multiplies two binary numbers. It is built using adders. A carry look ahead multiplier of n-bits gives a 2n-bits product. A Verilog code is written for a carry look ahead multiplier by instantiating a carry look ahead adder. To elaborate first the multipliers LSB bit is multiplied with the multiplicand the result is stored in a temporary variable. Further the next bit of multiplier is multiplied with multiplicand and result is stored by shifting 1 bit. This process is continued until all the bits of multiplier is multiplied with multiplicand. The intermediate product results obtained are added to give out the final product.

      Example- 1] Consider two inputs of 4-bits, 0011(this is binary equivalent of 3)

      X 0010(this is binary equivalent of 2) 0000

      0011 (Procedure of successiveaddition) 0000

      0000

      00000110 (this is binary equivalent of 6) 2] consider two inputs of 128-bits,

      32d FFFF (this is binary equivalent of 128) X 32d FFFF ( this is binary equivalent of 128)

      32d 0B400000 (this is binary equivalent of 16384)

      3] consider two inputs,

      32d FFFF (this is binary equivalentof128) X 32d 0000

      32d 00000000

      The RTL view of carry look ahead multiplier is shown in figure 6

      Figure 6: RTL view of Carry Look Ahead Multiplier (High speed Multipliers)

    3. Complex summer

    A complex summer is a circuit that is defined to add two complex numbers. A Verilog code is written by instantiating carry look ahead adders. The real part and imaginary part are calculated separately and finally the result is shown together. The simulation result for the Verilog code is shown in figure 6.

    Fig 6: Simulation result of a complex summer

    Example: 1] Consider two inputs, 3+j2 and 4+j5 0011 (this is binary equivalent of 3)

    + 0100 this is binary equivalent of 4) 0111 (this is binary equivalent of 7)

    0010 (this is binary equivalent of 2)

    + 0101 (this is binary equivalent of 5)

    The simulation results of carry look ahead multiplier is

    shown in figure 7

    0111 (this is binary equivalent of 7) Hence the final result is 7+j7.

    2] Consider two inputs, 11+j5 and 4+j7.

    1011 (this is binary equivalent of 11)

    + 0100 (this is binary equivalent of 4) 1111 (this is binary equivalent of 15)

    0101 (this is binary equivalent of 2)

    + 0111 (this is binary equivalent of 5)

    Fig 7: Simulation result of a 256-bit carry look ahead multiplier (high

    speed multipliers)

    A multiplier is basically used to reduce the number of operations thereby reducing the dynamic power which is a major part of the total power consumption so the need of multipliers in increased. As designers mainly.

    1100 (this is binary equivalent of 7) Hence the sum is 15+j7.

  2. CONCLUSION

Design of high-speed multipliers and complex summers using carry look ahead adders is simulated. Verilog code is used to simulate the multiplier and complex summer. Using the carry look ahead adder it improved the overall speed of the multiplier. The experiment shows significant increase

in speed over conventional multipliers. Reduced propagation time and faster addition logic is ideal for calculation of very large numbers (hundreds or even thousands of bits). As for large numbers the logic for carry does not become any complex. Hence it can be adopted for multiplication of very large numbers. Similarly, a complex summer can also be used for addition of large complex numbers required in scientific calculations. The codes written in Verilog are simulated on Xilinx tool.

REFERENCES

  1. Samir Palnitkar, Verilog HDL A guide to digital design and synthesis.

  2. John M Yarbrough, Digital logic applications and design

  3. Anand Kumar Fundamentals of digital circuits Prentice hall India publications, 2004.

  4. Jagannath Samanta, Mousam Halder, Bishnu Prasad De PerformanceAnalysis of High-Speed Low Power Carry Look- Ahead Adder Using Different Logic Styles International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, Jan- 2013

  5. P. Ram Sirisha, Dr.A.M. Prasad, IEEE JOURNAL Design and Performance Analysis of 32-bit Array Multiplier using optimized Carry Select Adder September 2015.

  6. Hasan Krad* and Aws Yousif Design and Implementation of a Fast Unsigned 32-bit Multiplier Using Verilog Qatar University/Department of Computer Science & Engineering, Doha, Qatar.

  7. W. Stallings, Computer Organization and Architecture Designing for Performance, 71h ed., Prentice Hall, Pearson Education International, USA, 2006, ISBN: 0-13-185644-8.

  8. V. Vijayalakshmil,R. Seshadd, Dr.S. Ramakrishnan3 Design and Implementation of 32-Bit Unsigned Multiplier Using CLAA and CSLA IEEE 2013.

  9. G. Prakash, K. Sathishkumar, B. Sakthibharathi S. Saravanan,

    R. Vijaysai Achieveing reduced area by multi-bit flip flop design International Conference on Computer Communication and Informatics (ICCCI -2013), Jan. 04

  10. A novel implementation of 4-bit carry look ahead adder, International conference on electron devices and solid-state circuits, Jia Miao, Oct 2018

  11. FPGA Implementation of synchronous section carry based lookahead adders, K Preethi, P Balasubramanian, Mar 2014

  12. Performance analysis of 32-bit array multiplier with a carry save adder and with a carry look ahead adder, Raminder Singh,

    Praveen Kumar, Balwinder singh lakha

  13. A family of adders, conference paper, Feb 2001

  14. Performance analysis of 32-bit multiplier with a carry look ahead adder and a 32-bit multiplier, Hasan Krad, Aws fida El- din

  15. A novel high speed 64-bit multiplier, Pouya Asadi, Sep 2007

Leave a Reply

Your email address will not be published. Required fields are marked *