 Open Access
 Authors : Rachana S, Ritu Patil, Sahana V, Aruna Rao B P
 Paper ID : IJERTCONV8IS11062
 Volume & Issue : IETE – 2020 (Volume 8 – Issue 11)
 Published (First Online): 04082020
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Design and Delay Analysis of Various 256Bit Adders using Verilog
Rachana S
Department of ECE
K S Institute of Technology Bangalore, India
Ritu Patil
Department of ECE
K S Institute of Technology
Sahana V
Department of ECE
K S Institute of Technology Bangalore, India
Abstract In this paper, several adders are being examined and compared in terms of delay of throughput. The objective of this paper is to design different architecture of adders and to observe the reliable output. Existing adders performance will widely vary with respect to their area requirements and speed of execution. The proposed adders architecture named Ripple carry adder, Carry look ahead adder, Carry skip adder, Carry save adder, Carry select adder, decomposes into blocks of carry generator, carry propagator and multiplexer. As Addition is the most important operation in data processing hence its speed has a significant impact on digital circuits. We have demonstrated the efficiency of the proposed architectures along with the design method in 256 bit operands.
Keywords Throughput, RTL schematic, Technological schematic, Simulation, Ripple carry adder, Operands, RCA (Ripple Carry Adder), CLA (Carry Look Ahead adder), CSkA (Carry Skip Adder), CSA (Carry Save Adder), CSlA (Carry Select Adder), ALU (Arithmetic Logic unit)

INTRODUCTION
Adders are called a digital circuit because they perform addition of numbers. It is a circuit that sums up the amplitude of 3 inputs that gives 2 outputs called sum and carry.They are being used in many processor architectures, ALU and computational units. Each adder creates a carry value which needs to be propagated via the circuit adders. Even though for many number of representations, adders can be constructed in the form of binary coded decimal or excess3, the most common adders operate on binary numbers.
RLA is a digital adder circuit, where in the carry out of every full adder will be the carry in of the next most significant full adder. It is so called because each carry bit receives rippled into the following next stage. CLA or fast adder is a type of digital circuit. It calculates one or more carry bits earlier than the sum, which reduces the wait or delay time. CSA is a form of virtual adder used in computer microarchitecture to locate the sum of 3 extra nbit numbers in binary. CSlA is a way to enforce an adder, which may be a logic detail that finds out the sum of numbers. CSkA is a type of adder implementation that improves on delay of RCA when compared to other adders.
Aruna Rao B P
Department of ECE
K S Institute of Technology Bangalore, India

EXPRESSION OF ADDER Sum = A^B^Cin
Carry = (A&B)(B&Cin)(Cin&A) Carry generator = A&B
Carry propagator = A^B
Table 1: Truth Table

METHODOLOGY

Ripple Carry Adder
Basically, a full adder plays the addition operation on three inputs and produces the two outputs. Initially, it performs the addition on two inputs such as A and B along with the third input carry as CIN. The two outputs produced are designated as S and COUT, where S is sum and COUT as carryout. Full adder is designed with such a logic that it is capable of taking eight inputs at a time in order to create a bytewide adder and the output carry is cascaded from one adder to another.
Figure 1: RTL View of RCA
Logical Expression for SUM:
= A B CIN + A B CIN + A B CIN + A B CIN
= CIN (A B + A B) + CIN (A B + A B)
= CIN XOR (A XOR B)
Logical Expression for COUT:
= A B CIN + A B CIN + A B CIN + A B CIN
= A B + B CIN + A CIN
By making use of the truth table, we can implement the full adder logic. Sum expression is an XOR operation between the inputs A, B and CIN whereas Carryout expression is an AND&OR operation between the inputs A,B and CIN.
Figure 2: Technological View of RCA

Carry Look Ahead adder
A carrylook ahead adder (CLA) is also known as a fast adder which is basically used in digital logic. It is known as a fast adder because it increases the speed by reducing the time required to interpret the carry bits Working of the CLA follows like this, initially it calculates the carry bits before sum, so it is helpful in reducing the propagation delay to find the result of the larger bits of the adder.(P. Balasubramanian, 2016)
Figure 3: RTL View of CLA
The carry look ahead requires the additional hardware to improve its speed but it is not dependent on the number of bits. Basically this adder makes use of propagating and generating carries. Fast adder mainly depends on two things
i.e. Calculating for each digit position whether it is going to propagate the carry, now the word digit can be replaced by the word bit since it makes use of the concepts generating
and propagating carries. Secondly, by combining all these calculated values to deduce quickly to know whether the group is going to propagate the carry which comes in from the right.
G (A, B) =A & B P (A, B) =A+B
Figure 4: Technological View of CLA

Carry Skip adder
Carry Skip adder is often called as Carry bypass adder. In this the implementation of the adder enhances the delay of RCA with less effort when compared with other adders. In the worst case, the improvement in delay is achieved by making use of several carry by pass adders to form a blockcarryskipadder. Unlike the other adders such as RCA, CLA etc. the performance of this carry skip adder can be enhanced with only a few combinations of input bits. The critical path in this adder begins at the first full adder. In order to reduce this critical path, blockcarryskip adders are used where the skip adders are chained.
Figure 5: RTL View of CSkA
Blockcarryskip adders are basically composed of many number of carryskip adders. Mainly there are two kinds of this adder i.e. Fixed size blockcarrybypassadders and Variable size blockcarrybypass adders. The critical path in this fixed size adders consists of the ripple path and the first block consists of the skip element. The performance of this adder can be still increased by making use of the variable
size blockcarryskip adders i.e. the preliminary blocks of this adder are made smaller to notice the carry generated quickly to propagate in addition and the middle blocks are not made small later the most significant blocks are made small so that the carry inputs arriving late is processed quickly.(Shweta Thakur, Aug 2018)
Figure 6: Technological View of CSkA

Carry Save adder
In Ripple Carry Adder (RCA), propagation of carry from one stage to the other stage takes longer time. Due to this reasonRCA will introduce an overall delay in the circuit. In order to avoid this problem, carry save adder came into an existent. It also had sort out the delay problem up to certain extent. Due to which the propagation of carry in carry save adder can be avoided. In this adder partial sum and partial carry is generated and also get stored. The partial carry which is stored cannot be propagated to the successivebits of higher order. The generated partial carry and partial sum in last step will be get added by using any of the carry propagation adder.(Ashvin Chudasama, 2016)
Figure 7: RTL View of CSA
In order to avoid waiting for ripple,carry look ahead adder adds up the group generate signals and group propagate signals. Carry Look Ahead adder provides higher delay for the higher order bits when compared to other addrs due to
the existence of large number ofgates. In digital adders, speed of the addition is defined by timeneeded to propagate the carry acrossthe adder. In case of primary adder for eachbit position the sum is generated sequentially only after the previous bit position has been summed.
Figure 8: Technological View of CSA

Carry Select adder
The carryselect adder comprises two ripple carry adders and a multiplexer. Addition of two nbit numbers with a carryselect adder is computed with two adders, therefore we use two ripple carry adders. In order to perform the calculation twice, one time by assuming the carryin being zero and the other time assuming it will be one. After both the results are calculated, the correct sum, and the correct carryout, is selected by the multiplexer once when the correct carryin is known. Therefore the wide variety of bits in every carry select block can be uniform, or variable.(Bala Sindhuri Kandulaa, 2016)
Figure 9: RTL View of CSlA
Figure 9 is the RTL (register transfer level) view of the carry select adder. It has 3 inputs A, B and Cin with the sum and carry as output. Since we are working on 256 bit the inputs to A, B are 255:0 which is equal to 256 bit.
After working with the Xilinx tool the simulation output was 5.31 secs which is the CPU execution time.
Figure 10: Technological View of CSlA


SIMULATION RESULT
Total CPU time to Xst completion: 5.39secs
Timing Report:
Figure 14: CSA
Total REAL time to Xst completion: 6.00 secs Total CPU time to Xst completion: 5.28 secs
Timing Report:
Figure 11: RLA
Total REAL time to Xst completion: 6.00 secs Total CPU time to Xst completion: 5.41 secs
Timing Report:
Figure 15: CSlA
Total REAL time to Xst completion: 6.00 secs Total CPU time to Xst completion: 5.31 secs
SL.N O
TYPES OF ADDER S
REAL TIME EXECUTION(I N SECS)
CPU TIME EXECUTION(I N SECS)
1
RCA
6.00
5.41
2
CLA
5.00
5.06
3
CSkA
6.00
5.39
4
CSA
6.00
5.28
5
CSlA
6.00
5.31
SL.N O
TYPES OF ADDER S
REAL TIME EXECUTION(I N SECS)
CPU TIME EXECUTION(I N SECS)
1
RCA
6.00
5.41
2
CLA
5.00
5.06
3
CSkA
6.00
5.39
4
CSA
6.00
5.28
5
CSlA
6.00
5.31

CONCLUSION
Timing Report:
Figure 12: CLA
Total REAL time to Xst completion: 5.00 secs Total CPU time to Xst completion: 5.06 secs
Timing Report:
Figure 13: CSkA
Table 2: Comparison Table
An extensive performance of all types of adders has been examined. Their performance was analyzed in terms of gate level and delay throughput. From this analysis, 256 bits ripple carry adder is just a series of full adder connected serially where carry propagator from first full adder to last one. Delay is maximum on this case. Carry look ahead adder is one which is calculated beforehand and of course delay is much lesser when compared to others. In carry save and carry select adder, the delay is minimum as compared to carry skip and full adder. Therefore, carry skip is faster than
Total REAL time to Xst completion: 6.00 secs
full adder. Hence it can be concluded by stating that full adder has the maximum delay when compared to other
adders (carry look ahead adder, carry skip adder, carry save adder, carry select adder)(Kunjan D. Shinde)
REFERENCES

Ashvin Chudasama, T. N. (2016). Implementation of 4×4 Vedic Multiplier using Carry Save Adder in QuantumDot Cellular Automata . 12601264.

Bala Sindhuri Kandulaa, K. P. (2016). Area Efcient VLSI Architecture for Square Root Carry Select Adder using Zero Finding Logic . Procedia Computer Science 89 , 640 650.

D.Mohanapriya, D. (2016). A Comparative Analysis of Different 32bit Adder Topologies with Multiplexer Based Full Adder , Volume 6 Issue No. 5. IJESC , 48504854.

Dr. G.S. Sunitha, R. H. (2017). DESIGN AND IMPLEMENTATION OF ADDER ARCHITECTURES AND ANALYSIS OF PERFORMANCE METRICS . International Journal of Electronics and Communication Engineering and Technology (IJECET) Volume 8, Issue 5, 16.

J. Vinoth Kumar, D. C. (2017). DESIGN OF ENHANCED SQRT CARRY SELECT ADDER FOR VLSI IMPLEMENTATION OF 2D DISCRETE WAVELET TRANSFORM . International Journal of MC Square Scientific Research Vol.9, No.2, 6469.

K. RENUKA PRIYADARSHINI, V. N. (JanDec2018). Implementation of Area Efficient CarrySelect Adder . International Journal of VLSI System Design and Communication Systems ISSN 23220929 Volume06, 226231
.

Omid Akbari, M. K.K. (2016). RAPCLA: A Reconfigurable Approximate Carry LookAhead Adder .

P. Balasubramanian, C. D. (2016). Asynchronous Early Output SectionCarry Based Carry Lookahead Adder with Alias Carry Logic .

Padmanabhan Balasubramanian 1, D. M. (2018). Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic. electronics.

PUSHPENDRA KUMAR SHARMA, M. K. (2019). Performance Analysis of Low Power and High Speed onebit Full Adder Circuit . International Journal of Applied Engineering Research ISSN 09734562 Volume 14, Number 2, 116121.

R. Bala Sai Kesava, K. B. (2016). Low Power And Area Efficient Wallace Tree Multiplier Using Carry Select Adder With Binary To Excess1 Converter. 248253.

S. M. PADMAVATHI, N. R. (2016). Design and Implementation of Carry Skip Adder using AOI and OAI . International Journal of VLSI Design and Communication Systems (IJVDCS), 08050809 .

Shweta Thakur, E. A. (Aug 2018). Design & Implementation of 16bit Carry Skip Adder using Reversible Computing . Shweta Thakur Journal of Engineering Research and Application ISSN : 22489622, Vol. 8, Issue 8 (Part I), 6872 .

Sujan Sarkar, J. M. (2017). Design of Hybrid (CSACSkA) Adder for Improvement of Propagation Delay . 332336.

Ubaidulla, P. A. (August 2016). Implementation of High Speed and EnergyEfficient Carry Skip Adder using Verilog HDL . IJSTE – International Journal of Science Technology & Engineering  Volume 3  Issue 02, 156159.