- Open Access
- Total Downloads : 19
- Authors : Shiv Ashish Agrahari, Anil Kumar Sahu
- Paper ID : IJERTCONV3IS20084
- Volume & Issue : ISNCESR – 2015 (Volume 3 – Issue 20)
- Published (First Online): 24-04-2018
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License: This work is licensed under a Creative Commons Attribution 4.0 International License
A Review paper on Approach of Low Cost Digital Test Stimulus Generation for Sigma Delta ADC Built-in Self-Test
Shiv Ashish Agrahari
ME Research Scholar, SSTC, Bhilai
Abstract-Design issues of analog to digital converter play very important role in mixed signal design and SoC. Testing of a SoC (System on Chip) is a challenging task, especially for its growing analog and mixed-signal core. In this paper, we have reported a brief review on different BIST approach for sigma- delta ADC to measure offset error and gain error of sigma-delta modulator. This review is made up of a generator of stimulus and an analyzer of response. We compare a digital technique for the test of static characteristics of the modulator with existing work. A shift register based signal generator is reported which can concurrently produce test stimulus and reference signals.
Keywords: BIST; Mixed Testing; ADC converter; Stimulus generator; Sigma delta modulator; Analyser; Soc.
The task of testing a VLSI chip to guarantee its functionality is extremely complex and very time-consuming. The problem of testing the chips themselves, the combination of the chips into systems has caused test generation's cost to grow exponentially. Built-in self-test (BIST) is widely accepted approach to deal with the testing problem at the chip. This increases the controllability and the observability of the chip, thereby making the test generation and fault detection easier.
In conventional testing, test patterns are generated externally by using computer-aided design (CAD) tools. The test patterns and the expected responses of the circuit under test to these test patterns are used by automatic test equipment (ATE) to determine if the actual responses match the expected ones. On the other hand, in BIST, the test pattern generation and the output response evaluation are done on the chip; thus, the use of expensive ATE machines to test chips can be avoided.
The paper is organized as follows: Section 2describes Sigma Delta ADC Testing. Section 3 describes The Basic Built-in Self-Test (BIST) Structure. Section 4 discusses previous work regarding testing Delta Sigma converters. Section 5 describes proposed work and finally the conclusions are drawn in Section 6.
SIGMA DELTA ADC TESTING
ADC testing can roughly be divided into two separate parts, static and dynamic testing. In static testing, the converter under test is subjected to a series of dc voltage levels and the output values are monitored to determine the converters accuracy. One major limitation in static testing is that nonlinearities related to the input signal bandwidth may pass undetected.
Anil Kumar Sahu
Assistant Professor, SSTC, Bhilai
Dynamic testing is when the converter is stimulated by periodic waveforms instead of dc levels. This type of testing is usually better suited for production testing due to easier signal generation and less time-consuming behaviour. The signal bandwidth can be higher than in static testing and thereby resembling the actual applications signal. However one disadvantage is that dynamic tests are usually not deterministic in nature, the analog input is not compared to the resulting digital code; instead the converter transfer function is interpreted from the resulting out data. To ensure sufficient resolution under test, the signal source needs a resolution at least 3-bit greater than the device under test. (IEEE_Std_1241, 2001)
THE BASIC BUILT-IN SELF-TEST (BIST) STRUCTURE
A basic BIST configuration is shown in Figure 1. The main function of the test pattern generator is to apply test patterns to the unit under test (assumed to be a multi-output combinational circuit). BIST increases the controllability and the observability of the chip, thereby making the test generation and fault detection easier. The resulting output patterns are transferred to the output response analyzer. Ideally, a BIST scheme should be easy to implement and must provide high fault coverage.
Fig. 1 Basic BIST configuration
BIST controller is used to control the whole testing process. The test pattern generator and output response analyser can be modified according to accuracy and area of the chip.
A number of research papers of various journals and conferences were studied and survey of existing literatures in the proposed area is reported below:-
In , describes a method for obtaining a short periodic approximation of the PDM pattern and identifies two methods of integrating this analog test scheme into the current digital test environment: scan-based storage and RAM. Using such design for test logic as the 1149.1-1990 JTAG architecture and a typical RAM BIST controller, these
analog signal generation techniques can be added to digital integrated circuits (ICs) with minimal additional hardware overhead, and also explained two memory-based PDM techniques which utilize an arbitrary finite-length bit pattern for analog signal generation.
In , demonstrated a new method for generating analog signals with very low complexity and hardware requirements. It consists of periodically replicating short optimized bit streams recorded from the output of a sigmadelta modulator. A technique to generate sine waves and other signals with small hardware area and simple circuits is presented. It consists of reproducing periodically the output of a sigma delta modulator with some memory on the IC and also demonstrated the various types of signals that can be generated with the bit stream approach.
In , proposed a built-in self-test structure to test the static parameters of analog to digital converters (ADCs). To serve the test stimulus, they used ramp signal generated by an integrator.A specific range of signal is divided into2+1 segment, with each segment corresponding to one output combination of a n+1-bit counter, where n is the number of bits of the ADCs under test. The testing process is ended with digital data processing by comparing the outputs of ADCs under test with the outputs of the n+1-bit counter. The advantages of this structure are less area overhead, High speed, Simple structure.
In , explained a BIST scheme for testing on-chip AD and DA converters. On-chip generation of linear ramps as test stimuli for measuring the DNL and INL of the converters. The proposed BIST scheme in this work employs the delta- sigma modulation technique to generate the required linear ramp for testing the converters.For ADC testing, proposed BIST strategy is "linear histogram testing" and measure differential/integral nonlinearities (DNL/INL). For DAC testing, proposed test scheme that employs an analog comparator and two counters for measuring the DAC parameters. The DAC BIST strategy is immune from the common offset voltage of the analog comparator since it is cancelled out in the analysis process and thus has little effect on the test accuracy also.
In , measure the four key parameters of A/D converters, namely offset error, and gain error, integral nonlinearity error and differential nonlinearity error. In proposed scheme, a sigma-delta modulation based signal generator is used which can concurrently produce analog sinusoidal test stimuli and digital sinusoidal reference signals on a chip. By comparing the sinusoidal histogram of the ADC output signals with that of the generated reference digital signals, the testing parameters can be determined on-chip also in signal generator is implemented on-chip which not only can supply a high quality analog signal to the A/D converters under test, ut also is able to concurrently produce a digital reference signal without any extra area overhead. Based on this real-time generated reference, there is no need to calculate the reference histograms in apriority, nor is it necessary to store the histograms of any fixed frequencies.
In , new architecture for the sigma-delta modulator so that its performance can be determined using only digital test
stimulus. This architecture does not require analog test stimuli, which is prone to distortion while setting up the high- resolution modulator to perform testing. Simulation results show that this technique is capable of accurately determining the performance of a second-order sigmadelta modulator ADC. A sigmadelta DFT architecture that can be tested with a digital signal. This feature eliminated the need to generate an analog signal, which can be costly for high-resolution modulators.
In , presented a low-cost BIST scheme based on linear histogram for testing ADC. A parallel time decomposition technique is used to minimize hardware overhead, it also minimize the testing time of the BIST scheme based on histogram. To generate the on-chip precise analog stimulus and simplify the analog circuit of the generator at same time, the technique digital delta-sigma noise shaping is used. Triangular waveform is used for test stimulus. The scheme follows the concept of time decomposition to reduce the area overhead of analyser. Regarding increasing testing time in the scheme of time decomposition, the parallel time decomposition technique is proposed further to reduce testing time of the ADC BIST based on the linear histogram.
In , proposed a Built-In Self-Test (BIST) technique for the test of SNDR (Signal-to-Noise plus Distortion Ratio) in ADCs. The technique is mostly digital, uses a bit stream as test stimulus and carries out a sine-wave fitting algorithm to analyse the output response. The test signal generation and the output response analysis both are performed on-chip. Simulations results show the capability of this technique to obtain measures of the SNDR for a 16-bit audio ADC.A 4th order since filter has been used instead of a 3rd order in the decimation filter. Equally, larger digital paths have been employed in the last stages of the decimation filters. Two possible implementations have been presented, for ICs with or without a memory. In both cases, the test time is much reduced (0.03s). Only an additional attenuated reference voltage and several switches need to be added in the analogue modulator.
In , presented a Built-In Self-Test (BIST) methodology to measure offset error and gain error of sigma-delta modulator. This structure is made up of a generator of stimulus and an analyser of response. A memory-based signal generator is presented which can concurrently produce test stimuli and reference signals. Contribution is the detection of the static parameters by analysing the output bit stream of the 1-bit first-order sigma-delta modulator in order to have a logic test decision. This technique can be easily implemented, since the digital sequence stored in memory can be at the same time the digital test stimulus and test reference. Hence, testing of the static characteristic of the modulator under test with a simple response analyser by comparing the real bit stream output with the ideal one.
Study of more than 10 research papers can be summarized in following manner:-
Most of the researchers have addressed static specifications of the sigma-delta modulator.
Different types of test stimulus generator were used such as:-
Ramp type stimulus generator.
Sinusoidal type stimulus generator.
Bitstream or digital bit generator.
Triangular type stimulus generator.
Memory-based stimulus generator.
Different types of tester or analyser were used.
Shift resister based.
Different order of sigma-delta modulator are is tested such as-
First order sigma delta modulator.
Second order sigma delta modulator.
Parameter used to estimate the performance is: SNR, SNDR, dynamic range, power consumption, FOM, resolution, bandwidth, hardware cost, oversampling ratio.
Digital bit stream pattern generator takes very less area on a chip.
Sigma delta modulator can beused in form of pattern generator.
Ramp stimulus generator is depending on the accuracy of integrator.
Memory based built in self-test takes a large area.
After reviewing the papers we find that there are some limitations in the process taken. Some of them are
There is a tread off between area, complexity and speed.
Complex circuit consumes more power.
Analog stimulus generator requires digital to analog converter.
Bitstream or digital bit in memory takes more area and makes the testing process complex.
Ramp stimulus generator is depending on the accuracy of integrator.
Complex computation and more number of input
Figure 2 is showing the basic building blocks of complete testing for sigma-delta analog to digital converter. Major blocks areTest Stimulus Generator, Sample & Hold circuit, Mux, Response Analyzer, Devices under test.
Fig 2 Block Diagram of Proposed Work
Test stimulus generator
Test stimulus generator consists of two blocks. Shift Registers and Digital filter.
Bitstreams are generated with the help of shift registers. These patterns are sending into digital filter and analyser. Digital filter excess these patterns and convert it into discrete analog level. One bit DAC can be used here. Digital filter works like digital to analog signal generator.
Sample and hold circuit
Maintain the desired analog input to the modulator during a required time.
Switches between controlling function during the test mode and functional configuration during usual mode. Select signal is high for test mode and low for a usual mode.
Response analyser has two input digital signal. One from shift registers and the other one is from the output of sigma- delta modulator. Analyser compares these input bit by bit. A window method can be used.
In this method, a fixed analog input is applied to the modulator under test and the corresponding output level is evaluated. The principle of test consists of the comparison between the real measured and the ideally stored bit stream. The modulator response analysis is determined by a window with Test period and L length, the test procedure is represented by the figure 3. The output code does not change during Tt. Tt must be enough in order to find the initial state of the modulator after a number of L iterations. Thus, we can propose the following hypothesis: the analog magnitude
applied to the input of the device during Tt is constant since the signal dynamics is very low.
Fig. 3 the Window Method
Fig. 4 Flow chart of proposed work
This technique uses digital bit stream as test stimulus and a digital filter to convert bit stream into its analog value. Since the digital sequence is generated from shift register hence, pattern generator takes less area. We can measure the static characteristic (offset error and gain error) of the modulator under test with a simple response analyser by comparing the real Bit stream otput with the ideal one. Conclusion is that proposed methodology is less complex and also testing time is very less. Because of these cost and power consumption would be less. Chee-Kian, O., Kwang-Ting, C. & Wang, L. C. (2004), A New Sigma-Delta Modulator Architecture for Testing Using Digital Stimulus. IEEE Transactions on Circuits and Systems, 51, 206-213.  Wang, Y.-S., Wang, J.-X., Lai, F.-C. & Ye, Y.-Z. (2005), A Low-
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