 Open Access
 Total Downloads : 134
 Authors : Gorantala Shyamsunder, Dr. S. Chandrashekar Reddy
 Paper ID : IJERTV6IS070269
 Volume & Issue : Volume 06, Issue 07 (July 2017)
 DOI : http://dx.doi.org/10.17577/IJERTV6IS070269
 Published (First Online): 26072017
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
The Active Voltage Quality Regulator with the DCLink Capacitor Boosting Circuit
Gorantala.Shyamsunder
Student of E.P.S [Electrical Power System] Department of Electrical and Electronics Engineering Christu Jyoti Institute of Technology & Science Warangal, Telengana, India
Dr. S. Chandrashekar Reddy
Professor
Department of Electrical and Electronics Engineering Christu Jyoti Institute of Technology & Science Warangal, Telengana, India
AbstractVoltage sags have always been a huge threat to sensitive industrial and commercial electrical consumers; and deep sags with long duration time are usually more intolerable. In this paper, a new topology of seriesconnected compensator is presented to mitigate long duration deep sags, and the compensation ability is highly improved with a unique shunt converter structure acting as a DCLink capacitor boosting circuit that has been theoretically analyzed. Additionally, the proposed active voltage equality regulator is a cost effective solution for long duration sags that are lower than 50% of the nominal voltage as it is compared with the traditional dynamic voltage restorer. High operation efficiency is ensured by applying the dclink voltage adaptive control method. Analysis, along with simulation and experimental results, is presented to verify the feasibility and effectiveness of the proposed topology.
KeywordsDynamic voltage restorer (DVR), dynamic sag correction, long duration deep sag, DCLink capacitor boost circuit, seriesconnect compensator.

INTRODUCTION
The Power quality (PQ) problems have obtained increasing attentions as they can affect lots of sensitive endusers including industrial and commercial electrical consumers. Studies indicate that voltage sags, transients, and momentary interruptions constitute 92% of all the PQ problems occurring in the distribution power system. In fact, voltage sags have always been a huge threat to the industry, and even 0.25 s voltage sag is long enough to interrupt a manufacture process resulting in enormous nancial losses. Voltage sags are generally classified according to its depth and duration time. Typical sag can be a drop to between 10% and 90% of the rated RMS voltage and has the duration time of 0.5 cycles to 1 min. The majority of the sags recorded are of depth no less than 50%, but deeper sags with long duration time obviously cannot be ignored as they are more intolerable than shallow and shortduration sags to the sensitive electrical consumers. More characteristics about voltage sags are described in many customer power devices have been proposed to mitigate such voltage sags for sensitive loads.
Fig. 1. Singlephase DySC configuration.
Fig. 1.1 SIMULATED DySC
The most studied voltage regulator topologies can generally categorized into two groups: the inverterbased regulator and direct acac converters. Several acac converterbased regulators are introduced. Seriesconnected devices (SD) are voltagesource inverterbased regulators and an SD compensate for voltage sags by injecting a missing voltage in series with the grid. There are lots of SD topologies, and key
features related to the evaluation of a certain SD topology are the cost, complexity, and compensation ability. Dynamic voltage restorer (DVR) is a commonly used SD and has been widely studied. The overall evaluation has shown that DVR with no storage and loadsideconnected shunt converter ranks the highest as it can compensate for longduration deep sags at a relatively low complexity and cost.
However, the aforementioned DVR topology is still not a cost effective solution for long duration deep sags as it regularly contains a series transformer that is heavy, bulky, and costly operating at the line frequency. This drawback is obviously non ignorable especially in lowpower applications. A type of transformer less SD topology known as dynamic sag corrector (DySC) is proposed, and it is a low cost, small size, Light weight, and highly effective system for sag mitigation as the series transformer is no longer needed. There are several circuit structures of the DySC Fig. 1 illustrates another possible configuration. When the grid voltage differs from its desired waveform, a missing voltage will be injected and filtered by the DySC through its halfbridge series converter (V1, V2) and output filter (Lf , Cf ) to maintain the load voltage at its rated value. During this period of time, the energy needed for the compensation is provided by the residual supply via a passive shunt converter (D1, D2, L1 ) and stored in the dclink capacitors (C1, C2 ). So, the dclink voltage should always be lower than the peak value of the supply voltage, and it means that the DySC can only compensate for voltage sags no deeper than 50% since the largest injection voltage of the DySC is solely determined by its dclink voltage. The ridethrough time of the DySC in deeper voltage sags is limited by the dclink energy storage, and it is inadequate to provide reliable protection for sensitive loads. So, although the DySC is an excellent solution for sags in many cases, it is invalid for longduration deep sags as its compensation ability is limited by the passive rectifier, either PWM rectifier or backup grid is adopted to increase the energy provided during voltage sags. But the compensation ability is greatly enhanced at the expense of significantly increasing the complexity and cost. In this paper, position of the shunt converter and series converter in the DySC is changed according to the structure differences between the DVR with the loadsideconnected shunt converter and the DVR with the supplysideconnected shunt converter. As a result, the shunt converter together with the series converter formed a boost charging circuit and the dclink voltage will be charged to exceed the peak value of the supply voltage. This obtained novel topology is called the transformer less active voltage quality regulator with the parasitic boost circuit (PBAVQR), and it is capable of mitigating long duration deep voltage sags without increasing the cost, volume, and complexity compared with the traditional DySC topology. The dclink voltage adaptive control method is also applied in the PBAVQR to improve its operation efficiency. This paper starts with introducing the operating mode and working principles of the proposed configuration. Then, the parasitic boost circuit model is provided followed by the theoretical analysis to calculate its dclink voltage. At last, the simulation results using MATLAB and experimental results on a 220 V2kWprototype are given to verify the feasibility and effectiveness of the PBAVQR topology.

TOPOLOGY AND PRINCIPLE
As shown in Fig. 2, the PBAVQR topology is mainly consists of five parts, including a static bypass switch (VT1, VT2),a halfbridge inverter (V1, V2), a shunt converter (VT3, VT4),a storage module (C1, C2 ), and a lowpass filter (Lf , Cf ). The operating mode and applied control strategies are similar to what have been described in [25]. Under normal operating conditions, the static bypass switch is controlled to switch on and the normal grid voltage is delivered directly to
Fig. 2. Proposed PBAVQR topology.
Fig. 3. SPBAVQR topology.
Fig. 3.1 SIMULATED PBAVQR
the load side via this bypass switch. When an abnormal condition is detected, the static bypass switch will be switched OFF and the inverter will be controlled to inject a desired missing voltage in series with the supply voltage to ensure the power supply of sensitive loads. There are totally two different kinds of control strategies in th proposed PB AVQR system. When the grid voltage is lower than the rated voltage, an inphase control strategy will be adopted and a phaseshift control strategy will be applied when the supply voltage is higher than the nominal voltage. Working principle of the PBAVQR is different compared with that of the DySC due to its unique shunt converter structure. When the proposed configuration is analyzed, both the operating states of the switches (V1, V2) and the trigger angles of the thyristors (VT1,VT2) should be taken into consideration. So, a simplified PBAVQR (SPBAVQR) circuit shown in Fig.3, where two thyristors (VT3, VT4) in the proposed PBAVQR are replaced by two diodes (D1, D2), is firstly introduced to better explain its working principles. The following analysis will be based on the SPBAVQR which can be regarded as a
special type of PBAVQR. The only difference between these two configurations is that the shunt converter of the PB AVQR is controllable while the shunt converter of the SPB AVQR is uncontrollable. That is to say, the dclink voltage of the SPBAVQR represents the upper limit of the dclink voltage in the PBAVQR structure. So, theoretical conclusions drawn with the SPBAVQR are basically applicable to the PBAVQR.
As shown in Fig. 3, switches V1 and V2 are now also parts of the parallel circuit, which means that the dclink voltage will be affected by the on/off status of the switches. So, the turn on and turn off conditions of the compensation process should be considered to understand the working principles about the parasitic boost circuit of the SPBAVQR. Figs. 4 and 5 illustrate four different operating conditions of the SPBAVQR within one switching cycle during the positive and negative halfcycle of the sinusoidal supply voltage separately. Both the compensation process and charging process can be explained based on these operating conditions. In Figs. 4 and 5, the solid line means that there is current flowing through and arrows depict directions. Operating conditions during the positive halfcycle are illustrated in Fig.
4. When V2 is switched on, as shown in Fig. 4(a), the grid charges the inductor L1 via the diode D2 and the capacitorC2 discharges to maintain the load voltage. When V2is switched off, as shown in Fig. 4(b), the energy stored in the inductor during previous period is released to dclink capacitorsC1 and C2 through VD1 which is the antiparallel diode of V1.Operating conditions during the negative halfcycle are given in Fig. 5. When V1 is switched on, as shown in Fig. 5(a), the inductor L1 is charged via the diode D1, and the load is compensated by the capacitor C1. When V1 is switched off, as shown in Fig. 5(b), the energy stored in L1 is released through VD2, which is the antiparallel diode of V2, to capacitors C1 and C2 .So, in each halfcycle of the grid, one capacitor of the dclink discharges to provide the energy needed for the compensation, and this energy is actually obtained from the supply source via the charging process described earlier.
Apparently, the charging circuit of the proposed configuration works exactly like a boost circuit and the dc link voltage in this situation is controlled by the duty ratio of the two switches. So, the compensation ability of the SPB AVQR is theoretically unlimited as long as the grid is strong enough to provide the needed power. However, as the boost circuit is parasitic on the series inverter, and the two switches are actually controlled according to the missing voltage, there still exist some restrictions. The relationships between the dc link voltage and other system parameters will be discussed in the next section. In Figs. 4 and 5, two endpoints of the inverter are marked as a and b. Parts of the waveforms obtained at the inverter side and load side under four operating conditions are
Fig. 5. Operating conditions during negative halfcycle. (a) V1 switched on.
(b) V1 switched off.
Schematically shown in Fig. 6, where UaN represents the voltage between a and N. As shown in Fig. 6, when V1/V2 is switched on/off, the dclink voltage will be added/subtracted to the supply voltage to get a switching pulse voltage UaN and the switching harmonics of UaN will be filtered by Lf and Cf to get a smooth load voltage. So, the load voltage will be maintained at its rated value if the inverter is properly controlled according to the required missing voltage during sags.

MODELING AND THEORETICAL ANALYSIS DClink voltage is a key parameter to evaluate the
compensation ability about a series compensation device since
Fig. 4. Operating conditions during positive halfcycle. (a) V2 switched on.(b) V2 switched off.
Fig. 6. Waveforms of supply voltage, load voltage, and UaN. (a) V2 on/off.(b) V1 on/off
it decides the maximum value of the injected compensation voltage. In this section, in order to evaluate the compensation ability of the proposed topology and verify its feasibility in
mitigating long duration deep sags, relationships between the dclink voltage and other system parameters will be derived based on the circuit model of the aforementioned operating conditions. As can be seen from Figs. 4 and 5, working principles during the positive and negative halfcycle of the supply voltage are the same, so the following analysis will be focused on the situation in the positive halfcycle. The control strategy applied for voltage sags is inphase compensation, so the energy needed to maintain the load voltage in one half cycle can be expressed as below equation
WhereT0 is the grid voltage period time, Vref is the rated rms Value of the load voltage, P0 is the rated load power, and V is the rms value of the missing voltage. In steadystate compensation, the energy needed for the compensation should completely be provided by the residential grid which is also the charging energy through the parasitic boost circuit in this case. So the charging energy provided during T0 /2 referred to
as E1 equals to E0. E0 can be easily obtained according to (1), but the calculation of E1 involves with the operating conditions shown in Fig. 4. The simplified circuit model of Fig. 4 is illustrated in Fig. 7, where compensation loop including the filter and the load is ignored and only the charging circuit is considered.
In Fig. 7, VS is the rms value of the supply voltage. Two state equations can be obtained based on Fig. 7 and written in the equation (2)
the analysis will be significantly simplified if some realistic approximations are carried out. Then(2) can be discredited into (3) based on two following assumptions:C1 and C2 are well designed so that Vdc1 and Vdc2 can be regarded equal without considering their ripple voltages; the switching frequency is much higher than the line frequency that the supply voltage in the nth switching cycle can be treated as a constant value
where tonn and toff n are, respectively, the turnon and turn off time ofV2 in the nth switching cycle, Ts is the switching period, Vdc is the steadystate dclink voltage, and Ionn or Ioff n represents the variation amount in charging current during tonnor toff n . As the analysis is within the positive halfcycle of the grid, there exists a constraint: n T0 /2Ts. Apparently, ton and toff n here are actually the inverters duty cycle and they can be expressed as (4) when twolevel symmetric regularsampled PWM method is adopted
The recursion formula of the charging current at the end of the nth switching cycle can be obtained by combining (3) and (4)
Where Ioff n represents the charging current instantaneous value at the end of the nth switching cycle and Ionn can be derived at the same time
The energy stored in an inductor is related to the current that flows through it, so the charging energy provided by the grid via the parasitic boost circuit in the nth switching cycle can be
expressed and then rearranged as equation (7)
Ioff (n1) in (7) can be superimposed according to the recursion formula shown in(5). Before the expression is given, there are some features about the charging current
should be clarified:1) the value of the charging current cannot be lower than zero as the current flowing through a diode is unidirectional; 2)the value of the charging current can either be zero or nonzero and its value always decreases after increasing in one halfcycle of the sinusoidal grid voltage. Then, the nonzero terms of the charging current can be derived as follows:
where n0 is the initial superposition instant and Ioff n is always equal to zero when n is smaller than n0 . So, n0 can be calculated according to (5) and expressed as follows:
Where ceil () represents the rounded up function and the arcsine function here ranges from 0 to /2. Furthermore, when the charging current calculated by (8) decreases to the value no more than zero, n will reach its upper limit denoted by ne. Substituting (6), (8), and (9) into (7), the energy provided by the supply in the nth switching cycle can be written as follows:
E1 now can be obtained if (10) is added with n ranging from1 to T0 /2Ts . So, the overall energy balance equation can be written as follows:
The charging current peak value Imax is considered to arise at the switching cycle after the value of (8) reaches its upper limit. So Imax is expressed as follows:
where nmax is the switching cycle when Ioff n reaches its maximum value and nmax can be written as follows:
So far, the main features of the SPBAVQR topology can be described by (11) and (12). As shown in (11), the dclink voltage is not only related to the supply voltage, but also associated with the charging inductance, load active power, and switching frequency. However, the dclink voltage cannot be obtained directly from (11) as n0 and ne cannot be computed with unknown dclink voltage. So, an iterative algorithm is applied to estimate the dclink voltage, where Ts, VS , T0, Vref, L1 , and P0 are all treated as constants. A flow chart of the adopted calculating method is illustrated in Fig. 8, where Vdc0 is the initial value for Vdc and Vdc is the iterative step. The algorithm is terminated if the error between E0 and E1 is smaller than the error tolerance . Moreover, the charging current can be calculated by (12) and(13) as long as Vdc is obtained .Fig. 9 shows the relationships between the steadystate dclink voltage and the supply voltage with different inductance values obtained according to (11). Other system parameters are listed as follows: P0 = 2 kW, Ts = (1/15000)s, T0 = 0.02 s, Vref= 220
V. The black solid line in Fig. 9 is the VdcVS curve of the DySC topology. As can be seen in Fig. 9, the steadystate dc link voltage of the SPBAVQR under different supply voltage is much higher than that of the DySC topology and it decreases lightly with the falling of the supply. Additionally, when the supply voltage is lower than 50% of its rated value, the dclink voltage of the SPBAVQR is still maintained high enough for the compensation while that of the DySC is too low to mitigating the deep sag. Fig. 9 also indicates that the dclink voltage of the SPBAVQR becomes higher with a lower inductance under the same circumstance. Fig. 10 gives the ImaxVS curve under the same condition. It presents that the steadystate charging current peak value increases with the decreasing of the supply voltage and it can be suppressed by increasing the charging inductance.
Fig. 8. Flow chart for calculating Vdc.
Fig. 9. VdcVS curve of the SPBAVQR with different inductances.
Fig. 10. ImaxVS curve of the SPBAVQR with different inductances.
Fig. 11. VdcVS curve of the PBAVQR with different trigger angles.
Although conclusions drawn from the theoretical analysis for the SPBAVQR can also be applied to the proposed PB AVQR topology, there still exist some differences in their dc link voltages. When the proposed PBAVQR is discussed, the trigger pulse angle for VT3 and VT4 should also be taken into consideration. In the PBAVQR circuit, the charging process begins after the VT3 or VT4 is triggered, so the initial superposition instant n0 in (11) is now determined by denoted by n1 and the energy balance equation is written as follows:
Here, ne is still determined by (8) as aforementioned and
n1can be derived as follows:
Furthermore, the thyristors are triggered only once in each halfcycle and the current through them should be higher than the holding current to maintain the triggered state. So, is required to meet the constraint expressed as follows:
The charging current peak value of the PBAVQR can still be described by (12) as long as n0 is substituted with n1 . As can be seen from (14) and (15), the trigger pulse of the PB AVQR will certainly affect its dclink voltage and charging current. Fig. 11 shows the VdcVS curve under the influence of according to (14). The charging inductor in Fig. 11 is set to 2 mH and other parameters remain the same as those in
Fig. 9. Fig. 11 demonstrates that the steadystate dclink voltage gets higher with a smaller trigger angle as the charging time becomes longer.
Fig. 12. ImaxVS curve of the PBAVQR with different trigger angles.
It also indicates that the PBAVQR is capable of mitigating deep sags with a proper trigger pulse. Fig. 12 presents how affects the ImaxVS curve under the same condition. As shown in Fig. 12, the charging current peak value can be reduced by decreasing with the same supply voltage.
IV. SIMULATION AND EXPERIMENTAL VERIFICATION
In order to show the validity of the proposed PBAVQR, simulation and experimental results are presented in this section. The simulation results are based on the MATLAB software and the experimental results are based on a 2 kW singlephase prototype.

System Parameters
There are mainly four parameters need to be designed, namely the dclink capacitor C1 /C2 , the filter inductor Lf , the filter capacitor Cf , and the charging inductor L1 .
During the steadystate compensation, one capacitor discharges at the switchedon position and two capacitors are both charged at the switchedoff position in each switching cycle. Furthermore, C1 and C2 discharge, respectively, in the negative and positive halfcycle of the supply. So, if the two capacitors are treated equally during the charging process, the energy balance equation that required for the capacitors can be written as
Where vdc is the fluctuation voltage of Vdc. In the theoretical analysis, the dclink voltage is assumed to be a constant. Sovdc/Vdc here is limited within 5% at the voltage drop of 50%to minimize the overall dclink voltage ripple. In this way, the estimated minimum value of C1 /C2 can be calculated according to (17) with Vdc substituted by the dc link set value Vdcset. How to set the dclink value is introduced in [25] and in this paper it is given as
TABLE I SYSTEM PARAMETERS
Fig. 13. Simulation result of the DySC.
As shown in Figs. 912, a higher dclink voltage will be obtained with a smaller L1 , but the peak value of the charging
current will get larger at the same time. So, charging inductanceL1 is designed as a result of the compromise between the compensation ability and the charging current peak value. The main function of the output LC filter in the proposed structure is to eliminate the harmonic components of the injected compensation voltage. The value of Lf and Cf are designed according to its natural frequency and several other criterions which are given as follows:
Where fs is the switching frequency, vL is the voltage drop Across the inductor Lf at IL max, IL max is the maximum value of the load current, I ripple is the maximum ripple current of the filter and is the coefficient between the switching frequency and the filters natural frequency. Generally, ranges from 0.05to 0.2.
The PBAVQR systems key parameters are listed in Table I according to the design principles mentioned earlier.

Simulation Results/p>
Fig. 13 shows the simulation results of the DySC topology with different supply voltages. In the simulation, the supply voltage drops to 180 V at 0.1 s and then falls to 100 V at 0.4 s.
As shown in Fig. 13, when the supply voltage is 180V, the DySC can effectively compensate for the voltage sag; however, when the supply voltage drops to 100 V, the load voltage becomes not sinusoidal as the maximum injected compensation voltage is limited by the low steadystate dc link voltage. Fig. 13 also indicates that the DySC can only mitigate deep sags for a few line cycles depending on the energy stored in dclink capacitors as its steadystate dclink voltage is always lower than the peak value of the supply voltage. The graphics of the active and reactive power are also included in Fig. 13. When the supply voltage is 180 V, the dclink voltage does not reach its steady state value with limited simulation time, so the active power of the supply is lower than the load power and its value is about1.6 kW. When the dclink voltage reaches its steadystate value with 100 V supply voltage, the active power of the supply is about
1.65 kW which means that the load voltage is no longer maintained.
Fig. 14. Simulation result of the PBAVQR.
The simulation results of the proposed PBAVQR topology under the same condition is shown in Fig. 14. As can be seen in Fig. 14, when supply voltage changes, the dclink voltage precisely tracks Vdcset according to (18) and it also remains enough high for the compensation even with a 100 V supply voltage. Fig. 14 also indicates that the transient response here is not very good, but this can be improved by increasing the set value for dclink voltage. The active power of the supply during the steadystate compensation is 2 kW, and it is the same as the load power which means that the load voltage is effectively ensured. The reactive power during the steady state compensation is about 1.1 kvar with 180 V supply and is about 1.4 kvar witp00 V supply. The reactive power of the proposed PBAVQR is higher than that of the DySC due to the dclink voltage adaptive control method. Additionally, the instantaneous value of the active and reactive power can be suppressed by properly designing Vdcset and the charging time of the capacitors. Fig. 15 show strigger pulses for thyristors under different grid voltage. The supply voltage is 180 V in Fig. 15(a) and is 100 V in Fig. 15(b).As shown in Fig. 15, the trigger angle becomes smaller to ensure the compensation energy needed when the grid voltage decreases.
(a)
(b)
Fig. 15. Trigger signals under different supply voltage values. (a) 180Vsupplyvoltage. (b) 100 V supply voltage.
V. CONCLUSION
This paper has presented the active voltage quality regulator with dclink capacitor boost circuit to mitigate long duration deep voltage sags. The proposed PBAVQR topology is derived from the DySC circuit and the compensation performance is highly improved without increasing the cost, weight, volume, and complexity. It is relatively costeffective solution for deep sags with long duration time compared with the traditional DVR topology with loadsideconnected shunt converter as a series transformer is no longer needed. The working principle and circuit equations are given through theoretical analysis. Simulation and experimental results are presented to verify the feasibility and effectiveness of the proposed topology in the compensation for long duration deep voltage sags that are lower than half of its rated value. The operating efficiency of the proposed PBAVQR system also remains at a relatively high level as the dclink voltage adaptive control method is adopted. Ina conclusion, the proposed PBAVQR topology in this paper provides a novel solution for long duration deep voltage sags with great reliability and compensation performance.
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