Standard Cell Library Development

DOI : 10.17577/IJERTV8IS070093

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Standard Cell Library Development

Sumukha M

B.E Student

Sangmesh Melinmani

Assistant Professor Electronic and Communication

Dayanand Sagar College of Engineering Bangalore, India

Manasa C K

B.E Student

Electronic and communication Dayanand Sagar College of Engineering Bangalore, India

Electronic and communication Dayanand Sagar College of Engineering Bangalore, India

Abstract: A Standard Cell Library(SCL) is collection of cells that can be synthesized to a larger design, which is described with a hardware description language. We present the design of 1.8V High Density 9 track SCL in UMC180nm technology. Here we generate comprehensive library containing core number of necessary cells, providing detailed layout, schematic, symbol and abstract views, which are characterized for three process corners for timing and functional properties.



The complexity of modern IC design and the market pressure to produce designs rapidly, has led to the extensive use of Semi custom design. Semi custom design is a methodology for making an integrated circuit in which a portion of the circuit function is predefined and unalterable, while other portions can be configured to meet the specifications. Designers can therefore design ASICs themselves, using SCL.

SCL is a collection of cells that can be synthesized to a larger design, which is described with a hardware description language. SCLs are used for a large range of applications. The use of a SCL drastically reduces the cost of designing a chip. It also reduces the time-to-market, which results in lower production cost, early sales, longer time in marked, etc. The economic and efficiency of an ASIC design depends heavily upon the choice of the library. Hence it is important to build library that full fills the design requirement.

In this work we present the development of high density SCL in UMC180nm technology. We generate a comprehensive library containing core number of necessary cells, providing detailed layout, schematic, symbol and abstract views, which are characterized for the three process corner. The electrical and physical characteristic of the SCL are provided in .LIB and LEF format respectively. The library is designed using Cadence tools. We have designed a high density SCL for the specifications as show in Table I.

Table I : Specifications


    In the present work we design a SCL which includes combinational, sequential and special cells of different drive strengths. The cell list is listed in Table II. The cells are designed for various drive strength so as to achieve maximum performance at minimum area. When the synthesizer compiles the design from a behavioral description into a collection of standard cells, often large nets are created, i.e. many gates connected to a single net. The greater the number of devices connected to a net, the greater drive strength required to sustain maximum clock speed. This also happens as the P&R tool wires in the standard cells. As a result, we need to design cells with a wide range of buffer drive strengths in the library, in order to support the synthesizer and P&R tool in the optimal buffering of large nets. Having different implementations of each cell improves the performance of the circuit that may achieve near full- custom performance designs. That happens because when the cell does not need to drive a big load, a small transistor version can be used, which leads to lower power consumption. On the other hand, for instances that need to drive a large load, a cell with larger transistors can be employed to improve performance. Therefore, an indispensable step for the design of a SCL is to define different output driving strengths.

    The typical design flow of a SCL consists in designing a set of logical gates at the transistor level for a given technology process. Fig.1 shows an Overview of the steps required to design SCL and the tools used for the same. The design starts from a specification, defining logical and electrical parameters like propagation delay and power consumption. From these, the Schematic is designed to meet the required specifications. Then the layout is drawn for each of the cells designed. Once the layout is DRC and LVS clean, the extracted circuit is obtained through an automated extraction tool. This circuit contains not only the drawn transistors but also every parasitic generated from the physical layers. In this way, a more realistic view is obtained, and with it, simulations are performed to characterize the electrical behavior of the designed gate. The output of the characterization is store in .LIB format that can be used by the synthesizer. After the characterization if the required specification are not met then the layout is altered and again re-characterized. With this electrical characteristic of each gate, a circuit can be synthesized from a high level description. Once the cells are characterized an abstract view of the layout is generated by the abstract generator. With the abstract views the P&R tool can easily assemble the IC from these predesigned blocks. The physical characteristics of the cells are in the .LEF file.

    Fig.1 Design Flow of a Standard Cell Library and the Tools used.


A . Schematic design:

The design of the SCL begins with the sizing of the transistor so as to meet certain constraints. The constraint that has to be taken care while designing the combinational cells is that the average delay of the cell should be minimum. So, we set the beta ratio and stage ratio for the entire library such that the average delay is minimum for each cell. Once we fix the beta and the stage ratio the design of combinational cells is done. The constraint that has to be taken care while designing the sequential cells is that the timing of setup0 and setup1 should be same. And in clock inverter and clock buffer we should see that the rise delay and the fall delay are equal.

  1. Beta Ratio Calculation:

    Beta ratio is the ratio of PMOS width (Wp) to NMOS width (Wn) in the CMOS process. To calculate the beta we simulate the cell for all the possible values of the MOS widths in the real time scenario and tabulate the rise and fall delay. The real time scenario which we have used is FO3 chain. FO3 chain is arrangement of cells as shown in Fig.2. We calculate the delay at the middle of the chain. The significance of using the FO3 chain is that it eliminates the effect of the input slew after 4 to 5 stages. So the rise delay and fall delay are calculated at the 5Th stage of the chain.

    Fig.2: FO3 Chain of the INV

    The Beta ratio is fixed for the library. The perl code is written to create the FO3 deck of the cell. The deck sweeps the value of the MOS widths and measures the rise delay and fall delay for each value of the MOS width. Then we calculate the average delay for all the values of the MOS width. The ratio of Wp to Wn at which the average delay is minimum is defined as the beta ratio for that cell. In order to obtain a more reliable Beta ratio for the entire library we consider the following cells: INV, NOR and NAND of different drive strengths. NAND and NOR cells are converted as an inverter and placed in the FO3 chain. Each of the cells will have different beta at which the performance loss is zero for that particular cell. Once the beta ratios of all the cells are calculated we tradeoff between the performances of the different cells to decide a single beta ratio for the library. The differen beta ratio and the corresponding performance loss for different cells are as shown in the Table

    1. We should set the beta in such a way that the performance lose of all the cell must be feasible.

      TABLE III : Comparison of Performance loss for different Beta ratios of different

  2. Stage ratio calculation:

    In certain combinational cells like buffer there are 2 stages. In this the output stage should have the strength to drive the output load. But for the input stage it is sufficient if it has the strength to drive only the output stage and thus it can be sized smaller then the output stage. Doing this would reduce the power. Likewise if there are more number of stages, the transistors in the output stage are set as per the beta value and the previous stage transistors are sized only to drive the next stage. The ratio of the Wp of the output to the Wp of the previous stage is called the stage ratio. The stage ratio is also fixed for the library. Stage ratio calculation steps are same as that of the beta ratio calculation; the only change is the transistor whose value has to be varied. For stage ratio calculation we consider the following cells: BUFFER, AND and OR of different drive strengths. The MOS widths of the output stage are kept as per the beta set for the library and vary the MOS widths of the input stage. Stage ratio is set at which the performance loss is less and power gain is maximum. Comparison of performance loss and power gain for different stage ratios of different cells is as shown in the Table IV.

    TABLE IV : Comparison of Performance loss and Power Gain for different Stage ratios of different cells.

  3. Sequential cells:

In sequential circuit design the constraint on setup time and hold time is determined by delay tolerance-based binary search method that is the setup time should also be such that it does not degrade the Clock-Q propagation time beyond a pre-determined tolerance value. In library characterization, to ensure that set up time chosen is not so close to the switching point that the simulation fails, it performs a delay tolerance check by multiplying the delay from clock to the output Q by factor specified. As soon as the CK-Q delay is more than delay tolerance variable, the simulation is considered as fail. The setup time is the time during which the input data to the input of the sequential logic must remain stable prior to the arrival of the clock so that the correct value is latched at the output. Hold time is defined as the minimum time that an input signal must remain

stable after the active clock signal to ensure that input value is correctly latched at the output.

Fig.3 Setup and Hold time constraints for a positive edge triggered flip- flop.

4 . Clock inverter and Buffers:

The clock signal is another very large net that regularly requires very high drive currents. These nets are broken down into simpler nets and designed as a tree. But, there are skew problems which are frequently made worse just by adding buffers. Skew is the time difference between the clock signals arriving at different clocked elements in a chip. The Place and Route tool automatically designs a balanced clock tree, and then adjusts the buffers depending on the load a particular clock net sees to partially compensate the skew differences. For this effort the library needs specific cells referred to as the clock buffers. Clock buffers have high drive strength and near equal rise and fall time.

B. Layout Architecture :

In layout architecture we first define the routing grids. Routing grids are used by CAD tools to route wires over the standard cells placed in the design. The PNR tools use these routing grids as a reference to place the cells. The grids are defined with respect to the cell origin. These grids can be offset from the origin however by exactly half the grid spacing as shown in Fig.4. The intersection of horizontal and vertical grids is called hit point. And the pins within the cell except for abutment type of pins i.e., power rail should be placed on the hit point. So that the P&R tool can easily have access to the pins. Using grid offset can increase the number of hit points as shown in Fig.5. The cell height must be a multiple of horizontal grid spacing and cell width is multiple of vertical grid spacing. Grid spacing must be defined for each routing layer. Grid spacing needs to be at least line-on- via, and are usually via-on-via.

Fig.4: Vertical and Horizontal grids with and without Offset

Fig.5: How Grid Offset Increases number of hit points.

There are three types of pitch at shown in Fig.6. We calculate the pitch for all the 3 types of pitch, with different orientations of via and then decide on the final pitch considering the pitch value, number of VIAs we can place and the height of the cell. Pitch calculation for different orientation are tabulated as shown in TABLE V.

Fig.6: Types of Pitch

From the above table we can see that if we choose x-pitch

=0.6 and y-pitch= 0.6 we can have more number of VIAs. Track is approximately the minimum spacing i.e., the pitch in the technology node. Track is generally used as a unit to define the height of the standard cell. A 12 track cell will be taller than a 9 track cell. A 12 track standard cell will be taller means more metal1 routing space is available within the cell, hence cells will be faster. Where as in a 9 track cell the cell will be compact but speed is less compared to 12 track. Once we decide the pitch and routing grids, the cell height is fixed with the following equation.

Cell height = Number of track * y-pitch

= 9*0.6 = 5.4

TABLE V : Pitch Calculation for different Orientation





Line to Line



Line to VIA
















Fig.7: Layout Architecture

Then we calculate the power rail width. Once the layout architecture is decided we draw the layout for all the cells. And verifications are performed to ensure that each cell in the library passes Design Rule Check (DRC) and Layout Versus Schematic (LVS) checks. When the layouts are DRC and LVS clean a circuit extractor tool must be used to scan the different layers of the physical design and extract the parasitic elements in this geometrical description. The generated circuit contains not only the transistors that implement the logic of the gate, but also every parasitic element, like the capacitance between the gate and the bulk. This allows a more accurate simulation and analysis of the designed circuit.


    1. Characterization:

      Upon completion of the physical implementation, cell characterization is performed to generate timing models of the library that are used for synthesizing behavior codes of a design and also the timing optimization during the P&R step. Once the results of library characterization are obtained, it is verified whether the required specifications are met. If not changes are made in the layout and again the library is characterized. To obtain realistic manufacturing process characteristics, circuit simulation is performed for the three process corners at shown in TABLE VI for the range of input slew and output load capacitance. The characterization is done using an automatic cell characterization tool. After characterizing, the cells functional description and timing data are transformed to a standard industry file format, Synopsys Liberty format (or *.lib file). This data is used by other design tools like synthesizer and the P&R tool. The final requirement is a documentation that summaries the functionality and timing of each cell. The functionality is frequently described with truth table, and timing data is presented in a simple format in the datasheet.

      TABLE VI : Voltage and Temperature for different Process






      Voltage (volts)




      Temperature( C)




      B . Conceptual

      Along with the timing library, the P&R tool also requires a physical description of the library that includes definitions of blockages, information regarding routing layers, pin information and to avoid the generation of shorts among the cells when routing the cell interconnection. Once a cell is fully verified, an abstract view can be generated. Cadence Abstract generator is used to generate the physical description i.e., the abstract view and the Layout Exchange Format (LEF) file for all the cells. These are required for placing and routing of the final chip by the P&R tool.


The work described in this document has produced a 1.8V Digital Standard Cell Library for UMC180nm CMOS process, operating at -40C to 125C temperature. In total this library has 104 cells which include logical cells, sequential cells and special cells which are listed in Table I. Each cell has the following views: schematic, symbol, layout and abstract. Results of AND2_x1 cell is as shown in figures below. For each standard cell, physical characteristics are given in a LEF file, which is used in the automation of the design of standard cell based ICs and is widely accepted among CAD tools. Each standard cell has its electrical characterization for three different process corners [TABLE VI], for a range of input slew and output load. This information is given in a LIB format as shown in Fig.9, which is used by synthesis tools to generate the net list of circuits. Fig.10 shows the rise delay, fall delay, rise transition and fall transition for different output capacitance and slew.

TABLE VII : Layout Architecture values

Fig.8 Schematic of AND2_x1

Fig.9 Symbol of AND2_x1

Fig.10 Layout of AND2_x1

Fig.11 Abstract view of AND2_x1

Fig.12 Datasheet of AND2_X1

Fig.13. Rise delay, fall delay, rise transition and fall transition for different values of output capacitance and slew


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