Quasi Z-Source Extended Boost Inverter with Active Z-Network Switch

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Quasi Z-Source Extended Boost Inverter with Active Z-Network Switch

Mr. Nathrao V. Munde Electrical Engineering Department Walchand College of Engineering Sangli, India

Dr. Ramchandra P. Hasabe Electrical Engineering Department Walchand College of Engineering Sangli, India

AbstractA novel configuration for a quasi-Z-source extended-boost inverter with an active Z-network switch is discussed in this paper. The suggested topology of the inverter, in comparison with Enhanced-Boost Quasi-Z-Source Inverters (EB-QZSI) which have two switched impedance networks, achieves the same boost factor with one extra switching device along with a reduction of two LC pairs and one diode. Besides, the current stress around switches is halved, which results in a larger reduction in switch conduction loss. Due to a reduction in losses, the efficiency of the proposed inverter is improved. Also, the proposed inverter maintains a common ground between the inverter bridge and the source. Besides, the input current is continuous for the proposed inverter. The operation principles of the suggested topology are described below. Some points of differences and similarities in the EB-QZSI and the suggested inverter topology are also described in the paper. The simulation results of the suggested topology are achieved. all the results are checked using theoretical analysis.

Index Terms Impedance network, quasi-Z-source inverter, active switched

  1. INTRODUCTION

    In fuel cell and solar systems which are renewable energy systems, the Z-source inverter (ZSI) seems to be a very successful topology as discussed in [1]. ZSI contains unique qualities, which are not obtainable from a conventional current source or voltage source converter. To reduce the conceptual and theoretical problems which are present in conventional current source (CSI) and voltage source converter (VSI) [2], a Z-source converter is used. The Z-source converter eliminates the logical and technical obstacles and drawbacks of the conventional current source converter and voltage source converter. For any power conversion, the Z-source can be applied. Turning on of the switches in the same leg simultaneously is possible in the Z-source inverter that too without dead time. This is not allowed in conventional VSI and CSI. ZSI also has the buck-boost capability with improved reliability of the converter.

    Given the above benefits, the ZSI also suffers from certain disadvantages such as a discontinuous input current due to the

    the impedance network. However, the drawbacks are input current is discontinuous and still, there is no common ground between dc link and power supply.

    To reduce the passive elements of the impedance network a switched boost inverter (SBI) is invented. SBI adding only one extra active switch to reduce the passive components. The boost factor of the SBI is the same as ZSI. By reducing the passive components significant reduction in volume, weight, and converter cost is achieved in [5] and [6]. To improve boost inversion ability, high voltage-gain switched Z-source inverter (HVG-SZSI) in [7] is invented. this topology brings together SBI and QZSI. But the problem with sharing common ground persists.

    1

    =

    1 4 + 22

    (1)

    1

    =

    1 4 + 22

    (1)

    By using cascaded networks, voltage gain can be improved. Extended-boost ZSIs in [8] have four families. With the addition of LC pairs and diodes to the QZSI, other families can be realized to improve boost ability. Besides, voltage stress across the capacitors is reduced in comparison to the conventional ZSI. The boost factor of enhanced-boost Z-source inverter with switched Z-impedance (EB-ZSI) in [9] is very high and its expression is given in (1).

    where stands for boost factor and the shoot-through duty cycle is represented by . The proposed topology also suffers from certain drawbacks such as different ground points between dc supply and inverter bridge and the input current is discontinuous. To overcome these drawbacks a new topology enhanced-boost quasi-Z-source inverter (EB-QZSI) is proposed in [10]. The proposed inverter provides continuous input current by using two switched impedance network. The proposed inverter escapes the above-mentioned disadvantages in [9] and maintains a high boost factor. Fig. 1 shows EB-QZSI with continuous input current configuration. To get a high boost factor, both [9] and [10] use four inductors and four capacitors due to which it becomes bulkier and heavier leading to an increase in converter cost.

    input diode in between input power supply and dc connection, failure to share a common ground in between them. To solve these issues, [3] a class of quasi-Z-source inverter (QZSI) is invented for joint earthing and continuous current characteristics with reduced ratings of components and source

    L1 D1

    Vi + +

    D3

    L2 Din

    C4 D4

    L3 D2 L4

    S1 S3

    – +

    + C2 a

    V

    tension, but no improvement in boost factor is achieved when

    – – C3

    – C1

    PN Cf R vo

    compared to the original ZSIs. To achieve a high boost factor, extended boost topologies have emerged. The proposed inverter in [4] is able to improve voltage boost ability with switched inductor (SL) cells used in place of two inductors in

    S2 S2

    b

    b

    Fig. 1.Enhanced-boost quasi-Z-source inverter for continuous input current configuration using two switched impedance networks [10].

    2

    A new quasi Z-source extended boost inverter with an 2 = 2 = 2

    (5)

    2

    A new quasi Z-source extended boost inverter with an 2 = 2 = 2

    (5)

    active Z-network switch is introduced in this paper. Proposed topology overcomes the above-mentioned disadvantages of a traditional ZSI. The proposed inverter reduces two inductors,

    When all switches in one leg are turned OFF, peak dc-link voltage ( ) is zero.

    two capacitors, and one diode and adding only one extra switch as compared with EB-QZSI. The boost factor of both the topologies is the same. The proposed topology has all the

    = 0

    (6)

    = 0

    (6)

    + VL1 –

    L1

    D4 D1

    + VL2 –

    L

    – VC1 +

    C1

    iPN

    advantages that are present in EB-QZSI such as, the input 2

    current is continuous, double-ground features, etc. Also, the current stress around switches is halved, resulting in a large reduction in switch conductive loss and an improvement in overall inverter efficiency. The principles of operation are evaluated in section II. The EB-QZSI and suggested topology are compared with each other in section III. The theoretical testing of the proposed inverter is performed in section IV with simulation results.

    Vi +-

    iL1

    D3

    2

    2

    iC C2

    iL2

    +

    VC2

    D

    S

    D2

    (a)

    D1

    iC1

    VPN=0

  2. PROPOSED TOPOLOGY

    Fig. 2 displays the suggested topology structure consists of two inductors (1 , 2 ), two capacitors (1 , 2 ),

    + VL1 –

    L1

    4

    + VL2 –

    L2

    – VC1 +

    C1

    four diodes (1, 2, 3, 4), and one active witch(), couples the source voltage to the dc link. A low pass filter (, ) connects the dc link to the load . Remember that in this paper evaluation is done using a single-phase H-bridge inverter but the suggested topology can also be extended to three-phase circuits

    Vi +-

    iL1

    D3

    C2

    iC2

    iL2

    + S

    VC2

    D2

    iC1

    VPN

    iPN

    D4 D1

    – +

    Fig. 3. Corresponding circuits of the proposed topology. (a) Shoot-through state and (b) non- shoot-through state

    L1 D3 L2

    +

    C

    S C1 S1 S3

    i

    2) Non-shoot-Through State

    – 2

    Vi + V a

    Lf o

    b

    b

    +

    Non-shoot-through state conditions are shown in Fig. 3

    – D2

    PN Cf R vo

    (b). In this state the switch S and diode 4 are turned OFF and

    S2 –

    diodes , , and

    are switched ON. The source charges

    S2 1 2 3

    Fig. 2. Quasi Z-source extended boost inverter with Active Z-network switch

    1. Operation Principles

      For study purpose, there are two operative conditions of the proposed inverter that is shoot-through state and non-shoot through state. operation principles of traditional ZSI and proposed inverter are similar. Fig. 3 (a) and (b) displays the proposed inverter's corresponding circuits for the duration of the shoot-through and non-shoot-through conditions, accordingly,

      1. Shoot-Through state

        When all the switches in any leg are switched ON simultaneously, the inverter bridge is short-circuited as shown in fig.3 (a). this condition is called as a shoot-through state. The diode 4 and switch S is switched ON and the diodes 1,

        1

        1 = 1 = + 1

        (2)

        2

        2 = 2 = 1 + 2

        (3)

        1

        1 = 1 = 1 2

        (4)

        1

        1 = 1 = + 1

        (2)

        2

        2 = 2 = 1 + 2

        (3)

        1

        1 = 1 = 1 2

        (4)

        2, and 3 are biased in reverse. Via capacitors, inductors are charged in the shoot-through state. The two inductor voltages (1, 2) and two capacitor currents (1 , 2 )are derived in this state. Power is not transferred to the load , because the inverter bridge is a short circuit in this state.

        the capacitors via inductors. During this state, power is transferred to the load which is stored in the inductors, inverter bridge is open-circuited. In this state, the voltage and current relationship can be written as

        1

        1 = 1 = 2

        (7)

        2

        2 = 2 = 1 + 2

        (8)

        1

        1 = 1 = 1 _

        (9)

        2

        2 = 2 = 1 2

        (10)

        Where _ stands for average dc-link current in the non- shoot-through condition.

        The maximum dc-link voltage is equivalent to the capacitor voltage 1 .

        = 1

        (11)

    2. Boost Factor Derivation

      Once the voltage balance principle is applied for the inductor 1 from (2), we obtain

      = (1 D)2 1

      (12)

      From (3), applying the volt-sec balance law to the inductor

      2, we have

      2 = (1 2D)1

      (13)

      The voltage across the capacitor 1 is obtained by putting

      1

      1 = 1 4 + 22

      (14)

      1

      1 = 1 4 + 22

      (14)

      (13) into (12), we have

      1 2

      2 = 1 4 + 22

      (15)

      1 2

      2 = 1 4 + 22

      (15)

      Substituting (13) into (14), yields

      = 1 2

      1 4 + 22

      (16)

      = 1 2

      1 4 + 22

      (16)

      In non-shoot-through condition, the peak dc-link voltage across the converter bridge can be derived from (11) and (14), we have

      Thus, the boost factor of the suggested inverter can be expressed as

      1 2

      = =

      1 4 + 22

      (17)

      where is the duty ratio. The value of is between 0 to 0.29

    3. Control Strategy for the proposed topology

      0

      = =

      (18)

      0

      = =

      (18)

      In this paper, switches are controlled using control signals generated using the PWM control technique. Voltage gain of the Single-phase dcac converter is obtained by

      Where stands for the modulation index, is the boost factor and the peak output voltage is represented by 0. Boost factor is dependent upon the PWM control technique. From (18), when the boost factor is high, automatically voltage gain

      is high. Simple boost control (SBC) in [6] is used in the proposed inverter. as shown in fig.4, in one switching cycle two shoot-through states occur. By using the SBC, current stress around the switches is halved as compared with the control method in [5]. In a shoot-through state, a two-phase leg is switched ON simultaneously under the SBC although the only one-phase leg is switched ON in control technique [5]. By controlling the modulation index, we can control the duty ratio in SBC as follows:

      1

      Fig. 4 shows the PWM control technique for the proposed inverter [6]. Two modulating waveforms, i.e., and

      2

      1 = (1 4 + 22)2 2

      (24)

      (1 )2

      2 = (1 4 + 22)2 2

      (25)

      2

      1 = (1 4 + 22)2 2

      (24)

      (1 )2

      2 = (1 4 + 22)2 2

      (25)

      , are related with a high-frequency triangular

      Fig. 4. PWM control for the proposed inverter.

    4. Inductors and Capacitors Design

    2(1 )2

    1 = (1 4 + 22)

    1

    (19)

    2(1 )

    2 = (1 4 + 22)

    2

    (20)

    2(1 )2

    1 = (1 4 + 22)

    1

    (19)

    2(1 )

    2 = (1 4 + 22)

    2

    (20)

    During shot-through state the inductor currents rise linearly according to the above activity concepts. Therefore, the current ripple of inductors can be obtained in terms of (2), (14), and (15) as follows:

    where represents the number of shoot-through states within one switching cycle. Under the suggested topology SBC approach, = 2. Thus, the inductors 1 and 2 can be obtained by

    2(1 )2

    1 = (1 4 + 22)

    (21)

    1

    2(1 )

    2 = (1 4 + 22)

    2

    (22)

    2(1 )2

    = (1 4+ 22)

    1

    (23)

    2(1 )2

    = (1 4 + 22)

    1

    (23)

    The average current of the input supply can be achieved under lossless conditions as (23)

    The average input source current is equal to the average inductor 1 current, applying the capacitor charge balance theory from (4), (5), (9), (10), and (23), the average inductor currents can be extracted as follows:

    waveform, i.e.,

    , to produce pulses. This pulse is used to

    operate the switches 1, 2, 3, and 4 . Compared to another triangle waveform (dashed line) with a double frequency and half of the amplitude of that of , a constant voltage is produced for the 0 switch. The 0 a control signal is then passed through the OR logic gate to produce the shoot-through states in the inverter bridge into the control signals of switches

    1 to 4.

    In addition, The average non-shoot-through dc-link current may be written as

    2

    _ = (1 )(1 4 + 22) 2

    (26)

    According to (4), (5), and (24), (25), voltage ripple of the capacitors can be produced as follows:

    (2 )2

    1 = (1 4 + 22)2 2

    1

    (27)

    (1 )2

    1

    1

    Parameter

    EB-QZSI

    Proposed

    1

    1 4 + 22

    1

    1 4 + 22

    Capacitor 1

    voltage

    (1 )2

    2

    (1 )

    (1 2)

    3

    (1 3 + 2)

    4

    (2 )

    2(1 )

    2(1 )

    ,

    (1 )2

    Diode 1,2

    stresses

    (1 )

    3

    2(1 )

    4

    2

    ,

    Switch

    stresses

    14

    ,

    Parameter

    EB-QZSI

    Proposed

    1

    1 4 + 22

    1

    1 4 + 22

    Capacitor 1

    voltage

    (1 )2

    2

    (1 )

    (1 2)

    3

    (1 3 + 2)

    4

    (2 )

    2(1 )

    2(1 )

    ,

    (1 )2

    Diode 1,2

    stresses

    (1 )

    3

    2(1 )

    4

    2

    ,

    Switch

    stresses

    14

    ,

    2 = (1 4 + 22)2 2

    (28)

    TABLE IV. COMPARISON OF VOLTAGE STRESS IN THE SAME BOOST FACTOR AND INPUT VOLTAGE

    Therefore, the capacitors can be designed by

    (2 )2

    1 = (1 4 + 22)2 2

    (29)

    (1 )

    2 = (1 4 + 22)2 2

    2

    (30)

    (2 )2

    1 = (1 4 + 22)2 2

    (29)

    (1 )

    2 = (1 4 + 22)2 2

    2

    (30)

    1

    2

  3. COMPARISON OF PROPOSED TOPOLOGY WITH EB-QZSI

    The proposed topology is compared with the enhanced- boost quasi-Z-source inverter for continuous input current configuration (EB-QZSI) which have two switched impedance networks [10]. Detailed comparison of the topology characteristics as shown in table I.

    1. Topology characteristics

      Topology Characteristics

      EB-QZSI

      Proposed

      No. of Inductors

      4

      2

      No. of Capacitors

      4

      2

      No. of Diodes

      5

      4

      No. of Switches

      0

      1

      Common Ground

      Yes

      Yes

      Starting inrush current

      No

      No

      Continuous input current

      Yes

      Yes

      Input current ripple

      Approximate zero

      Approximate zero

      Boost factor

      1

      1 4 + 22

      1

      1 4 + 22

      Topology Characteristics

      EB-QZSI

      Proposed

      No. of Inductors

      4

      2

      No. of Capacitors

      4

      2

      No. of Diodes

      5

      4

      No. of Switches

      0

      1

      Common Ground

      Yes

      Yes

      Starting inrush current

      No

      No

      Continuous input current

      Yes

      Yes

      Input current ripple

      Approximate zero

      Approximate zero

      Boost factor

      1

      1 4 + 22

      1

      1 4 + 22

      TABLE I. COMPARISON OF TOPOLOGY CHARACTERISTICS

      Detailed comparison of the topology characteristics as shown in table II. when comparing the topology characteristics, LC output filter, and switches of the inverter bridge are not taken into account. It can be found from the table III that the boost factor of the proposed topology and EB-QZSI is the same. However, the proposed inverter reduces two inductors, two capacitors, and one diode as compare to EB- QZSI. To reduce these passive components, proposed topology adding just one switch into the circuit. Input current ripple in both the topologies is approximate zero. Advantages of the EB- QZSI is no start-up inrush current, common ground between source and inverter bridge, input current ripple is approximate zero, and input current is continuous. These are all advantages also present in the proposed inverter by using less passive components.

    2. Voltage and Current Stresses

      By using the same boost factor and input voltage, the proposed inverter compares voltage stresses across diodes, capacitor voltages, and switch stresses with EB-QZSI as shown in Table . In proposed topology, The voltage stresses

      For comparison purposes, te same input voltage, voltage gain, and load are taken in proposed and EB-QZSI as shown in the table. The control technique of both the inverters is different, because of this the stress across the switches is not the same. In the proposed topology SBC control method [6] is used and in EB-QZSI control method [5] is used. By using the SBC control method [6], the current stress around the switches is reduced by halved as compared to the control method [5] as shown in table . Inductor currents of both the topologies are equal, under the same operating condition. It is envisaged that the current stress across the diodes is generally less than that of EB-QZSI.

      Parameter

      EB-QZSI

      Proposed

      2(2)

      2(2)

      [2(1 )]

      [2(1 )]

      Inductor currents

      1,3

      2,4

      (1 )

      (1 )

      Diode stresses

      1

      1

      2

      2

      1

      2

      3,4

      1

      1

      2

      ,

      (1 )2 [2(1 )

      22

      Switch stresses

      1 + 2

      Parameter

      EB-QZSI

      Proposed

      2(2)

      2(2)

      [2(1 )]

      [2(1 )]

      Inductor currents

      1,3

      2,4

      (1 )

      (1 )

      Diode stresses

      1

      1

      2

      2

      1

      2

      3,4

      1

      1

      2

      ,

      (1 )2 [2(1 )

      22

      Switch stresses

      1 + 2

      TABLE V. COMPARISON OF CURRENT STRESS IN THE SAME VOLTAGE GAIN, INPUT VOLTAGE AND LOAD

      across the capacitors 1

      and 2

      is higher than the EB-QZSI.

      But the entire voltage stress across the capacitors in both the topologies are identical. Because the proposed inverter uses only two capacitors and the EB-QZSI used four capacitors. As shown in table the voltage stress around the switches is the same in both the topologies. The total voltage stress across the diodes is identical in both the topologies as shown in table .

    3. Inductance and Capacitance

    From table , the voltage stress across the inductors of the proposed inverter is double as compared to EB-QZSI. Current stress across the inductors is the same in both topologies, as shown in table . In other words, with the same operating conditions, the inductance of the suggested topology is double than EB-QZSI and the capacitance of the proposed topology is the same as EB-QZSI.

    TABLE VI. COMPARISON OF INDUCTANCE AND CAPACITANCE

    Parameter

    EB-QZSI

    Proposed

    1,3

    (1 )21

    2(1 )21

    2,4

    (1 )2

    2(1 )2

    1,4

    (2 )22(21)

    2,3

    (1 )22(22)

  4. SIMULATION RESULTS OF THE PROPOSED INVERTER

    Simulation results are given to validate the process and efficiency of the proposed topology. Table displays the circuit parameters used to simulate the proposed topology.

    TABLE VII. PARAMETERS USED FOR SIMULATION

    Parameters

    Values

    Input voltage ( )

    50 V

    Output voltage()

    100

    Fundamental frequency ()

    50

    Switching frequency ()

    10

    Inductors (1 = 2)

    2 mH

    Capacitors (1 = 2)

    470

    Output filter inductor ()

    4.6 mH

    Output filter capacitor ()

    10

    Load resistance ()

    50

    The simulation results for the proposed topology are shown in Fig. 5. The suggested topology has been simulated using MATLAB / Simulink on the open-loop configuration. The control method [6] is used to simulate the proposed topology. To boost the input voltage, D = 0.2 and M = 0.8 is taken. RMS output voltage across the load is roughly 101 V and dc-link voltage is approximately 178V as shown in fig.5 (a). To provide a pure AC supply to the load, the LC filter is connected as shown in fig.2. The value of output filter inductor () and capacitor () are 4.6 mH and 10 respectively as shown in table VIII. the voltage across capacitor Vc1 and Vc2 are approximately 180 and 108 V respectively, as shown in fig.5 (a). These results are matched with theoretical values (14) and

    (15) respectively. The values of both the Inductor currents 1 and 2 are increases in shoot-through state linearly. as shown in fig. 5 (b). In non-shoot-through condition, inductor current decreases linearly. Accordingly, the above operational criteria in section are well confirmed over the analysis of the following simulation.

    14

    1 + 2

    1 + 22

    ,

    (2 ) 22

    (2 ) 22

    14

    1 + 2

    1 + 22

    ,

    (2 ) 22

    (2 ) 22

    (a)

    (b)

    Fig. 5. Simulation results of the proposed topology with = 50 V, = 0.2 and = 0.8. (a) From top to bottom: Output voltage of inverter bridge (), output voltage (), and capacitor voltages (1, 2 ), respectively. (b) From top to bottom: dc-link voltage () and inductor currents (1, 2 ), respectively.

  5. CONCLUSION

In this paper, a new Quasi Z-source extended boost inverter with Active Z-network switch is presented. The proposed inverter is compared with EB-QZSI. There are some advantages of the proposed inverter over the EB-QZSI such as

1) current stress across the inverter bridge switches is less and it helps to improve the efficiency of the overall inverter. 2) reducing the weight, volume, and cost of the proposed topology by reducing the two inductors, two capacitors, and one diode but the boost factor is the same in both the topologies. 3) the power losses of the suggested topology are reduced, by reducing the passive components, that help to improe boost ability.

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