Phase Locked Loop: A Review

Phase Locked Loop: A Review

Rachana Arya Suman

Ph.D. Scholar, ECE Separtment Associate Professor OPJS university, Churu, India OPJS university, Churu, India

Abstract Phase locked loop act as colossal role towards the expansion of the ASIC (application specified integrated circuits). With this technology, the delay time of the circuits was decreased. It is primary building block for several devices, like clock pulse creation, microprocessors, fasten the circuits and lots of. The essential quality like locking capability of this locked loop, it can be present in various applications. At the present time, wireless equipments can show the way in our lives. All engineering mind focused on the tininess of the circuits, mechanism and dimensions the devices. The RF communication is indispensable for promptness of data transition in wireless systems. Through the frequency synthesis, RF transmission use steady timing signals to be generated by phase locked loop. After detailed study of many papers, the performance, design, and enlargement of PLL circuit is framed.

1. INTRODUCTION

   Phase lock loop is a fundamental part of radio, wireless and telecommunication technology. Nowadays digital systems are using clocks for sequencing their operations and synchronizing different functional units. The most versatile application of phase locked loops (PLL) is clock generation and clock recovery. The data transfer rates and clock frequencies have been constantly increasing with every generation of processing technology. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability.

   The history of the phase-locked loop dates back to as early as 1932. According to author Dr. Rolland Best, the French engineer De Belle size is the inventor of coherent communication. Phase locked-loops (PLLs) are extensively used to generate well-timed on-chip clocks to be used in high-performance digital systems. Phase locked loop is a closed loop system which locks the phase of its output signal to reference input signal. PLL is a mixed signal circuit as its architecture involves both digital and analog signal processing units.

   Classification of PLLs

   Using the notation of Best [8] and Gardner in [9], the different classes of PLLs are as follows:

   1. Analog Phase-Locked Loop (PLL)

   2. Digital Phase-Locked Loop (DPLL)

   3. All-Digital Phase-Locked Loop (ADPLL)

   On the basis of component used, the PLL can be divided into sub-sections; given in table 1.

   TABLE 1: CLASSIFICATION OF PLL ON THE BASIS OF COMPONENT USED

   PLL Type

   Phase Detector

   Loop Filter

   Controlled Oscillator

   Analog PLL	Analog Multiplier	RC	Voltage
   Digital PLL	Digital Detector	RC	Voltage
   All Digital PLL	Digital Detector	Digital	Digital Controlled
   Software PLL	Software Multiplier	Software	Software

2. RELATED WORK

   In 2019, Shruti Hathwalia and Naresh Grover [14], presented a comparative study on DPLL. In that research they present a relative review of Ring oscillator and LC oscillator for PLL. They also discuss both the oscillators parameters and pros and cons of the systems.

   Lei Zhang et al. [15], uses a fast acquisition PFD to eliminate non ideal effects of PLL. 65nm technology is used for designing of PFD. This consumes the area of 0.0016mm2 for 1.5mW power only. By the simulation, the maximum operating frequency is 5GHz.

   Usha Kumari and Rekha Yadav [12] reviews and article on Digital PLL. They had discussed about the basic building blocks and the features of them. By the comparison analysis they concluded a circuit having low noise and better control range. The circuit is basically used for receivers and wireless systems.

   Supraja Tirumalasetti et al. [16], proposed reduces jitter PFD to increase the lock range of PLL. It uses the pass transistor to increase the rise time. The operating frequency of this is 5MHz with delay of 2.93 seconds.

   Leela Bitla et al. [17], presented a paper on Analysis of NAND gate based phase frequency detector for phase locked loop. The PFD designed for this is a NAND gate based that consume appreciably low power over different temperature variation. The range of slew rate is 44 v/ns – 30 v/ns on 65C.

   Shanker N. Dandra and Ankita H. Deshmukh [6], designed DPLL using 45nm technology. X-OR Phase detector is used for DPLL. The Vdd is 0.9v with input frequency of 2.4 GHz. The lock frequency of DPLL is 7.1 GHz at 0.9V control voltage. Loop is locked at 2.4 GHz frequency.

   In 2017, Nabihah Ahmed et al. [19], obtained a tri-state CP and 2nd order LPF used in PLL system. The projected design has been simulated by 130nm technology in Cadence Tool at 1.2v supply. The throughput swing is 288 mV to 413.8 mV at

   4.7 GHz frequency. The layout area measurement is 31.4 µm x 22.6 µm (0.7096 mm2).

   Gande Bhargav et al. [20], devised a PLL by adjusting the values of CP and LPF. The locking time is about 1.5µs at 1V supply. The total power consumption of oscillator is 0.5uW. CMOS technology (90nm) is used for the proposed design

3. REGION OF OPERATION OF PLL

   The PLL have three basic regions of operation for which it

   stages. As a result, the VCO changes its operating frequency, hence changes the output feedback signal. This output signal is fed back to the Phase Detector. The Phase Detector detects the new phase difference again and the same feedback process occurs. In this way, the phase error vanishes eventually and the phase locking is completed.

   Reference

   can work. If it is not locked (input and output are on different phase) PLL is in dynamic state. And if both phases are same it is called as static state.

   Hold

   Pull in range

   Clock (i)

   Feedback Clock (o)

   e

   Detector

   Detector

   VCO

   Loop Filter

   Loop Filter

   Voltage signal

   Output (Vc)

   1. Hold range

      Lock in

      Fig. 1: PLL Region of Operation

      Fig. 2: Block Diagram of Analog PLL

      A four-quadrant multiplier Phase Detector is shown in Fig.3 [12], which is an ideal analog design. The phase detector is a multiplier and it is applied for determining the phase relationship between the reference clock and the feedback clock. The output of the multiplier is made up of two

      It is the range of frequencies in which PLL can maintain

      phase tracking between input and output. If reference frequency is gradually condensed or enlarged, the PLL will be unable to find lock. This is called hold range. It will be temporarily stable just in this range [9].

      periodic waveforms. One frequency is the difference of the two input sinusoids and the output waves frequency is their sum [9].

      Reference

   2. Pull in range

      In dynamic state it will constantly locked. Initially PLL is unlocked. It will obtain locked state if reference frequency is applied in the pull in range. If input frequency is outside then

      Reference clock

      Feedba ck

      clock

      clock

      Feedback clock

      -/2

      Vo

      –

      V

      /2

      this, the PLL will never acquire lock condition.

   3. Lock range

      The range frequencies from which lop can uphold the lock state. All the region of operation is shown in the Fig 1.

   4. Pull out range

   The frequency, facilitate the PLL to release. If input frequency is below the pull out range the PLL remain lock. On the other hand if it will exceed, PLL will not be capable to follow the output signal. After some time it may obtain lock. It is called static state of PLL.

4. OPERATION OF PLL

   The Analog PLL is built with entirely analog functional blocks. The basic block diagram of a analog PLL is shown in Fig. 2. APLL is a closed-loop feedback system that sets fixed phase relationship between its phase of output clock and the phase of a reference clock [9]. This is used to track the phase changes that are within the bandwidth of the PLL. PLL also multiplies a low-frequency reference clock i, to produce a high frequency clock or feedback clock o. An analog multiplier is used as the Phase Detector (PD) to produces an error output signal based on the phase difference between the feedback clock and the reference clock [10, 11]. The phase difference signal is applied to the Loop Filter. The Loop Filter is basically a low pass filter, built with passive or active components. The filtered error signal acts as a control signal (voltage or current) to the oscillator and adjust the frequency of oscillation to align feedback phase to the reference phase. The Voltage-Controlled Oscillator (VCO) is a ring oscillator constructed by differential inverter

   Fig. 3: Operating diagram of a four-quadrant multiplier PD

   If we have two sinusoids s1 and s2, both have same frequency but have phase difference of 90º. By multiplying these two signals, s3 signal is obtained. We take s1 and s2 as sine and cosine signal respectively.

   Fig. 4: Multiplier based Phase Detector

   s1 (t) = A1 cos [t+1 (t)] (1)

   s2 (t) = A2 sin [t+ 2 (t)] (2)

   s3 (t) = s1 (t). s2 (t) (3)

   The output of the multiplier is

   s3 (t) = Km s1 (t) s2 (t)

   =KmA1cos [t+1 (t)] A2 sin [t+ 2 (t)] (4)

   Where Km is the gain of the multiplier. By the above equation, the multiplier signal s3 consists of two parts, the first one is the function of only the phase difference of two signals, and the second term is the frequency which is twice of the signal frequency plus the sum of the two phases. The second part of the equation is the high frequency component and it can be discarded by filtering out since it does not contain any necessary information.

   2	Ring	Simple to integrate	Reduced phase noise
   		Superior phase noise	Hardly ever worn for RF systems
   		Phase generation is 360° at the time of oscillation and it is used in elevated data links	It will suffer with jitter problems

   2	Ring	Simple to integrate	Reduced phase noise
   		Superior phase noise	Hardly ever worn for RF systems
   		Phase generation is 360° at the time of oscillation and it is used in elevated data links	It will suffer with jitter problems

5. COMPARISION OF PLL PARAMETERS

   The different comparison parameters of all the components are shown by tables I, II and III.

   TABLE I. COMPARISON OF DIFFERENT TYPE OF PHASE DETECTOR

   Phase Detector
   S.N.	Type	Advantages	Disadvantages
   1	EX-OR	It will generate the output voltage for both the cycles of input pulse.	The data losses occurred, because that is not sensitive for both edges
   2	JK flip flop	The data losses will not be occurred because that is sensitive for both clock edges	It produced larger phase tracking and the angle is -180° to 180° phase error
   3	PFD	The Phase error shifted for -360° to 360°. It will lock the input for different conditions.	Circuit complexity is high as the numbers of components are more than other phase detectors.

   Phase Detector
   S.N.	Type	Advantages	Disadvantages
   1	EX-OR	It will generate the output voltage for both the cycles of input pulse.	The data losses occurred, because that is not sensitive for both edges
   2	JK flip flop	The data losses will not be occurred because that is sensitive for both clock edges	It produced larger phase tracking and the angle is -180° to 180° phase error
   3	PFD	The Phase error shifted for -360° to 360°. It will lock the input for different conditions.	Circuit complexity is high as the numbers of components are more than other phase detectors.

   TABLE II. COMPARISON OF DIFFERENT TYPE OF LOOP

   FILTER

   Loop filter
   S.no.	Type	Advantages	Disadvantages
   1	Active fliter	In this filter load resistance does not affect the operation of circuit.	At the high frequency circuit output is not fixed
   		Bandwidth of the circuit can be easily adjusted by varying the parameters of the circuit.	The throughput is unreliable at high frequencies.
   		It provides good isolation between load and the circuit components.	As the change in the input voltage occurs, it will openly change the output of the circuit.
   2	Passive filter	Easy to design and compact, light in weight.	Q factor is low.
   		Works on very high frequency so it will suffer with noise.	It cannot reduce the ripples.
   		Enhances the circuit complexity.	It will easily alter the control voltage.
   		No isolation required between load and the circuit.	Modulate the clock frequency so the clock pulse will vary.
   		Q factor is high.	It becomes costly as active components are used.

   Voltage Control Oscillator
   S.no.	Type	Advantages	Disadvantages
   1	LC Oscillator	Squat phase noise	Outsized layout area- >larger area for inductor
   		Excellent stability	Tank networks may have resultant resonant frequencies, which cause unwanted performance loss to the circuit.
   		Low jitter performance of the circuit	Constricted tuning range, require lot of classification to tune and it has supplementary complex design.

   Voltage Control Oscillator
   S.no.	Type	Advantages	Disadvantages
   1	LC Oscillator	Squat phase noise	Outsized layout area- >larger area for inductor
   		Excellent stability	Tank netwrks may have resultant resonant frequencies, which cause unwanted performance loss to the circuit.
   		Low jitter performance of the circuit	Constricted tuning range, require lot of classification to tune and it has supplementary complex design.

   TABLE III. ADVANTAGES AND DISADVANTAGES OF VCO

6. RESULT AND CONCLUSION

The purpose is to limit the centre frequency by the scaling of transistor at the different levels. As a result the locking time of the PLL is reduced as compared to the paper [14]. As the same supply voltage is used in both papers transistors size would change the all parameters. The oscillation frequency is far better to the compared paper. The power consumption is almost 1.08mW with five stages of oscillator. The comparison parameters are shown in following table 4. By varying the low pass filter parameters the oscillation frequency can be changed.

TABLE 4 THE PERFORMANCE ANALYSIS OF DIFFERENT

PARAMETERS

Phase frequency detector is designed by the D flip flop so one glitch is coming at the simulation result at 1.06ns time period. These pulses can change the control voltage for VCO. The maximum peak occurs at 98.76 MHz frequency.

REFERENCES

1. L.Kyoohyun, A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization, IEEE journal of solid-state circuits, vol.35, Issue 6, pp.807-815, 2000.

2. J.F.Parker and A.D.Ray, A 1.6-GHz CMOS PLL with on-Chip Loop Filter, IEEE journal of solid-state circuits, vol. 33, Issue 33, pp. 337- 343,1988.

3. D.Ramey, A 21600-MHz CMOS Clock Recovery PLL with Low- Capability, Analog Integrated Circuits and Signal Processing journal, vol. 19, pp.91-112, 1997.

4. N.D.Patel and A.P. Naik, A Low Jitter Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer CMOS Technology, International Journal of Electronics and Communication Engineering and Technology, vol. 9, issue 3,pp. 112, 2018.

5. K. Parmar, All Digital Phase Locked Loop design for different applications: A Review, IJIRT, vol.1, Issue 8, pp. 96-99, 2014.

6. S.N. Dandare and A.H. Deshmukh, Design of DPLL using Sub Micron 45nm CMOS Technology and Implementation using Microwind 3.1 Software, Journal of Science and Technology, vol. 3, Issue 1, pp. 22-32, 2018.

7. W. Abbas, Z. Mehmood and M.A. Seo, Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS, Electronics, vol. 9, pp. 1-12, 2020.

8. D. Harikrushna, M. Tiwari, J.K. Singh and A. Khare, Design, Implementation and Characterization of XOR Phase Detector for DPLL

   in 45 nm CMOS Technology, Advanced Computing: An International Journal ( ACIJ )., vol. 2, Issue 6, pp. 45-57, 2011.

9. D. Ghai and N. Jain, All-Digital Phase Locked Loop (ADPLL) -A Review, International Journal of Electronics and Computer Science Engineering, vol.2, Issue 1, pp. 94-101, 2012.

10. P. K. Hanumolu, Analysis of Charge-Pump Phase- Locked Loops, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 51, Issue 9, pp. 1665-1674, 2004.

11. B. Razavi. Design of Analog CMOS Integrated Circuits, Tata McGraw Hill Edition, 2002.

12. U. Kumari and R. Yadav, Design and Implementation of Digital Phase Lock Loop: A Review, International Journal of Advanced Research in Electronics and Communication Engineering, vol. 7, Issue 3, pp. 197- 201, 2018.

13. P.Kumar and R. Yadav, Design of CMOS Based FM Quadrature Demodulator using 45nm Technology, IJRSET, vol. 3, Issue 7, pp. 12- 16, 2017.

14. S. Hathwalia and N. Grover, A Comparative Study of Ring VCO & LC-VCO based PLL, IJERA, vol. 9, Issue 2, pp. 52-54, 2019.

15. S. Gunda, R.S.E. Ravindran, B. Hemalatha and C. Divya, Design and Simulation of Digitally Controlled Oscillator of ADPLL, International Journal of Advanced Scientific Technologies in Engineering and Management Sciences, vol. 5, Issue 3, pp. 1-4,2019.

16. S.Tirumalasetti, K. Baburao. M. K. Kishore and E. R. K. Reddy, Design and Implementation of Optimum CMOS Phase Frequency Detector for PLL, International Journal of Computer Application, vol. 7, Issue 4, pp. 52-60, 2017.

17. L. Bitla, V. Saraswathi and H.M Akano, Analysis of NAND Gate Based Phase Frequency Detector for Phase Locked Loop, Journal of Critical Reviews, vol. 7, Issue 9, pp. 172-176, 2020.

18. N. Ahmad, N. A.B. Ishaimi and M.H Jabbar, Charge Pump and Loop Filter for Low Power PLL Using 130nm CMOS Technology, International PostGraduate Conference on Applied Science & Physics IOP Publishing IOP Conf. Series 1049, pp.1-10, 2018.

19. MD T. I. Badal, MD J. Alam, M. B. I. Reaz, M.A. S. Bhuiyan and N.

    1. Jahan, High-Resolution Time To Digital Converter In 0.13 µm Cmos Process For RFID Phase Locked Loop, Journal of Engineering Science and Technology, vol. 14, no. 4, pp. 1776-1788, 2019.