 Open Access
 Total Downloads : 2035
 Authors : Jignesh V. Patel , Hetal Bhatt
 Paper ID : IJERTV1IS10129
 Volume & Issue : Volume 01, Issue 10 (December 2012)
 Published (First Online): 28122012
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Performance Evaluation Of Different Types Of Analog To Digital Converter Architecture
Jignesh V. Patel1, Hetal Bhatt2
1(PG Student (SemIII), Sankalchand Patel College of Engineering, Visnagar)
2(Assistant Professor, Sankalchand Patel College of Engineering, Visnagar)
Abstract
Signal processing is very important in many of the system onachip applications. Analog to digital converters (ADCs) is a mixed signal device that converts analog signals which are real world signals to digital signals for processing the information. A paper present review study of the most popular type of Analog to Digital Converters like flash, pipelined, sigmadelta and successive approximations. The paper represents the fundamental operating principles of these architectures with the sources of error. At last comparison between all analog to digital converters also discussed.
Keywords: Flash ADC, Sigma Delta ADC, Pipelined ADC, Successive Approximation ADC

Introduction
In the recent years, the need to design a low voltage, low power, high speed and wide bandwidth analogtodigital converter has increased tremendously. Analog to digital converters are the basic building blocks that provide an interface between an analog world and the digital domain. As it is the main block in mixed signal applications, it becomes a bottleneck in data processing applications and limits the performance of the overall system. In this paper we present a number of A/D converter architectures. We discuss different architecture of ADCs that include Flash, Pipeline, SigmaDelta and Successive Approximation ADCs. [1] [2]

ADC Architecture
At present, there exists a variety of ADCs with different architectures; accuracies power consumptions, specifications, sampling rates, resolutions and temperature ranges. These ADCs are used in different applications according to the characteristics of ADCs. Since the performance resolution, sampling rate and power consumption of an ADC is basically determined by its architecture, one single ADC type cannot cover all applications. For instance, flash (parallel) ADCs can
be used in high speed and low resolution applications. Because of its parallel architecture, all conversions are done in one cycle with many comparators. On the other hand, a successive approximation ADC can be used in lowspeed and highresolution applications since the conversions are done in many cycles with only one comparator. Therefore, it is important to select a proper ADC for each particular application. [2].

Types of ADCs
Among the variety of ADC architectures, there are four most popular ADC architectures presently used. These are as follows:

Flash ADC
Figure 1. Block Diagram of Flash ADC
The flash ADC is known for its fastest speed compared to other ADC architectures. Therefore, it is used for highspeed and very large bandwidth applications such as highdensity disk drives, radar processing, digital oscilloscopes, and so on. The flash ADC is also known as the parallel ADC because of its parallel architecture.
Figure 1 illustrates a typical flash ADC block diagram. As shown in Figure 1, this architecture needs 2n 1 comparators for an nbit ADC; for example, a set of 63 comparators are used for 6bit flash ADC.
Each comparator has a reference voltage that is provided by an external reference source. These reference voltages are equally spaced by VLSB from the largest reference voltage to the smallest reference voltage. An analog input is connected to all comparators so that each comparator output is produced in one cycle. The digital output of the set of comparators called the thermometer code is changed into a binary code through the encoder. [2]

Design Considerations and Implications
The flash ADC architecture has high speed conversion due to its parallel structure. However, the flash ADC needs a large number of comparators as the resolution increases. For instance, a 6bit flash ADC needs 63 comparators, while 10bit flash ACD need 1023 comparator. The increase in comparator will increase die size and power consumption. [14] Represent technique for reducing circuit complexity for encoder design.
3.1.1. Error Sources in Flash ADC

Metastability
When a digital output of a comparator is ambiguous i.e. neither a one nor a zero, the output is defined as metastable. Metastability can be reduced by allowing more time for regeneration. Graycode encoding can be used to improve metastability. Gray code encoding allows only one bit in the output to change at a time. The comparator outputs are first converted to graycode encoding and then later decoded to binary. Another problem occurs when a metastable output drives two distinct circuits. It is possible for one circuit to declare the input a "1" while assumes it's a "0". This can create major errors. To avoid this, only one circuit should sense a potentially metastable output.

Sparkle Codes
Normally, output of the comparator is thermometer code, such as 00111111. Errors may cause an output like 0011011. The spurious "0" in the result sequence is called a sparkle. The sparkles can be due to imperfect input settling or comparator timing mismatch. The magnitude of the error can be quite large and can be avoided by employing an input trackandhold in front of the ADC along with an encoding technique that suppresses sparkle codes [7].

Clock Jitter
Jitter in sampling rates decrease Signal to Noise ratio in Analog to Digital Converter. This becomes noticeable for high analog input frequencies. To achieve accurate results, it is critical to provide the ADC with a lowjitter, sampling clock source [8].



Pipelined ADC
Figure 2. Block Diagram of Pipeline ADC
A pipeline ADC quantizes input voltage in a number of stages. The pipelined ADC architecture is implemented using at least two or more low resolution flash ADCs as shown in Figure 2. Each stage has a S/H circuit to hold the amplified residue from the previous stage. Then, the input is fed to the low resolution flash ADC to generate a segmented binary output. Like the subranging ADC, the segmented output is changed to an analog signal and is subtracted from the input. This residue is amplified in an amplified to send to the next stage. The segmented binary outputs from each stage are timealigned with a shift register. The final binary output is obtained after passing through digital error correction logic. This conversion process in the pipelined ADC is shown in Figure 2. [2]
3.2.1 Design Considerations and Implications
In Pipelined converters it is possible to achieve higher resolutions than flash converters containing a similar number of comparators. However this comes at the price of increasing the total conversion time from one cycle to x cycles. But since each stage samples and holds its input, x conversions can be carried out simultaneously. The total throughput can therefore be equal to the throughput of a flash converter, i.e. one conversion per cycle. The difference is that for the pipelined converter, latency equal to x cycles is introduced. The power consumption is also increase in Pipelined ADC. Another limitation of the pipelined architecture is that the conversion process
generally requires a clock with a fixed period. Converting rapidly varying nonperiodic signals on a traditional pipelined converter can be difficult because the pipeline typically runs at a periodic rate. Different ays to overcome these practical design issues have been discussed in [8, 09, 10].
3.1.1. Error Sources in Pipelined ADC

Overlapping
The following condition should be met to correct for overlapping errors:
J Ã— L+K > M
where J is the number of stages, L is the coarse resolution of subsequent stages in the ADC circuit, K is the fine resolution of the final ADC stage, and M is the pipeline ADC's overall resolution. Pipeline ADCs include digital errorcorrection circuitry which is operates between the stages. Some pipeline quantizers have a calibration unit that compensates for unwanted side effects such as capacitor mismatch or temperature drift in the multiplying DAC.

Other Difficulties in Pipeline ADC

Pipeline latency, caused by the number of stages through which the input signal must pass.

Sensitivity to process imperfections that cause nonlinearities in gain, offset, and other parameters.

Complex reference circuitry and biasing schemes.

Critical latch timing, needed for synchronization of all outputs.

Greater sensitivity to board layout, compared with other architectures.
3.1 Sigma Delta ADC
The sigmadelta architecture takes a fundamentally different approach from the other architectures. Sigmadelta converters offer high integration, high resolution, and low cost, making them a good ADC choice for different applications such as weighing scales and process control. [2]
Sigmadelta () converters have relatively simple structures. Also called oversampling converters.
Figure 3. Block diagram of a Sigma Delta ADC
It consists of two main blocks. One is the Sigmadelta modulator that includes an integrator, a comparator, and a singlebit DAC. The other is a digital filter that changes the Sigmadelta output to binary code with filtering. Its block diagram is shown in Figure 3. The output of the 1bit DAC is subtracted from the input signal, integrated, and then converted to a 1bit binary output. This single bit again goes to the DAC to be processed. This closedloop process is performed at a very high oversampled rate [12].

Design Considerations and Implications



Noise Shaping
One of the most advantageous features of the sigmadelta architecture is the capability of noise shaping, a phenomenon by which much of the low frequency noise is effectively pushed up to higher frequencies and out of the band of interest. As a result, the sigmadelta architecture has been very popular for designing lowbandwidth high resolution ADCs for precision measurement [12] [13].

Oversampling
Deltasigma ADCs use sample rates that are a large multiple, for instance, 128 times the sample rate sufficient for a given signal. For example, to sample a 25 kHz signal, a sample rate greater than the Nyquist rate (that is, > 50 KHz) would be sufficient. However, a deltasigma ADC using an oversample factor of 128 samples the signal at 6 MHz This approach has several benefits, such as better antialiasing and higher resolution.
In the frequency domain, sampling a signal effectively modulates the input signal spectrum with carrier frequencies that are multiples of the sample rate Fs (that is, 0, Fs, 2Fs, 3 Fs, and so on). To recover the signal the sampling rate require must be greater than the Nyquist rate (Fs > 2Fmax). The oversampling property of sigma delta ADC will provide better antialiasing as shown in Figure 4.
Figure 4. Concept of Oversampling in Sigma Delta ADC

Error Sources in Sigma Delta ADC
A limitation of Sigma delta architecture is its latency, which is substantially greater than all other types of architecture. Because of latency and oversampling sigmadelta converters are not often used in multiplexed signal applications. To avoid the interference between multiplexed signals, a delay at least equal to the decimator's total delay must occur between conversions. These characteristics can be improved in sophisticated sigmadelta ADC designs by using multiple integrator stages and/or multibit DACs [12] [13].

Successive Approximation ADC
Successive Approximation Register ADC is a proper choice for low power applications. SAR ADC employs a successive approximation algorithm to convert analog input to a digital code successively. In other words, one bit is determined in each clock cycle using binary search algorithm.
In this structure track/hold circuit is used to hold the analog input voltage (VIN). The binary search algorithm is implemented by Nbits register. The block diagram is shown in Figure 5.
Figure 5. Block diagram of a successive approximation (SAR) ADC
Initially the value of register is set to mid scale i.e. MSB set to 1 and all the other bits are set to 0. The output of DAC (VDAC) becomes half the reference voltage VREF /2, where VREF is the reference voltage of ADC. The comparator will compare the input voltage VIN with VDAC. If VIN is greater than VDAC, the comparator output will be set to 1, and the MSB of the Nbit register remains at '1'. If the input voltage VIN is less than VDAC then the comparator output becomes 0. The SAR control logic will change the MSB of the register to '0', set the next bit to 1 and perform comparison again. The operation of 4bit SAR ADC is shown in figure 6. This process continues till LSB and once this process is completed the Nbit digital word is available in the register. [2]
Figure 6. A 4bit SAR ADC operation

Design Considerations and Implications
A SAR converter using a single comparator it is possible to realize a high resolution ADC. To achieve nbit resolution n comparison cycles are requires, compared to p cycles for a pipelined converter and 1 cycle for a flash converter. Since a successive approximations converter uses a fairly simple architecture employing a single SAR, comparator, and DAC, and the conversion is not complete until all weights have been tested, only one conversion is processed during n comparison cycles. For this reason,
Parameter 1 Select this architecture if you want?
Flash
UltraHigh Speed when power consumption not primary concern
Pipeline
High speeds, few Msps to 100+ Msps, 8 bits to 16 bits, lower power
SigmaDelta
High resolution, low to medium speed, no precision external components.
Successive Approximation
Medium to high resolution (8 to
16bit), 5Msps and under, low power, small size.
Parameter 2 Conversion Methods
Flash
N bits – 2N 1 Comparators Complexity increase by a factor of 2
for each bit.
Pipeline
Small parallel structure, each stage
work on one to a few bits.
SigmaDelta
Oversampling ADC, 5Hz – 60Hz
rejection programmable data output.
Successive Approximation
Binary search algorithm, internal circuitry runs higher speed.
Parameter 3 Encoding Methods
Flash
Thermometer Code Encoding
Pipeline
Digital Correction Logic
SigmaDelta
OverSampling Modulator, Digital Decimation Filter
Successive Approximation
Successive Approximation
Parameter 4 Disadvantages
Flash
Sparkle codes / metastability, high power consumption, large size, expensive.
Pipeline
Parallelism increasesthroughput at the expense of power and latency
SigmaDelta
Higher order (4th order or higher) – multibit ADC and multibit feedback DAC
Successive Approximation
Speed limited to ~5Msps. May require antialiasing filter
SAR converters are more often used in higher resolution and lower speed applications.. This feature makes the SAR architecture ideal for converting a series of timeindependent signals [2]. [1516] Suggest methods for highspeed lowpower structures for SAR ADCs. Aliasing is another parameter of consideration when using a SAR ADC.
The process of sampling a signal leads to aliasing – the frequencydomain reflection of signals about the sampling frequency. In most applications, aliasing is an unwanted effect that requires a lowpass antialias filter ahead of the ADC to remove high frequency noise components, which would be aliased into the passband. However, undersampling can put aliasing to good use, most often in communications applications, to convert a highfrequency signal to a lower frequency. Undersampling is effective as long as the total bandwidth of a signal meets the Nyquist criterion (less than onehalf the sampling rate), and the converter has sufficient acquisition and signal sampling performance at the higher frequencies where the signal resides.

Error Sources in Successive Approximation ADC
The different sources of error and drawbacks are:

The serial nature of SAR architecture limits its speed.

The settling time of the DAC, this must settle to within the resolution of the overall converter, for example, Â½ LSB.

Comparator noise causes performance degradation of the ADC because of the lack of gain in the ADC architecture. One can put a preamplifier before the comparator to reduce this noise, but at the expense of burning more power in the preamplifier.





Comparison of all ADC Architecture
In this section we represent the comparison of
all ADC architecture by considers different parameter like conversion methods, encoding method, conversion time, size, resolution and disadvantages. The comparison of different ADC can be understood from following Table1.
Parameter 5 Conversion Time
Flash
Conversion Time does not change with increased resolution
Pipeline
Increases linearly with increased resolution
SigmaDelta
Tradeoff between data output rate and noise free resolution
Successive Approximation
Increases linearly with increased resolution
Parameter 6 Size
Flash
2^N1 comparators, Die size and power increases exponentially with
Pipeline
Die increases linearly with increase in resolution
SigmaDelta
Core die size will not materially change with increase in resolution
Successive Approximation
Die increases linearly with increase in resolution
Parameter 7 Resolution
Flash
Component matching typically limits resolution to 8 bits
Pipeline
Component matching requirements double with every bit increase in resolution
SigmaDelta
Component matching requirements double with every bit increase in resolution
Successive Approximation
Component matching requirements double with every bit increase in resolution
Table1 Comparison of ADCs Architectures. [3]

Conclusion
In this paper various types of ADCs have been discussed with their architectures and working principal. The design constraints and sources of errors for all architectures have been highlighted to draw a fair comparison of all architectures. At last comparison between all ADC architecture by considering different parameter is also presented.
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