 Open Access
 Authors : Ritesh Soni , Sumam M J
 Paper ID : IJERTV9IS070194
 Volume & Issue : Volume 09, Issue 07 (July 2020)
 Published (First Online): 15072020
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Implementation of Low Voltage SubBandgap Voltage Reference in 90nm CMOS
Ritesh Soni
M.Tech in ECE
Department of Electronics and Communication Engineering
Goverment Engineering College, Idukki Kerala, India
Prof. Sumam M J Associate Professor
Department of Electronics and Communication Engineering
Goverment Engineering College, Idukki Kerala, India
AbstractThe paper introduces a new low voltage design Subbandgap reference circuit consists of the MOSFETs and BJT subthreshold. The proposed subBGR circuit shall be implemented in a standard CMOS technology of 90 nm. The results achieved low power consumption in subBGR circuit and operated from 0.7v to 2v supply voltage. The simulation was carried out at voltage variations and temperature variation at
range of 20Â°C140Â°C on the cadence virtuoso using spectre
simulator.
KeywordsSubthreshold, voltage reference, Bandgap reference, Temperature coeffificient

INTRODUCTION
The increase in portable device usage has boosted to emphasis on minimizing power, speed and area. With the advancement of the semiconductor manufacturing technology the feature size of the devices had been reduced to nanometers. More devices are integrated on the same area of the chip, thus significantly improving system performance. The CMOS subthreshold voltage references (VRs) were operated with low supply voltage and consumed low power [1]. The VRs can be categorized as two types: one type relating to the bandgap voltage of Silicon or a fraction of it (i.e., subbandgap) with BJTs and resistors, The other was related to other factors such as MOS transistor threshold voltages and MOS transistor subthreshold parameters (For resistors with or without [1][4].
capacitor voltage divider and charge pump were used to achieve a complementaryto absolutetemperature division (CTAT) voltage (VBE) and low voltage power supply, but the temperature coefficient (TC) is as high as 75 ppm/Â°C and the temperature range is limited to be only 0Â°C80Â°C [7]. CMOS VRs [8][12] has several issues remaining, such as leakage current consumption , low reference voltage of 257.5mv and wide area. In this work, we propose a CMOS subthreshold voltage reference (VR) implemented in a circuit. The reference voltage is biased with the temperatureindependent , increasing performance and accuracy of circuit with very low sensitivity to variations in process, supply voltage. For the rest of the paper, Section II present the materials and methods of the voltage reference. The measurement results of a prototype design in a standard 0.90Âµm CMOS process are introduced and analyzed in Section III.

PROPOSED VOLTAGE REFERENCE
Fig. 1 shows the proposed subBGR circuit using a single parasitic vertical PNP BJT, i.e., Q0 to generate CTAT Voltage and polyresistance R2 for PTAT voltage generation. The circuit process can be described as the summation of two currents (one PTAT and the other CTAT). BJT s base emitter forward voltage indicates a negative TC, for a bipolar system collector current IC and saturation current IS depends on temperature as shown below
Although several lowpower VRs were developed in [1][20],
I I exp( VBE )
V
V
the other output voltage either increases exponentially or C s decreases linearly with temperature. The most popular on T chip integration solution is the Bandgap Voltage Reference
(BGR), which can be used in standard CMOS technology that exploits parasitic vertical BJTs. Conventional BGRs produce an independent reference for low temperature, approximately
I = bT(4+m) exp( Eg )
S KT
1.25 V and thus require a higher supply voltage that may not satisfy the lowvoltage requirements for lowpower
The current IR flowing through the resistor R2 is given by
applications. However, many approaches have been introduced using the BGR concept to maintain sub1V Operation [3]. Bandgap references (BGRs) are widely used for
VBE
R
R
=
=
I
I
R
2
(3)
generating a temperatureinsensitive reference voltage determined by the bandgap of silicon[5][6]. The BGR typically uses PN diodes to produce both proportionalto absolute (PTAT) and complementarytoabsolute (CTAT) temperature. The circuits given in [6] and [7] The switched
where VBE is the emitterbase voltage of Q0 as shown in equation (3), the voltage VBE should be decreased and R2 increased in order to reduce the current IR and thus the power consumption. Although, improving R2 will eventually increase the chip area consumption.So the best way to do that is to
minimize the VBE value. Decreasing the Q0 current often reduces its baseemitter voltage. Reducing VBE, however, also where VBE is the emitterbase voltage of Q0 as shown in equation (3), the voltage VBE should be decreased and R2 increased in order to reduce the current IR and thus the power
function of its gate source voltage VGS and drain source voltage VDS.
For VDS > 0.1 V, drain current ID is almost independent of VDS and is approximately given by
consumption. Although, improving R2 will eventually increase
I = KÂµC ( 1)V2 exp(VGS VTH )
the chip area consumption.So the best way to do that is to minimize the VBE value. Decreasing the Q0 current often reduces its baseemitter voltage. Reducing VBE, however, also reduces the negative TC or increases the absolute value of VBE TC since VBE derivative analysis is given as
D ox
V = V – V
T
=V
VT
K
K
ln( nK4 )
(6)
(7)
VBE
= VT ln IC (4 + m) VT – Eg V
GS GS5
GS4 T
5
T T IS
T KT 2 T
(4)
VBE
T
VBE (4 m)VT Eg / q T
(5)
where m is the nonidentical factor of transistor, VT is the thermal voltage, Eg is the bandgap energy of silicon, and q the elementary charge. The current through Q0 should not be too small so as not to increase the required positive TC of the proportionaltoabsolutetemperature (PTAT) voltage. To optimize the power and area, the current IR through R2 is chosen to be three times of the current through Q0. The combination of the PMOS with a P+ poly resistor R2 produces a PTAT current flow. Reference voltage with nominally zero temperature coefficient is obtained with negative and positive TC voltage. The circuit is designed using 90nm CMOS technology.
Fig. 2. Schematic of the OPA used in the SubBGR circuit..
where K is the aspect ratio (W/L) of the transistor, Âµ is the carrier mobility, COX is the gateoxide capacitance, VT is the thermal voltage, VTH is the threshold voltage of the MOSFET, and is the subthreshold slope factor. The drain source voltage VDS of transistors NM4NM7 are designed to be larger than 0.1 V. The threshold voltages of NM4 and NM5 are the same, and the drain current of NM5 is two times that of NM4, so the drainsource voltage of NM5 can be derived from (6) is given by
VDS 5
VGS
VGS 5
VGS 4
VT
ln( nK4 )
K
(8)
5
In a similar way, the voltage VDS7 is given by
Fig. 1. Schematic of the proposed subBGR
The operational amplifier OPA shown in Fig. 2 enforces that nodes to have equal potential. The OPA uses the folded cascode structure to improve the loop gain and Power. The offset voltage of the OPA can be minimized by using largesize input transistors and coupling capacitor. The transistors PM2 PM3 are current mirrors and the size of PM3 is approximately two timesof PM2 similarly PM4PM5. The transistor NM11 work as diode connected NMOS , So the current through NM11 is the same as that of R2.
The PTAT voltage generator consists of transistors NM4
VDS 7
VGS
VGS 7
VGS 6
VT
ln( nK6 )
K7
(9)
NM7 all of which work in the subthreshold region. The subthreshold drain current ID of a MOSFET is an exponential
Fig. 3. Practically measured Vref with respect to change in supply voltage.
Fig 3. Shows the simulated output voltage determined against 0v to 2v. Fig. 3. Simulated output voltage measured was also shown by temperature variation 20Â°C140Â°C. The generated Vref of the proposed subBGR is 248 mv and also associated in the PTAT term with the process parameter in the PTAT term ,which is not constant in actual system and depends on the capacitance of the gateoxide and depletion layer. Still the variance is not too large. The TC of Vref is also related to the process parameter and the effect of parameter on Vref and TC of Vref are similar , so output Vref variation is very small . Therefore, the output voltage Vref is given by
VX

RESULT
The proposed subBGR schematic is developed using cadence virtuoso tool in a standard 90nm CMOS. Simulated output using Spectre simulator as shown in fifigures. Fig 4. shows the measured output voltage Vref versus temperature variance range. Fig 5. shows the histogram simulation results of Vref and TC. The average Vref and standard deviation are
248.352 mv and 4.967 nV respectively, leading to a variation coefficient i.e minimum. Fig 6 and 7 show The spectral power of the subBGR proposed in Fig 6 shows Power versus voltage range from 0v to 2v and Power variation is nearly constant from 0.7v 2v. Fig 7. show the average power
Vref
VGS
R
R
2
VBE Vof
(10)
consumption and standard deviation are 457pw and 231pw respectively, with range of temperature 20Â°C140Â°C.
Vref
nVT
ln( nK4 K6 )
K K
VBE
R gm
Vof
(11)
5 7 2 11
The derivative of Vref over temperature is given by
Vref
k ln( nK4 K6 ) KN
(12)
T q
K5 K7
R2 gm11
where KN is the negative TC of VBE. A zero TC can be obtained since the two terms of (12) can cancel each other with proper design, and hence Vref would be stable across a temperature variation range. The absolute value of the negative TC is reduced by 1/gm11R2 times compared with the traditional currentmode bandgap voltage reference . So the PTAT compensation factor of (K4K6K5K7) can also be reduced, which helps reduce the power and area of the PTAT circuit.
Fig. 4. Practically measured Vref versus temperature .
Fig. 5. Histogram simulation result of supply voltage.
Fig. 6. Practically measured spectral power versus supply voltage.
Fig. 7. Histogram simulation result of power.
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