 Open Access
 Authors : Shamja T M , Sindhu T V
 Paper ID : IJERTV11IS050282
 Volume & Issue : Volume 11, Issue 05 (May 2022)
 Published (First Online): 01062022
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
High Performance LookAhead Binary Counter based on Partitioning
Shamja T M
Electronics and Communication Engineering Department IES College of Engineering
ThrissurKerala,India
Sindhu T V
Assistant Professor
Electronics and Communication Engineering Department IES College of Engineering
ThrissurKerala,India
Abstract A synchronous binary counter is one in every of the essential components widely utilized in VLSI design, and it's required to be fast and support a large bitwidth in many applications. However, most of the previous counters are related to a limited counting rate because of large fanouts and long carry chains, especially when the counter size isn't small. within the proposed work, a brandnew fast structure for synchronous binary counting, which includes a minimal counting period for practical counter sizes starting from 8 to 128 bits is meant supported partitioning. We first adopt an 1bit Johnson counter to scale back the hardware complexity, and so duplicate the 1bit Johnson counter to decrease the propagation delay caused by large fanouts. within the proposed counter architecture, an Nbit counter is realized by partitioning it into three subcounters, C1, C2, and C3. Subcounter C1 is an 1bit counter that toggles between 0 and 1 every clock. Subcounter C2 is an (n1)bit counter that works supported the backward carry propagation, and therefore the last subcounter C3 is an (Nn)bit binary counter supported look ahead logic. The state lookahead path prepares the counting paths next counter state before the clock edge such the clock edge triggers all modules simultaneously, thus concurrently updating the count state with the same delay in the least counting path modules/stages with relation to the clock edge. Implementation results show that the proposed design may be realized with a little number of flipflops, which is nearly linear to the counter size, and it can operate at a high clock frequency.
Keywords Back ward carry propogation , Prescaled Counters, State lookahead logic

INTRODUCTION
Counter is one of the essential components actively employed in many applications like measurement systems, analogtodigital converters, frequency dividers, phaselocked
loop frequency synthesizers, and so on. ecause of recent advances within the applications, it's commonly required to implement a quick, wide counter supporting continuing counting rate independent of the counter size. However, the counting rate and therefore the size conflict with one another, because the carry propagation from a low order bit to a highorder bit becomes longer because the counter size gets larger.
To obtain a stable binary output, a synchronous binary counter can be used. The simplest synchronous counter is the ripple carry counter in which the carryout of an onebit adder is connected to the carryin of the succeeding stage. The chain of carry signals is called a ripple carry chain, as the carry signal is continually rippled into the next stage. The main limiting factor of the speed of a synchronous counter is
the long carry propagation caused by the carry chain. There have been many techniques developed to derive fast counters. The ripple carry chain in the traditional binary counter was replaced with a carrylookahead circuit in order to achieve a significant speedup [1].
In addition, a statelookahead topology was used in [3] to break the carry chain by adding D F/Fs, avoiding the rippling. In [4], the carry chain was constructed with employing a tree structure. However, regarding a counter as a combination of an adder and a state register is not effective in achieving a constant clock period, since the lower bound of the adder delay is not constant. There have been other efforts to speed up the counter by improving the F/F. For example, high speed synchronous counters were developed by using the F/F based on the true singlephase clock [1], [5]. To accomplish both constant delay and binary sequence, another carry propagation method called backward carry propagation was presented in [7]. It exploits the characteristics of a binary sequence that the more significant bits become high earlier than the less significant bits. This approach can be applied to achieve a constantdelay counter since the carry propagation is only determined by the least significant bit (LSB).
Another synchronous binary counter based on prescaling was presented in [8]. A wide counter is partitioned into subblocks. The highorder block is enabled by a prescaled enable (PEN) signal generated from the loworder block, and the clock period of a prescaled counter is determined by the least significant block. However, there are still issues related to the large fanout and the wide distribution of a PEN signal that is necessary to drive a large number of inputs of the F/Fs in the next block. The huge fanout is in fact the critical issue to be solved in realizing a fast binary counter. As the counter size increases, the fanout issue becomes more severe, leading to the longer propagation delay.
In this paper, we present a binary synchronous counter that operates with a constant delay for practical counter sizes ranging up to 128 bits. In the proposed counter, the large fan out issue is mitigated by duplicating the onebit Johnson counter and by applying the backward carry propagation method to get rid of the additional delay induced by the ripple carry propagation. And further delay is reduced by applying state lookahead logic that prepares the counting paths next counter state prior to the clock edge such that the clock edge triggers all modules simultaneously. The proposed counter achieves the highest counting rate, and the counting rate is
determined only by the leastsignificant 1bit counter regardless of the counter size.

EXISTING COUNTERS
Some previous works in which concepts that are relevant to the proposed counter are described below. The backward carry propagation presented in [7] is an important concept in implementing a fast synchronous counter. What makes it work is the fact that a more significant bit of the counter becomes high earlier than the least significant bit due to the characteristics of the binary number system. Instead of a single chain used in the conventional binary counter, each counter bit has a separate AND chain connected in the backward direction. In a carry chain, the early arriving signals are evaluated in advance before the lately available signals arrive. Therefore, the propagation delay is mainly determined by the delay of the last AND gate and a T F/F.
Fig.1. 64bit prescaled counter that generates prescaled enable signals with ring counters.
The constantdelay binary counter based on prescaling was presented in [8], which is depicted in Fig. 1. A wide counter is partitioned into subblocks of different sizes, and the high order subblock operates at the lower frequency than the low order subblock. The main concept is to make a highorder block add one according to the PEN signal generated from the loworder block called a prescaler. The frequency of a PEN is much slower than that of the clock signal. This is possible because the highorder block is incremented much less frequently than the loworder block. The typical method to generate the PEN is to use a ring or twistedtail counter [8]. The ring counter connects the output of the last F/F to the input of the first one, making a circular structure. When the n
bit ring counter reaches 21 value, the PEN signal becomes
1. Similarly, the nbit twistedtail counter or the Johnso
counter, in which the inverted output of the last F/F is connected to the input of the first one, activates the PEN
signal when the count value becomes 21. They can operate
at a high frequency, as there is no combinational circuit
between adjacent F/Fs, allowing the PEN to be synchronous with the clock. However, the approach is not efficient, as it needs N F/Fs to traverse N states, increasing the hardware complexity. Moreover, the PEN signal needs to drive all the F/Fs in the next partition, leading to a high fanout and increasing the propagation delay and thus decreasing the overall counting speed. Moreover, the PEN signal needs to drive all the F/Fs in the next partition, leading to a high fan out and increasing the propagation delay and thus decreasing the overall counting speed.
Fig.2. Detailed structure of the existing Nbit counter
Fig.3 Prescaled enable signal generation with redundant 1bit Johnson counters.
An Nbit counter is partitioned into three different subcounters was presented in [2] in order to take advantage of prescaling. In this counter architecture, an Nbit counter is realized by partitioning it into three subcounters, C1, C2, and C3, as shown in Fig. 2. Subcounter C1 is an 1bit counter that toggles between 0 and 1 every clock. Subcounter C2 is an (n 1)bit counter that works based on the backward carry propagation, and the last subcounter C3 is an (Nn)bit conventional binary counter. Here m 1bit Johnson counters are employed to generate m PEN signals to be used for the last
subcounter. we assume that n = log2 and m = ( )/ ,
where L is the maximum fanout to be determined by
conducting simulations The Johnson counter is initialized to 0, and the PEN signal is generated to enable the counting of the next subcounter when the Johnson counter undergoes a state change from 0 to 1.
The basic principle of the partitioned counter is to prescale the highorder block by considering the loworder block. An Nbit counter is divided into 3 subcounters such that the propagation delay of the (Nn)bit synchronous ripple carry binary counter C3, which consists of (Nn1) AND gates, is smaller than the period of PEN2 generated in C2. And subcounter C2 is an (n1)bit backward carry propagation counter and enabled by the 1bit counter C1. Observing that the delay of the long carry chain is reduced to only one AND gate by employing the backward carry propagation, we can guarantee that the carry propagation of C2 is shorter than the period of PEN1 generated in C1.
To deal with the fanout issue, a 2bit ring counter is
replaced with an 1bit Johnson counter as illustrated in Fig. 2,
where a 5bit backward carry propagation counter and a PEN generator are exemplified for N = 64, n = 6 and m = 4. The 1 bit Johnson counter changes its state when enabled after being initialized to 0 at the beginning. Our goal is to make
PEN2 have a pulse every 2 cycles, 64 cycles in this
example. For the purpose, the enable signal should be high at
the (2 2)th and (2 1)th cycles, the 62nd and 63rd cycles
in the example, in order to make PEN2 being 1 at the (2
1)th cycle, or 63rd cycle in the example. Such a signal can be
generated by exploiting the backward carry propagation
method depicted in Fig. 3. The AND operation of Q[5], Q[4], Q[3] and Q[2] can be realized by employing backward AND chains. The Q[5]&Q[4]&Q[3]&Q[2] signal becomes high when Q[2] undergoes a transition from low to high and lasts for four cycles. The late arriving signal Q[1] is connected to the last AND gate to make the output of the AND chain high for two cycles. The enable signal is equivalent to the result of
&Q[5:1], and the computation takes only one AND gate as
&Q[5:2] is already computed in advance thanks to the backward carry propagation. The enable signal is high at the 62nd and 63rd cycles and repeats periodically every 64 cycles. The PEN2 is inverted one clock cycle after the enable signal is asserted. However, the performance of module C3 is slow due to the long carry propagation caused by the carry chain in the conventional counter. So, there is a scope to improve the design of subcounter C3.
Fig.4 Detailed structure of the proposed Nbit counter.

PROPOSED COUNTER ARCHITECTURE In proposed counter, we improve counter operating
frequency by employing a unique parallel counting architecture in conjunction with a state lookahead path and pipelining to eliminate the carry chain delay of subcounter C3 is depicted in figure.4. The state lookahead path bridges the expected overflow states to the counting modules, which are exploited within the counting path. The counting modules are partitioned into smaller 2bit counting modules split by pipelined DFF latches. The state lookahead path is partitioned using the identical pipelined alignment paradigm because the counting path and thereby provides the proper predicted overflow states for all counting stages. Thereby, all counting states and each pipelined DFFs are triggered concurrently on the clock edge, enabling the count state in modules of most significance to be predicted by the count state in modules of lower significance. This cooperation between the counting path and state lookahead paths enables every counting module to be triggered concurrently on the clock edge with none rippling effect.
Fig.5 Functional block diagram of our proposed 8bit parallel counter with state lookahead logic and counting logic.
A. Parallel Counter Architecture
Figure.5 represent a sample 8bit parallel counter architecture that is utilized in our proposed counter. This structure consists of the counting path (all logic not encompassed by the dashed box) and therefore the state look ahead path (all logic encompassed by the dashed box) .We construct our counter as a singular mode counter, which sequences through a hard and fast set of preassigned count states, of which each next count state shows the following counter value in sequence. The counter is separated into steady 2bit synchronous up counting modules. Next state transitions in counting modules of upper significance are enabled on the clock cycle preceding the state transition using stimulus from the state lookahead path. Then at the rising clock edge (CLKIN) all counting modules concurrently transition to their next states. The counting path controls counting operations and therefore the state lookahead path anticipates future states and thus prepares the counting path for these future states. Three types of modules are there, module1, module2, and module3 S, where S=1, 2, 3, etc. and represents the position of module3 accustomed construct both paths.
Fig.6 Module1 hardware schematic.
Fig.7 Module3 hardware schematic.

Counting Path: Fig. 6 shows the hardware schematic of Module1. it's a parallel synchronous binary 2bit counter, which is chargeable for loworder bit counting and generating future states for all module3 Ss within the counting path by pipelining these future states through the state lookahead path. Module1 and module3 are exclusive to the counting path and every module represents two counter bits. within the counting path, each module3 is preceded by an associated module2. The output of module1 is Q1Q0 and QEN1 connects to the module2s DIN input. Module2 could also be a standard positive edge triggered DFF and is present in both paths. within the counting path.
Module 2 act as a pipeline between the module1 and module3 1 and subsequent module3S with in the counting path. In state lookahead logic module 2 placement increases counter operating frequency by eliminating the lengthy AND gate rippling and large computer circuit fanin and fanout present in large width parallel counters. instead of the modules of upper significance are enabled by the module3S and state lookahead logic. Thus, the module2s within the counting path provide a 1cycle ookahead mechanism for triggering the module3Ss, and enabling the module2s to stay up a unbroken delay for all stages.
Module3Ss serve two main purposes. Their first purpose is to come back up with all counter bits associated with their ordered position and the second purpose is to enable future states in module3Ss in conjunction with stimulus from the state lookahead path. Fig. 7 shows the hardware schematic of module3S. And it is a parallel 2bit binary counter whose count is enabled by INS, that connects to the Q output of the preceding module2. It also provides onecycle look ahead mechanism.

State LookAhead Path: The state lookahead logical operation avoids the utilization of an overhead delay detector circuit that decodes the low order modules to get the enable
signals for higher order modules and enables all modules to be triggered concurrently on the clock edge, thus avoiding delay and rippling. The state lookahead logic is principally adoring the onecycle lookahead mechanism within the counting path. To enabling the subsequent states high order bits depends on early overflow pipelining across clock cycles through the module2S within the state lookahead path.
For example, in a 4bit counter constructed of two 2bit counting modules, the counting paths module2 decodes the loworder state Q1Q0=10 and carries this decoding across one clock cycle and enables Q3Q2=01 at module3 1 (see Fig. 1) on the next rising clock edge. This operation is equivalent to decoding Q1QO=11 and enabling Q3Q2=01 on the next immediate rising clock edge. The state lookahead logic expands this principle to an Xcycle lookahead mechanism.


PERFORMANCE COMPARISON Performance analysis of existing counter and proposed counter has been carried out using Xilinx ISE Design suit.It is observed that minimum input time arrival before clock is 6.214ns in existing system and 6.014ns in proposed system. And the maximum output required time after clock for existing system is 11.02ns and that of proposed system is 7.744ns.The average time delay of proposed system is 5.822ns , It is fewer than existing system.
Fig. 8 depicts the device utilization summary of existing system and Fig. 9 depicts the device utilization summary of proposed system. It is also noticed that power consumption is reduced to 141 P(mW) in this proposed design from 186 P(mW) in existing system.
Fig.8 Device Utilization Summary of Existing System
Fig.9 Device Utilization Summary of Proposed System.
The counting frequency of the proposed counter is almost constant, 2GHz, and almost independent of the counter size up to 128 bits and the hardware complexity is mainly determined by the counter size and the duplicated 1bit Johnson counters have a little effect on the overall complexity.

SIMULATION RESULTS
The proposed synchronous binary counter based on partitioning is implemented in Verilog and simulated using ModelSim SE 6.3f. Fig.10 shows the simulated result of 8bit parallel counter (called one by one in subcounter C3) and fig.11 depicts the simulated output of proposed binary counter realized with subcounter C1, subcounter C2 and subcounter C3.
Fig.10 Simulated result of parallel counter
Fig.11 Simulated result of proposed counter
The simulated counter output is also analysed in radix form without any further decodings techniques using ModelSim SE 6.3f.

CONCLUSION
In this brief, we presented a highperformance binary counter supported state look ahead logic. The counter structures main features are a pipelined paradigm and state lookahead path logic whose interoperation activates all modules concurrently at the systems clock edge, thereby providing all counter state values at the precise same time without rippling affects. Other
than that, the proposed counter design has used backward carry propagation and exploited redundant 1bit Johnson counters to cut back the quantity of flipflops and therefore the unwanted propagation delay caused by large fanout nodes. This structure avoids employing a long chain detector circuit typically required for big counter widths. additionally, this structure uses wellordered VLSI topology, that's designed in parallel counter architecture in subcounter C3, which is attractive for continued technology scaling because of two repeated module types (module2s and module3s) forming a ideal pattern and there is no increase in fanin or fanout because the counter width increases, leading to a uniform frequency delay that's attractive for parallel designs. Our proposed system is one step ahead than existing system in terms of number of gate count, delay, and power.
REFERENCES
[1] J. . Yuan, "Efficient CMOS counter circuits," in Electronics Letters, vol. 24, no. 21, pp. 13111313, 13 Oct. 1988, doi: 10.1049/el:19880891. [2] Y. Hyun and I. C. Park, "ConstantTime Synchronous Binary Counter With Minimal Clock Period," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 7, pp. 26452649, July 2021, doi: 10.1109/TCSII.2021.3054014. [3] S. AbdelHafeez, S. M. Harb and W. R. Eisenstadt, "High speed digital CMOS dividebyN frequency divider," 2008 IEEE International Symposium on Circuits and Systems, Seattle, WA, 2008, pp. 592595, doi: 10.1109/ISCAS.2008.4541487. [4] M. Kondo and T. Watnaba, Synchronous Counter, U.S. Patent no.5,526,393, June 1996.
[5] P. R. Thota and A. K. Mal, "A high speed counter for analogtodigital converters," 2016 International Conference on Microelectronics, Computing and Communications (MicroCom), Durgapur, 2016, pp. 1 5, doi: 10.1109/MicroCom.2016.7522592. [6] S. AbdelHafeez and A. GordonRoss, "A Digital CMOS Parallel Counter Architecture Based on State LookAhead Logic," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 6, pp. 10231033, June 2011, doi: 10.1109/TVLSI.2010.2044818. [7] P. Larsson and J. Yuan, "Novel carry propagation in highspeed synchronous counters and dividers," in Electronics Letters, vol. 29, no. 16, pp. 14571458, 5 Aug. 1993, doi: 10.1049/el:19930975. [8] M. Ercegovac and T. Lang, "Binary counter with counting period of one half adder independent of counter size," in IEEE Transactions on Circuits and Systems, vol. 36, no. 6, pp. 924926, June 1989, doi: 10.1109/31.90421. [9] M.R. Stan, A.F. Tenca, M.D. Ercegovac, "Long and fast up/down counters", Computers IEEE Transactions on, vol. 47, no. 7, pp. 722 735, 1998. [10] B. Nath and A. Majumder, "Binary Counter Based Gated Clock Tree for Integrated CPU Chip," 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2017, pp. 229233, doi: 10.1109/iNIS.2017.54 [11] J. E. Vuillemin, Constant time arbitrary length synchronous binary counters, in Proc. IEEE 10th Symp. Comput. Arith., 1991, pp.180183.