- Open Access
- Authors : Jayashree K , Divyansh Kumar Singh
- Paper ID : IJERTV11IS030103
- Volume & Issue : Volume 11, Issue 03 (March 2022)
- Published (First Online): 01-04-2022
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License: This work is licensed under a Creative Commons Attribution 4.0 International License
Development of S-Band Dual Digital Transmit Receive Unit for Air Surveillance Application
Bharat Electronics Ltd Bangalore, India
Divyansh Kumar Singh Bharat Electronics Ltd Bangalore, India
AbstractDual Digital Transmit Receive Unit(DDTRU) is an integrated module based on T/R module concept. The advantages of using T/R module concept are scalability, graceful degradation, adaptability, higher MTBF, transmitter power controlling.DDTRU unit consists of a T/R module, Analog Receiver, Digital receiver and a Power supply unit. T/R module is a Dual channel Transmitter and receiver based on GaN technology. Analog Receiver module takes the received RF (3.1 GHz to 3.5 GHz) from the Antenna and down converts to IF (60 MHz) through 2 stages of Analog Down conversion. IF is fed to Digital Receiver module which uses DDC digital down conversion techniques to extract the Baseband from IF, digitize the Baseband, convert to I and Q data, multiplex data of both channels and send out the I,Q data through an optical channel. Digital Phase shifters and attenuators present in T/R module and Analog receiver are controlled from Digital receiver.
Index TermsRadar, DDTRU,GaN technology, DC, Baseband.
T/R Modules are building blocks of Active Electronically Scanned Array (AESA) Antenna systems as they are
From the table, it is clear that GaN has high breakdown voltage, high heat resistance and high switching speed. Therefore, GaN device has been selected for power amplifier.
There will be two T/R modules in one DDTRU. In the transmit mode the RF input is passed through 6 bit digital attenuator , 6 bit digital phase shifter, switch, buffer amplifier, High Power amplifier (HPA), circulator, bi directional coupler through connector to antenna. The coupled RF sample pulse can be measured / detected for reporting the health of the RF amplification circuit.
On receive mode from antenna the RF flows through bi- directional coupler, receiver protector switch, limiter, LNA, band pass filter, amplifier, switch, digital phase shifter, digital attenuator to T/R switching unit, which in turn routes to First down convertor. The digital attenuator, digital phase shifter, switch and receiver protector switch will be controlled during transmit and receive mode as required by DRx through parallel lines.
configured for mounting directly behind the antenna element,
thereby minimizing losses and adding redundancy as compared to Passive Phased Array Antenna Systems. This
DA1. 1 to DA1.6 DP1. 1 to DP1.6
RF_ OUT. 1 to RF_ OUT.2
paper presents the development of S-band Dual Digital
– 2 to- 33 -6 -1
OUT To/ From Antenna
Transmit Receive Unit for Air surveillance Application.
DIGITAL ATTN DIGITAL PH SHIFTER
The phased array antenna 32 rows are powered by 32Dual
Digital Transmit Receive Unit (DDTRU). The DDTRU amplifies the carrier signal and provides to the antenna array for transmission. The unit receives the echoes from the targets,
50 dB RX BITE TRMSC
digitizes and generates I and Q data and sends to Digital Beam Former (DBF).
TRANSMIT RECEIVE MODULE
The module consists of transmit channel and receive channel in a single package with only one input and dual output. Transmit part of the system amplifies the 0dBm input signal to
+56dBm through a series of power amplifier modules.
The Transmit chain is realized by power amplifier modules based on GaN technology. The comparisons of characteristics of GaN and silicon carbide are shown in the table 1.
Electric field for breakdown
Figure of merit
In this T/R module the HPA is GaN based amplifier which generates heat and requires liquid cooling provision (external) to extract the heat out. To extract heat out it is essential to mount the GaN device closer to the chassis or on the chassis which can be mounted on cold plate.
The second most important device is LNA. The overall noise figure (NF) of 3.5dB of the receiver chain is defined by the selection of the LNAs gain and noise figure. Also the 1dB compression point (-5dBm) of the LNA defines the maximum input handling capacity of the receive chain. In turn both NF and 1dB compression point defines receiver dynamic range.
ANALOG RECEIVER UNIT
Analog Receiver Unit down converts the received RF (3.1-
3.5 GHz) to IF (60 MHz). This is achieved through 2 stages of down conversion.
First down converter chain comprises of 6 bit digital attenuator as MSTC, amplifier, coupler,6 bit digital attenuator as AMSTC, RF Band Pass filter, matching circuit, Mixer-I followed by First IF band pass filter. There is two numbers of first down converters in a DTRU.
anti-aliasing filter and decimation module are 16 bit I and 16 Bit Q samples available at 5MHz/2.5MHz.
MSTC1. 1 to
6BIT MSTC1. 6
AMSTC1. 1 to
FDDP1.1 to FDDP1.6 6 BIT
0. 60G IF1.1 to IF 2.1
DIGITAL PH SHIFTER
Second down converter comprises of Coupler, Mixer II, Second IF Band Pass Filter, IF amplifier, Digital attenuator (Fast AGC), Amplifier, Limiter, followed by 2 IF filter banks (one selectable) and coupler, through which it is fed to Digital Receiver. The bandwidths for IF filter banks are 5MHz and 2.5MHz. One of the IF filter banks will be selected by RF switches operating in tandem, depending upon the operating pulse width.
All the control signals namely Fast AGC for IF Gain Control, IF Filter switch controls are provided by Digital Receiver. LO2 input is fed by LO2 buffer module. The output of the second down converter is fed to DRx. There will be two such Second down converters in one DTRU.
6BIT to AGC1.6
BPF AMPLIFIER DIGITAL AMPLIFIER LIMITER ATTENUATOR
DIGITAL RECEIVER UNIT
The S-Band Digital Receiver (DRx) is based on Xilinx Artix FPGA. Major functions of the DRx are Digitization of 2 IF signals, 2-Channel Digital down Conversion and high speed serial communication with DBF unit. Two 16-bit ADCs are used for sampling the two IF channels with isolation of 60dB and sampling clock used is 50MHz.
The phase detector module decomposes the incoming 16 bit data from the digitization module into in-phase and Quadrature-phase components and mixes the data with 10MHz sine and cosine samples generated by an NCO at a sampling rate of 50MHz. The output of this stage is 16 bit I and Q data for each channel for filtering and decimation.
The sampled quadrature output stream is at 5/2.5MSPs depending on the bandwidth selection.Finally the baseband signal is passed through a Low Pass Filter and decimation filter to get the signal of interest. The filter cut-off is selected so as to allow maximum signal of interest. The output of the
Fig 4: Simulated DDC output for 60Âµs LFM and BW 2.5MHz
Fig 5: Simulated DDC output for 60Âµs LFM and BW 5MHz
Fig 6:Realized DDTRU
Table 2: Receiver Gain
Table 3: Receiver Noise Figure
Table 4: Transmit Output Power
Fig 7: DRx Output-In Phase channel 1
Fig 8: DRx Output- Q phase channel 1
Fig 9:DRx Output- In phase channel 2
Fig 10: DRx Output- Q Phase channel 2
Dual Digital Transmit Receive prototype unit has been developed. Set of tests are carried out to evaluate the performance of DDTRU and found satisfactory, complying with the requirements.
The authors express their sincere thanks to the management of Bharat Electronics for giving the opportunity to work in this area of research and for their valuable support during the course of the project.