 Open Access
 Total Downloads : 602
 Authors : Victor Du John H, Jackuline Moni D
 Paper ID : IJERTV3IS11173
 Volume & Issue : Volume 03, Issue 01 (January 2014)
 Published (First Online): 30012014
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Design of Low Power ADC Using 0.18m CMOS Technology
Victor Du John H a, Jackuline Moni D b, *
a Assistant professor, Karunya University, Coimbatore, Tamil Nadu, India.
b Professor Karunya University, Coimbatore, Tamil Nadu, India.
Abstract
The dual slope integrating analog to digital converter (ADC) is an efficient one for wireless transmission of ECG signals. Normally the dual slope ADCs are used for high resolution applications and the accuracy is very high. The main advantage of the ADC design is its high speed with low power. The dual slope ADC consists of integrator, comparator and a ten bit binary counter. To design integrator by using low power opamp; comparator by using CMOS transistor and a binary counter by using JK flipflop which are consume less power. These components have to be incorporated in a system with a single control switch that produces the control signals and dual ramp at the input side. Finally the digital output is occur at the terminal of binary counter. This work was done using CADENCE Virtuoso environment with 180nm technology.
time interval, the integrator's output at the end of this time interval is proportional to the average value of the input
Fig. 1. Block diagram of Dual Slope ADC.
Keywords: ECG, ADC, CMOS, binary counter

INTRODUCTION
Analog to digital converters are the interface between
V (T ) 1
0 RC
T
Vt dt
0
(1)
the analog input signal and digital signal processing block. Most of the real world signals are analog in nature, they are continuoustime, and continuousvalued signals etc., Compared to analog signals, digital signals have the following advantages:

It is immune to electrical noise

It can be manipulated easily

It is easy to store

It is easy to copy and transfer
The type of ADC used is an indirect method of A/D conversion, where the analog voltage is converted to a time period measured by a counter. An electronic switch selects the circuit's input as an unknown analog voltage or a reference voltage. At the initial condition, the counter is reset and then switch selects the unknown analog voltage to the integrator. The counter is enabled when the output of the comparator is zero (Vo =0), it counts for a fixed time interval until it flows. For a constant analog input, the slope of integrator's ramp output is proportional to the unknown input; hence the output voltage of the integrator at the end of the fixed time interval (T) is proportional to the analog output [1]. If the analog input (Vi) varies during the fixed
where R is resistance in and C is capacitance in F. At the end of clock period T, the input of the integrator is switched from the analog input to the reference voltage, making the integrator ramp output with a fixed positive slope [2]. The counter counts the integrators output to reach the comparator's threshold where the counter is stopped at required time period. Normally during the conversion period the input voltage varies between 0 to vin.


DUAL SLOPE ADC
The blockdiagram of the dualslope integrating A/D converter is shown in Fig. 1. This converter is based on the same principle as the singleslope converter. It converts the analog input to time, and the measure the time by counting fixedfrequency pulses [3], [4]. The improvement over the singleslope converter comes from using the same integrator to integrate first the input voltage Vi and then the reference Vref. As a result, the conversion function of the dualslope converter does not depend on exact values of the timeconstant RC or the clock period T, the integrator is built using RC around an opamp. Switches S1, S2 are used to bring either the input Vi or the reference
Vref to the input of the integrator. Zero crossing of the
integrator output Vint is detected using the voltage comparator. An (n+1)bit binary counter with reset R and
clock CLK inputs is used to count the number of fixed frequency pulses CLK generated by an external clock during the conversion period. The most significant (n+1)th bit of the counter is used as the signal Q to control the switches S1 and S2. All inputs to the counter and the latch are assumed to be risingedge triggered. At the beginning of a conversion period, the (n+1) bit binary counter and the integrator are reset by the signal R. When R goes low, the switch S1 is turned off and the fixedfrequency clock pulses CLK are passed to the clock input of the binary counter. The switch S1 is on and the switch S2 is off, so that the integrator output, assuming constant Vi is
installed between the voltage to be measured and the reference voltage (negative value). Depending on the operation, a switch connected in parallel with the integrator capacitor for resetting the integrator in two consecutive rounds (by discharging the integrator capacitor) [12]. The switches are controlled by dedicated controller. The conversion takes place in two phases; one is the runup phase, and the other is the rundown phase. In the first stage, the voltage which is supplied to the integrator is to be measured. During first part i.e. the runup phase, the switch selects the measured voltage as the input provided to the integrator. Then the integrator is allowed to ramp for a
Vint
(t) vi t
RC
(2)
fixed interval of time for the charging of the capacitor.
During the second part i.e. rundown phase, where the input to the integrator is a reference voltage (negative), the
At the end of the first interval t1, the counter counts up through 2n pulses, and goes from 011.1 to 1000. The (n + 1)th bit Q goes high, the switch S1 is turned off and the switch S2 is turned on. Therefore the length of the interval t1 is given as
switch selects the reference voltage as the input voltage of integrator. The time taken for the integrator's output to return to zero value is measured during this phase.
DESIGN OF INTEGRATOR USING OPAMP
1
t 2n t
(3)
The mathematical operation of integration can be simulated by replacing the feedback resistor in an inverting
so that the integrator output at the end of this interval is
OP AMP circuit and inserting a capacitor. Figure 2 shows
Vint
(t1)
vi 2n T RC
(4)
the ideal opamp integrator
in the second interval Vref is integrated using the same integrator, so that
Vin t
(t ) V1

vref
RC
t t1
(5)
the conversion ends at the time when the integrator output crosses zero. The length of the second interval t2 is
t2
v1 RC
vref
(6)
during the second interval, the counter counts up N pulses, the final count N is given by
Fig.2. Opamp Integrator
N 2n
v1 vref
(7)
The Integrator is a circuit using opamp that performs the mathematical operation of Integration. The integrator acts like a storage element that produces a
This is the ideal conversion function [13]. The most
important point to note here is that both RC and T cancel out from the final expression for N, so that accuracy of the converter is not affected by the exact values of T, R or C. The choice of R, C and T is still important in practical issues because the clock rate and voltage variation is within the limit of the design, and the voltage variations are also within the component and supply limits. For nbit conversion, the conversion time goes up to 2n+1T, where T s the period of the external clock used to measure the times t1 and t2. This limits the achievable sampling rate of the dualslope A/D converter.
PRINCIPLE OF OPERATION
voltage output which is proportional to the integral of its input voltage with respect to time [14]. In other words the magnitude of the output signal is determined by the length of time a voltage is present at its input as the current through the feedback loop charges or discharges the capacitor as the required negative feedback occurs through the capacitor. If an ideal op amp circuit operation is assumed, no current will flow into the inverting terminal of the amplifier due to the infinite input impedance [5]. Also, the voltage between the inverting and noninverting terminal is equal due to the effects of the negative feedback. This means that the voltage at the inverting terminal is at ground potential. So, If= – IC and Iin = Vi/Rin.
The basic integrating ADC circuit consists of a switch, an integrator, a timer that determines how long to integrate the
V 1
0 C
ic (t )dt
(8)
unknown and measures the duration of the reference integration, a controller, and a comparator. The switch is
the opamp for an integrator is designed using the CMOS transistors and the ratio of the CMOS are designed
according to the input and output requirements of the amplifier [1]. It gives the design of a two stage opamp and the structure of the two stage opamp is shown in the fig.3.
Fig.3. CMOS opamp
Fig.6. Comparator Schematic
ds
DESIGN OF COMPARATOR
Ids
k w (V 2 l gs
Vth
)2 (1 V )
(9)
The comparator is a circuit that compares one analog signal with another analog signal or a reference voltage and outputs a binary signal based on the comparison. The comparator is basically a 1bit analogtodigital converter [7]. The symbol of comparator is shown in the fig.5.
Fig.5. Schematic symbol of Comparator
The comparator is an analog circuit used to compare the sampled input signal and the reference signal. In this paper a low power two stage comparator is used which works in the positive feedback mode. Fig.6 shows the schematic diagram of the 2 stage comparator. The main advantage of using this kind of comparator is no power has been wasted from the supply when the comparator is not working stage [8]. The biasing circuit gives the biasing current to the comparator. The biasing current is given as
The W/L ratios are calculated according to the biasing currents of the transistor. The differential pair transistors Q3 and Q4 compare the two input signals and the error signal is amplified at the output stage. All the other transistors act as for switching operation [9]. The comparator consumes 13.8ÂµW when the supply voltage is 1.8V.


RESULTS AND DISCUSSION OUTPUT OF AN OPAMP
Fig.8. Schematic Diagram of Opamp
In this work, 10 bit binary counter is used to convert analog signal to digital signal, where it consists of JK flip flops, which has been driven by the synchronous clock pulse.
Fig.9. Output of Opamp
The schematic diagram of the designed opamp and its output response shown in the fig.8 & 9 which is in the inverted amplified form. The designed opamp is producing the output power of 0.25mW.
Fig.10. AC Response of Opamp
Fig.11. Gain of Opamp
The figure 10 and 11 shows the output AC response and the output gain of the designed opamp. The gain value of the opamp is 47db and the phase value is 180 degrees.
OUTPUT OF OPAMP INTEGRATOR
Fig.12. Schematic Diagram of Opamp Integrator
Fig.13. Output of Opamp Integrator with sine wave
The schematic diagram of the designed integrator using cadence tool is shown in the figure 12. The value of the feedback capacitor is 90nf and finally the obtained waveform is shown in the figure 13. The integrator will produces the cosine waveform when the input is sine wave and it produces triangular wave when the input is square pulses as shown in fig.14.
Fig.14. Output of Opamp Integrator with pulses
OUTPUT OF COMPARATOR
Fig.15. Schematic Diagram of comparator
OUTPUT POWER OF DUAL SLOPE ADC
Figure. 5.18. power of Dual slope ADC
Fig.16. Output response of comparator
0.2
0.19
0.18
0.17
power(mW)
0.16
0.15
0.14
0.13
0.12
0.11
power Variation plot
The schematic diagram of the designed two stage comparator is shown in the figure 15 and the corresponding output of the comparator is shown in the figure 16 which shows the compared output of sine wave and a reference signal.
OUTPUT OF DUAL SLOPE ADC
0.1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
voltage(v)
Figure. 5.19. power variation plot of SARADC
The fig.5.18 shows the power consumption of Dual slope ADC when the operating voltage is 1.8V. The variation of plots from 1.1V to 1.8V is shown in the fig.5.19.
DNL = +0.025 LSB, 0 missing codes (DNL<0.9)
0.03
DNL [LSB]
0.02
0.01
0
0.01
1
INL [LSB]
0.5
0
0 100 200 300 400 500 600 700 800 900 1000
code
INL = +0.91 LSB
0 100 200 300 400 500 600 700 800 900 1000
code
Figure. 5.20. INL and DNL for ADC using matlab
Fig.17. Output of ADC showing digital bits
Finally the output of the dual slope ADC is obtained using the designed blocks and the input analog signal and the corresponding output bits are shown in the figure 17.
The INL and DNL for an analog to digital converter is calculated using the histogram principle and linearised histogram principle in matlab. The input vector given to the calculation is the ECG data observed from the body. Since the obtained ECG signal is noise less the INL and DNL values will be less as shown in the fig.5.24.
PARAMETERS OF DUAL SLOPE ADC PARAMETERS VALUES
Resolution 10 bits
Technology 180nm
Supply 1.1V to 1.8V
Input range 10mV
power 110.4ÂµW to 202.4 ÂµW
ENOB 4.69 bits
SNR 29.9 db
INL 0.91 LSB
DNL 0.025 LSB
I supply 46ÂµA
FOM 18.28ÂµJ

CONCLUSION
In this work, dualslope ADC is operated at 1.1v with high data rate which consumes power of 110.4ÂµW. In contradict, a system operated at 1.8v which consumes power of 202.4 ÂµW. This shows that applied voltage is proportional to the power consumption of the system. This system has been designed in CADENCE Virtuoso Analog Design environment with 180nm technology. . In future work, to implement dualslope ADC for the wireless applications of ECG system.

REFERENCES

Andriana Voulkidou, Lambros Mountrichas, Stylianos Siskos An Adaptable 14Bit Dual Slope ADC with Wide Input Range Procedia Engineering 47 (2012) 997 1000.

Alberto RodrÃguezPÃ©rez, Manuel DelgadoRestituto and Fernando, MedeiroInstitute of Microelectronics of Seville, Power Efficient ADCs for Biomedical Signal Acquisition 2009.

ChiHang Chan, SaiWeng Sin, SengPan U,A 10 bit 100MS/s ReferenceFree SAR ADC in 90 nm CMOS

Daniel Schinkel, Eisse Mensink, Eric Klumperink, Ed van Tuijl, Bram Nauta, A DoubleTail LatchType Voltage Sense Amplifier with 18ps Setup+Hold Time

Ehsan Rahiminejad and Reza Lotfi, A LowPower Architecture for Integrating AnalogtoDigital Converters 2010.

Fan Hua, Wei Qi, Kobenge Sekedi Bomeh, Yin Xiumei,and Yang Huazhong, (Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 2008, China) An 8bit 180kS/s differential SAR ADC with a timedomain comparator and 7.97ENOB.

Hamed Mazhabjafari, 16 channel CMOS Impedance Spectroscopy DNA analyzer with Dualslope multiplying ADC IEEE trans on biomedical circuits and systems oct 2012.

Hasan Krad, A DualSope Integration Based Analog toDigital Convertor, American J. of Engineering and Applied Sciences 2 (4): 743749, 2009.

James L. McCreary, student member, IEEE, and Paul
r. Gray, member, IEEE, allmos charge redistribution analogtodigital conversion techniquespart1.

Jens Sauerbrey, Doris SchmittLandsiedel, Roland Thewes, A 0.5V, 1W Successive Approximation ADC, IEEE Journal of Solid State Circuit, IEEE 2002.

Jie Yuan, Ho Yeung An activitytrigerred 95.3 dbDR
75.6 db THD CMOS Imaging sensor with digital calibration, IEEE journak of SSC oct 2009.

MAXIM Application note 1080 Understanding SAR ADCs Mar 01, 2001.

Phillip DAllen.,Douglas R Holberg., CMOS Analog circuit design second edition Oxford university press.

Pratibhadevi Tapashetti, Ankur Gupta, Design and Simulation of Op Amp Integrator and Its Applications, International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 8958, Volume1, Issue3, February 2012