Design of Low Power 64-Bit SRAM Using 13T Cell

DOI : 10.17577/IJERTV2IS50703

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Design of Low Power 64-Bit SRAM Using 13T Cell

Sriram K V1, Ranganna Ramappa Naik1, Pavan Nandan S G1, Kendaganna Swamy2

1Department of Instrumentation Technology, RVCE.

2Assistant Professor, Department of Instrumentation Technology, RVCE.


A new 13T SRAM cell has been designed at 180nm for low power and high performance. It employs single line read/write architecture. The output of the cell features a full rail-to-rail swing. The static power dissipation of 13T SRAM cell is 283.14µW, which constitutes solely 35% of 6T SRAM cell and comprises of higher SNM. The 64-bit SRAM memory was designed using the 13T cell and has a total power dissipation of 4.5mW.

  1. Introduction

    Reducing the static power dissipation is a major issue in the current low power design trend. Different design styles have been introduced to reduce static power dissipation. In high density circuit such as memory, reducing static power will bring down a major portion of power consumption [4,6]. This paper discusses a new SRAM cell design for low power purpose at 180nm level.

  2. Working of 6T SRAM

    The conventional 6T SRAM is shown in Fig 1. It has six transistors which form the two access transistors and two inverters connected which are connected back to back. The widths of these transistors are chosen carefully so that the cell has better read-write stability [1-2, 5]. The widths of the pull-down, pull-up and access transistors should be as follows.

    Figure 1: 6T SRAM cell

    1. Reading

      For read operation first both bl and blb are precharged to and then the WL is enabled. Based on the data stored in the cell, one of the bit line discharges. The bit lines are connected to a sense amplifier, which amplifies the signal and produces a rail-rail-swing in the right direction.

    2. Writing

      For writing, the data and ~data are connected to the bl and blb and then the WL is enabled. Now, the data is forced into the inverters and hence the data is written into the cell.

  3. Working of 13T SRAM

    In the new design, we has used forced stack technique and introduced a pass transistor between the back-to-back connections of the two inverters. The design features dedicated single line read/write architecture. The dedicated read & write port improves the noise margin of the SRAM. A 13T cell is shown in Fig 2.

    Figure 2: 13T SRAM cell

    1. Writing

      The data_write line is precharged to the required state (i.e. logic 0 or logic 1) and then WL is enabled. After enabling WL, the data is written into the cell. The pass-transistor cuts the feedback from the second inverter and is immune to any noise caused by the second inverter.

    2. Reading

      The data_read line is precharged to Vdd prior to the application of RL signal. Once RL is enabled, based on the data stored in the cell data_read line retains or discharges its charge.

  4. 64-bit SRAM design

  5. Result

    Figure 5: Final module

    The 13T cell is replicated to form an 8×8 SRAM array. Lyon-Schediwy decoder is used to decode the address. A sense amplifier based on is used. The entire module is designed at 180nm technology.

    Figure 3: 8×8 SRAM array

    Figure 4: Decoder

    Simulations are performed at 180nm using cadence tool. The static power, dynamic power and total power dissipation of different SRAM designs [1,2] are tabulated in table 1.

    The SNM for each design is also tabulated in table

    2. The SNM graph of 13T SRAM is shown in fig. The simulated waveform of 64-bit module is shown in fig. the static and dynamic power dissipation of the 64-bit module is 4.513mW and 22µW respectively at 200MHz.

    Table I: Power dissipation in various SRAM design.


    Dynamic Power

    Static Power

    Total Power

















    Table II: SNM of various SRAM design


    Read SNM (V)

    Write SNM(V)













    International Journal of Engineering Research & Technology (IJERT)

    ISSN: 2278-0181

    Vol. 2 Issue 5, May – 2013

  6. Reference

  1. V. Singhal and B. Singh, 64-bits low power cmos sram by using 9t cell and charge recycling scheme, in Devices, Circuits and Systems (ICDCS), 2012 International Conference on, pp. 29-33, March 2012.

  2. A. Jain and S. Sharma, Optimization of low power 7t sram cell in 45nm technology, in Advanced Computing Communication Technologies (ACCT), 2012 Second International Conference on, pp. 324-327, Jan. 2012.

  3. N. Shibata, M. Watanabe, and H. Okiyama, A high-speed low-power multi-vdd cmos/simox sram with lv-ttl level input/output pins, write/read assist techniques for 1-v operated memory cells, Solid-State Circuits, IEEE Journal of, vol. 45, pp. 1856-1869, Sept. 2010.

  4. N. Tzartzanis, Static memory design, in High-PerformanceEnergy-Effcient Micro- processor Design (V. Oklobdzija and R. Krishnamurthy, eds.), Series on Integrated Circuits and Systems, pp. 89{119, Springer US, 2006.

  5. V. Sharma, F. Catthoor, and W. Dehaene, Sram bit cell optimization, in SRAM Design for Wireless Sensor Networks, Analog Circuits and Signal Processing, pp. 9-30, Springer New York, 2013.

  6. J. Singh, S. Mohanty, and D. Pradhan, Single-ended sram bitcell design, in Robust SRAM Designs and Analysis, pp. 57-82, Springer New York, 2013.

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