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**Authors :**Vigneshwari.R, Jenopaul.P -
**Paper ID :**IJERTCONV1IS06102 -
**Volume & Issue :**ICSEM – 2013 (Volume 1 – Issue 06) -
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**ISSN (Online) :**2278-0181 -
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**License:**This work is licensed under a Creative Commons Attribution 4.0 International License

#### Design of a Hybrid Adder using QCA in MAC unit

VIGNESHWARI.R (PG scholar),

Department of ECE,

PSN College of Engineering and Technology, Tirunelveli.

vigneshwari.raji@gmail.com

JENOPAUL.P (Professor)

Department of ECE,

PSN College of Engineering and Technology, Tirunelveli.

jenopaul1@rediffmail.com

Abstract – Quantum dot cellular automata design of a hybrid adder is proposed to reduce the area, delay and power consumption of an adder. In previous Quantum dot cellular automata design of a ladner-fischer prefix adder has been implemented. Hybrid adder has a better performance than the ladner-fischer adder. Hybrid adder has a minimum area, delay and power consumption. In this paper we are going to implement the hybrid adder in the application of multiple accumulator units.

Index TermsHybrid adder, LadnerFischer adder, nanoelectronics, quantum-dot cellular automata (QCA), MAC unit.

I NTRODUCTION

Nanoelectronics devices have been of interest to the research community during the last decade. These include carbon nano tubes, silicon nanowires, resonant tunneling diodes, and others. These devices have emerged as alternatives to the traditional VLSI technology based on CMOS. Conventional device physics is based on a free electron model and as device dimensions shrink (to be of the order of the wavelength of an electron), this model is not appropriate since the energies an electron is allowed to have become discrete. A recent book on nano electronics

[1] provides a good introduction to the quantum mechanics of electrons, notions of free and confined electrons as well as single electron and many electron devices. One of the devices suggested in the literature as an alternative to the traditional CMOS-based technology is the quantum-dot cellular automata (QCA). In QCA, the device used for logic is also used for interconnect. The basic logic gates in the QCA architecture are the majority gate (also referred to as the majority voter) and the inverter. The focus of this paper is on design of arithmetic circuits in QCA. In particular, our interest is in efficient design of multi-bit adders. One possible approach is based on examination of the best adders (meeting some criteria) developed for existing technologies such as CMOS for adaptation to new ones such as QCA. However, algorithms that have been optimally implemented in one technology may not necessarily be the best in a different technology [2].In thispaper, we pursue the following two directions. We consider area occupied by basic logic elements in a QCA design and examine optimization of logic. We also examine development of special adders for the QCA model. The quantity of logic also indirectly determines the amount of QCA wires in a design. Prior work on adder designs has examined a few directions. Wang et al. [3] present an efficient design of a 1-bit QCA adder that uses three majority gates and two inverters. Majority logic reduction for several three variable Boolean functions is studied in

[4] a performance comparison of some QCA adders is presented in [5]. Modular design of conditional sum adders is studied in [6]. Tang et al.[7] have presented a QCA circuits design methodology based on traditional CMOS circuits design flow and a SPICE model. Ripple carry and carry look ahead adder designs in QCA are presented in [8]. Robust QCA adder designs that exploit proper clocking schemes are proposed in [9]. Probabilistic analysis of molecular quantum-dot cellular adders is presented in [10]. Reliability of magnetic QCA adders and electrostatic QCA adders is studied via probabilistic transfer matrices in [11]. Robust adders based on QCA are described [12]. A model of QCA circuits using Bayesian networks is presented in [13] .Hierarchical probabilistic macro modeling for QCAcircuits is described in [14] . Energy dissipation per clock cycle in QCA adder circuits is studied in [15]. Cho and Swartz ladner [16] have presented design of a carry flow adder and a multiplier in QCA. Synthesis tools for QCA have been reported in [17] and [18].

To the best of our knowledge, there is no prior work that has examined in detail properties of basic logic elements in QCA for obtaining very efficient adder designs. Further, special algorithms for addition in the QCA model are limited. This paper begins by developing a QCA-based solution for the LadnerFischer prefix adder. The paper then proceeds to develop an adder that is a hybrid of LadnerFischer and ripple carry adder. This hybrid adder is shown to be well-suited to the QCA model. We demonstrate that the hybrid adder has lower delay (in view of parallelism) than the best existing adder designs in the literature. Further, the hybrid adder compares well with

existing adders in terms of area of the QCA design (since it incorporates best features of ripple carry adders). We also show that the hybrid adder has a smaller area-delay product than existing adder designs in QCA. Results of simulation using QCA Designer [17] support the theory presented. The remainder of this paper is organized as follows. Section II provides the basic notations pertaining to QCA. Section III presents QCA design of QCA design of the proposed hybrid adder. Section IV presents the details of simulation in QCA Designer. Section V presents comparisons with prior work.VI presents the details of multiplier accumulator unit. Conclusions are presented in Section VII.

Fig. 1. QCA cells with electrons indicating possible polarizations.

BASICS OF QCA

In QCA, the logic states are not stored as voltage levels [19]. Instead, the location of individual electrons determines the bi-nary state. Fig. 1 depicts QCA cells. Each QCA cell is a set of four dots positioned at the four corners of a square. Each QCA cell is occupied by two electrons. Several approaches have been suggested for computation with an array of QCA cells. One approach is based on transferring the array to an excited state from a ground state by merely applying input data (without explicit clocking). The array is expected to settle to a new ground state. However, sometimes the transition may result in a meta stable intermediate state. To facilitate transfer to a new ground state, another approach based on clocking has been suggested. Clocking (by application of an appropriate voltage to a cell) leads to adjustment of tunneling barriers between quantum dots for transfer of electrons between the dots.

clocking, involves generation of a potential field by a system of submerged electrodes. The former clocking scheme is adopted in this paper since the CAD tool mused for simulation supports zone clocking and further, prior works on adders are only based on this clocking scheme. Primitives in the QCA model consist of a wire, inverter and majority gate and are depicted in Fig. 3. Fig. 4 shows the operation of a wire in different clock zones. A majority gate in QCA takes three inputs and implements the majority function of three Boolean variables a, b and c. The majority function is denoted by M (a,b,c) is defined as M (a,b,c) =ab+bc+ca.

Fig. 2. QCA clock zones.

Clocking is performed in one of two ways: zone clocking and continuous clocking. In zone clocking , each QCA cell is clocked using a four-phase clocking scheme as shown in Fig. 2. The four phases correspond to switch, hold , and release and relax. In the switch phase, cells begin un polarized and with low potential barriers but the bar riers are raised during this phase. In the hold phase, the barriers are held high while in the release phase, the barriers are lowered. In the lat phase, namely relax, the barriers remain lowered and keep the cells in a un polarized state. An alternative to zone clocking, called continuous

Fig. 3. QCA wire, inverter, and majority gate.

Fig. 4. Operation of a wire in different clock zones.

A QCA design permits two options for crossover, termed coplanar crossover and multilayer crossover. While the coplanar crossover uses only one layer but involves usage of two cell types (termed regular and rotated), the multilayer crossover uses more than one layer of cells (analogous to multiple metal layers in a conventional IC). Multilayer crossover is predominantly used in this paper for wire crossings since the design is fairly simple. Some results for coplanar crossover are also presented for comparison purposes.

NEW HYBRID ADDER IN QCA

Design of 8- and 16-bit Hybrid Adder in QCA While the LadnerFischer adder supports parallelism, the requirement of majority gates (which contributes to the overall area) is quite high. The large number of majority gates has an indirect effect on the wire (delay and amount). It is therefore of interest to explore ways of reducing the area. From the literal true, it is known that ripple carry adders are simple and have low area requirement. This fact is taken advantage of in our design of a hybrid adder. In this section, we present an adder which is a hybrid of the LadnerFischer adder and a ripple carry adder. We show that this hybrid adder has advantages especially in the QCA domain over the LadnerFischer adder as well as the ripple carry adder in terms of delay. Further, the hybrid adder requires a substantially lower number of majority gates for different adder sizes in comparison to a LadnerFischer adder.

Fig. 5. Tree structure for C8,C12 and C16 carries.

Fig. 4 shows a general tree structure for computation of C16,C12 ,C8 and C4 Parallel prefix graphs for various adders can be derived from this. The proposed hybrid adder is based on the idea that a number of carries not explicitly labeled in Fig.4 (in particular,C1,C2,C3,C4,C5,C6,C9,C10,C13,C14 ) can be computed using a ripple carry style leading to a highly efficient adder in terms of majority gates and delay. We will investigate first the majority gate requirement for carries C16, C12 ,C8 and C4 With reference to Fig. 4, we note that C16, C12 and C8 depend on G1,G2 and G3 respectively. Let Gj,,j = 1, 2,3 represent generate (gi+3,pi+3)o(gi+2,pi+2)o(gi+1,pi+1)o(gi,pi), where I = 4, 8, and 12, respectively. Gj can be expanded as Gj can be expressed using majority gates. Using Proposition 1, we note that gi+1

+ pi+1gi can be expressed as M(gi+1,pi+1,gi). Direct evaluation of Gj using above equation requires up to ten majority gates since gi+3,pi+3,gi+2,pi+2,gi+1,pi+1 and gi require one majority gate each besides the three majority gates shown explicitly in the expression for Gj. Consequently, a total of 30 majority gates is required for G1,G2 and G3 We now present a new result that reduces the majority gate requirement substantially.

Proposition 1: Let f1,f2 and f3 be three Boolean functions such that f1=x1y1 and f2=x2+y2 where x1 and y1 are two binary inputs.Then

M( f1,f2,f3 ) = M( x1,y1,f3 ).

Proof: M(f1,f2,f3) is given by M(f1,f2,f3) = f1f2 + f1f3 + f2f3

= f1f2 + ( f1 + f2 )f3

= x1y1(x1 + y1 ) + ( x1y1 + x1 + y1 )f3

= x1y1 + ( x1 + y1)f3

= M( x1,y1,f3 ).

Majority logic expressions for compute c8,c12 and c16 can now be given as shown in below equation. The details are given in the equation

C8 = M(G1,p7,p6p5p4c4) C12 = M(G2,p11,p10p9p8c8)

C16 = M(G3+ p15p14p13p12 G2, + p15,p14. . .c8).

Fig. 6. Four-bit hybrid adder block

The requirements for majority gates for c7,c8,c11,c12, c15 and gates are required (including the requirements for pis and g4 , majority gate for AND of p6 and p5 , AND of p4 and c4 , AND of p6 p5 and p4c4 theOR operation). For in c8 of above equation three majority gates are required (by reutilization of majority gates for p6, p5, etc.) since p7,G1 and M() require one majority gate each (G1 is given by M(x7,y7,M(x6,y6,M(x5,y5,g4))) and the majority gates involved in computation of c7 , namely M(x6,y6,M(x5,y5,g4)), p6p5p4c4) are reutilized for G1and c8). For c11, the calculations are similar to c7 and so ten majority gates are required.

For c12 , the calculations are similar to c8 , therefore three majority gates are required. For c15, the calculations for the part given by M(x14,y14,M(x13,y13,g12))+ p14p13p12G2 are similar to c11 hence ten majority gates are required. For + p14p13p12p11p10p9p8c8 , four majority gates are required (one majority gate for AND of p11 with p10p9p8 , one majority gate for AND of p14p13p9p12 with p11p10p9p8 , one majority gate for AND of p14p13p12p11p10p9p8 with c8 and one for the overall OR operation). Hence, altogether 14 majority gates are required. For c16, four majority gates are required (one for M(.) and three for above equation and this is in view of the following facts: 1)c16 computation reutilizes majority gates involved in c15 and this is similar to the manner in which c8 computation reutilizes majority logic used for c7 ;

2) the first term within M() in c16 equation is realized as shown in above equation; and 3) In above equation G3,p15 and M(G3,) require one majority gate each. Fig. 5 illustrates the generation of carries of a 16-bit hybrid adder. The calculation of the remaining carries, namely ,ci,i = 1,

2, 3, 4, 5, 6, 9, 10, 13, 14 can be done in ripple-carry style (each cican be expressed in terms of M(xi-1,yi-1,ci-1) ). For example, carry c5 can be calculated as M(x4,y4,c4) . So ten majority gates are required for these ten carries. The requirements for sum are the same as for the Ladner Fischer adder. In particular, 32 majority gates, and 16 inverters are required for a 16-bit hybrid adder. The total requirements are summarized by Proposition 2.

Proposition 2: A 16-bit hybrid adder requires 86 majority gates and 16 inverters.

Remark :In Fig. 5, some of the carries computed in ripple carry style are shown enclosed in ellipses (& labelled with

$).

For example C5 and C6 in Stage 3 are computed in ripple carry style with one majority gate (delay) difference between C5 and C6 . However, C7 and C8 are computed in prefix style and in parallel with C6 . Similarly, in Stage 4, C9 and C10 are computed in ripple carry style but C10 is computed in parallel with C11 and C12 (the latter are obtained in prefix style). The result on majority gates for a 16-bit hybrid adder can be compared with that of the 16-bit LadnerFischer adder. In particular, 45 majority gates are reduced here which is approx-imately reduction by 35%.

Remark : One can comment on the latency reduction for 8- bit Hybrid adder in comparison to an 8-bit LadnerFischer adder. In the former, the critical path for c8 involves six majority gates while the same is required for c8 in Ladner Fischer .

However, in the latter, one clock zone delay is incurred in obtaining g0 and p0 (they can be obtained in parallel, hence just one zone delay) whereas in the hybrid adder, g0 s and p0 s are not required at all thereby a reduction of 0.25 units (corresponding to one majority gate) of delay is possible. We also note that besides g0 , computation of several other gs is skipped in the case of a hybrid adder. These include g1, g2, g3, g4, g5, g6 and g7 for an 8-bit hybrid adder. This leads to a substantial reduction in majority logic. However, the reduction is delay is only

0.25 units (due to the computation of g s happening in the same stage). Further reduction in delay (in a hybrid adder) is dependent isdependent on the clock zone for wires.

IV . SIMULATION RESULTS OF HYBRID ADDER

In this section, we present the simulation results for hybrid adder.

V . COMPARISON OF DIFFERENT ADDER

MULTIPLIER- ACCUMULATOR UNIT

MAC is composed of an adder, multiplier and an accumulator. Usually adders implemented are Carry-Selet or Carry-Save adders, as speed is of utmost importance in DSP One implementation of the adder could be as a quantum dot design of a hybrid addder . The inputs for the MAC are to be fetched from me mory location and fed to the multiplier block of the MAC, which will perform multiplication and give the result to adder which will accumulate the result and then will store the result into a memory location. This entire process is to be achieved in a single clock cycle. In the majority of digital si gnal processing (DSP) applications the critical operations are the multiplication and accumulation. Real-time signal processing requires high speed and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which is always a key to achieve a high perfor mance digital signal processing system.

Fig. 8. Basic structure of MAC

CONCLUSION

Many previous designs have claimed to provide high performance,but it consumes more power and the area-delay product had increased.To overcome this problem an efficient design of a hybrid adder is proposed. The designs are based on new results concerning majority logic. The hybrid adder is shown to be particularly well suited to the QCA model.For best improvements,further more the efficient design of hybrid adder is implemented in MAC unit.The MAC unit consist of multiplier and adder.Hybrid adder will be implemented in the adder part of the MAC unit and compare the performance of the previous adder.

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