Design and Implementation of Reversible Combinational Circuits by Creating Libraries of Basic Gates using Verilog HDL

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Design and Implementation of Reversible Combinational Circuits by Creating Libraries of Basic Gates using Verilog HDL

M.Sirisha

Department of Electronics and Communication Engineering, KS Institute of Technology,

Bangalore, India

Krithika.P

Department of Electronics and Communication Engineering, KS Institute of Technology,

Bangalore, India

Abstract-This paper signifies the research work on design of reversible gates and various applications of it using Verilog HDL and VHDL with Xilinx ISE version 13.1, spartan 6 FPGA. Reversible gates have the facility to generate unique output vector from each input vector and vice-versa. Irreversible gates are the circuits which have an information loss. Losing information in a circuit causes losing power. So reversible gates have a better advantage when compared to irreversible gates. Using Verilog and VHDL we are creating a library of reversible gates such as AND, OR, CNOT, NAND, NOR, XOR. Using this library, we are implementing applications such as full adder, decoder (2:4),decoder (3:8),multiplexer, fullsubtractor, comparator.

Keywords- Reversible logic, Irreversible logic, Xilinx, Spartan 6 FPGA, Library of basic gates, Implementation of digital circuits.

  1. INTRODUCTION:

    Computers today terribly waste energy and storage capacity. They throw away millions of bitsevery second. These are based on irreversible logic devices, which have been recognized as being fundamentally energy inefficient for several decades.So reversible gates are the best remedies.Reversible gates are the circuits in which losses are minimized. In these circuits number of inputs will be equal to the number of outputs and there is one to one mapping between vectors of inputs and outputs. Fredkin gate, Toffoli gate, interaction gate, and switch gate are typical ones.

    Full adder- Adder is a digital circuit which adds n number of input bits with carry.Adder circuits are not only used in ALUs, but also used in various processors to calculate various increment or decrement operations, addresses, etc. Multiplexer-Multiplexer is a device which has many inputs and only one output. It selects one of several analog or digital input signals and forwards the selected inputs into a single line.

    Decoder-a binary decoder is a combinational logic circuit which converts binary information from n coded inputs to a

    Anitha.R

    Department of Electronics and Communication Engineering, KS Institute of Technology,

    Bangalore, India

    Aruna Rao.B.P

    Department Electronics and Communication Engineering, KS Institute of Technology,

    Bangalore, India

    maximum of 2^n unique output. The decoders are used in analog to digital conversion in analog decoders.

    Fullsubtractor- A full subtractor is a digital combinational circuit that performs subtraction n input bits, taking borrow into consideration. They are used for mathematical calculation, electronic calculators and in digital devices.

    Comparator-Comparator is an electronic combinational circuit that compares n input bits and it has 3 outputs namely lesser than, greater than and equal to. They are used in devices such as ADC, Oscillators, traffic lights, etc.

    Reversible computing may have applications in computer security and transaction processing, but the main long-term benefit will be felt very well in those areas which require high energy efficiency, speed and performance.

    • Needand for reversible gates over irreversible gates:

      In recent times researchers have investigated various reversible logic gate and their all- feasible implementations.

      Process improvements are eventually a dead end

      • Energy usage will become prohibitive

      • Heat dissipation will become more problematic

        Classical computer dissipates a lot of energy

      • Bulk electron processes

    Many electrons used to do a single logical operation

  2. PROCEDURE AND METHODOLOGY:

    We are implementing applications like full adder, and multiplexer using XILINX ISE version 13.1 and spartan 6 FPGA. Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs. This tool enables the developer to synthesise their designs, perform time analysis, examine RTL diagrams, design reactions to different stimuli, and configure the target device with the programmer. Spartan 6 FGPA is a hardware kit which is used for implementation of the developer designs. This kit is easy to use and implement any complex circuit using VHDL and Verilog HDL. FPGA –

    FIELDPROGRAMABLEGATEARRAY is an integrated circuit manufactured to be configured by the developer.

    Create a new folder in D-drive

    Create a new folder in D-drive

    Double click on ISE icon-go to file-new project-location D

    Double click on ISE icon-go to file-new project-location D

    1. STEPS:

      Project settings -family -spartan 6

      Device-XC6SLX4

      Package-TQG144

      Simulation-ISIM

      Preferred language-verilog

      Next-finish

      User constraints-I/O pin planning post synthesis -select the pins

      User constraints-I/O pin planning post synthesis -select the pins

      Click on project-new source-Verilog module-file name-type the code

      Click on project-new source-Verilog module-file name-type the code

      Simulation -ISIM-behavioural check syntax-simulate behavioural

      Simulation -ISIM-behavioural check syntax-simulate behavioural

      Waveform:

      Force constants-force a value -apply-OK

      Force constants-force a value -apply-OK

      Implementation

      Implementation

      Figure 2.waveform of Toffoli AND gate

      Implement design

      Implement design

    2. Toffoli OR: Gate in which output goes high when any one of the inputs is high and output goes low when both inputs are low.

      Generate programme file

      Generate programme file

      Device manager-ports-VFPGA6-check the port

      Device manager-ports-VFPGA6-check the port

      Double click on VSF6-enter the com port

      Double click on VSF6-enter the com port

      Block diagram:

      Check the output in the kit

      Check the output in the kit

      Give the file used -configure

      Give the file used -configure

      Truth table:

      Figure 3.block diagram of Toffoli OR gate

  3. RESULTS:

    1. Implementation of library

      1.Toffoli AND 2.Toffoli OR 3.CNOT

      4.Toffoli NAND 5.Toffoli NOR 6.Toffoli XOR

      1.Toffoli AND- In and gate output goes high when both input a and b are high or output goes low.

      Block diagram:

      Table 2.truth table of Toffoli OR gate

      Waveform :

      Truth table:

      Figure 1.block diagram of Toffoli AND gate

      Figure 4.waveform of Toffoli Or gate

      Table 1.truth table of Toffoli AND gate

  1. CNOT: Gate in which output is a compliment of input. It has only one input and output.

Block diagram:

Figure 5.block diagram of NOT gate

Truth table:

Table 3.truth table of CNOT gate

Waveform:

Figure 8.waveform of Toffoli NAND gate

5. Toffoli NOR: Compliment of OR gate. Block diagram:

Figure 6.waveform of CNOT gate

4.ToffoliNAND: Complement of and gate. Block diagram:

Figure 9.block diagram of Toffoli NOR gate

Truth table:

Table 5.truth table of Toffoli NOR gate

Truth table:

Figure 7.block diagram of NAND gate

Waveform:

Table 4.truth table of Toffoli NAND gate

Waveform:

Figure 10.waveform of Toffoli NOR gate

  1. Toffoli XOR: Gate in which output goes high when one of the inputs is set otherwise output goes low.

    Truth table:

    Waveform:

    Table 5.truth table of Toffoli XOR gate

    Waveform:

    Figure 14.block diagram of 3:8 decoder

    Figure 11.waveform of Toffoli XOR gate

    Implementation of applications such as:

    1. 2:4 decoder

    2. 3:8 decoder

    3. full adder

    4. multiplexer

    5. full subtractor

    6. comparator

1. 2:4 Decoder: this reversible decoder is designed using 2 R-I gates and a pair of not gates.

Block diagram:

Figure 12.block diagram of 2:4 decoder

Waveform:

Figure 13.waveform of 2:4 decoder

  1. 3 TO 8 DECODERS:

    The output of 2:4 decoder id given to 4 different R-I gates such that we get 3:8 decoder.

    Block diagram:

    Figure 15.waveform of 3:8 decoder

  2. FULL ADDER: It is a combinational circuit which adds n number input bits with carry. These circuits can be implemented using HDL and VHDL.

    Truth table:

    Table 6.truth table of full adder

    Waveform:

    Figure 16.waveform of full adder

    1. MULTIPLEXER:

      The 4 x 1 multiplexer is designed using 2:4 decoder, 2 and gate and or gate. Also, each output line of the decoder is given to 2 AND gate and followed by or gate. In this we designed 2:4 decoder is designed using fredkin gate.

      Waveform:

      6.COMPARATOR: It is a combinational circuit which compares given n input bits. It has three outputs such as lesser than, greater than, equal to. It isused in CPUs and microcontrollers.

      Block diagram:

      Figure 20.blockdiagram of comparator

      Figure 17.waveform of multiplexer

    2. FULL SUBTRACTOR: It is combinational circuit that performs subtraction of two bits with borrow.

Block diagram:

Figure 18.block diagram of full subtractor

Truth table:

Waveform:

Table 8.truth table of comparator

Truth table:

Table 7.truth table of full subtractor

WWavavefefoorrmm::

Figure 19 .waveformof full subtractor

Figure 21.waveform of comparator

  1. CASE STUDY: In recent times researchers have investigated various reversible logic gates and their all- feasible implementations.The advantages ofour method is that it is implemented at gate level and all logics used in it are simple and easy to design.The circuits are designed using minimal number of gates. The existing designs of comparator use more no of gates such as 8 to 9 TR gates in reference [9], where as we have implemented using 2-3(least)no of gates such as 1 TR gate, 1 Feynman and 1 BJN gate. As mentioned in reference [7], fullsubtractor and adder is designed using 9 gates and hence the design gets complicated for writing code and simulation. We have reduced and implemented using 3 gates in our own techniques.

    1. FUTURE SCOPE:

      This paper presents the usage of library created using reversible gates and implementing higher complex digital circuits. The paper can further be extended towards the digital design system development using reversible logic circuits which arehelpfulinquantum computing, low

      powerCMOS,cryptography,opticalcomputing,dnacomp uting,digitalsignalprocessing,communications,compute r graphics and Nano technology.

    2. CONCLUSION:

    In this paper, the library of reversible gates has been created such as and, or, cnot, nand, nor and xor. Using this library applications like full adder, decoder and multiplexer has been implemented. Using irreversible gates also these applications can be created but there will be a drawback of garbage outputs, high cost, energy and power losses and information loss also will be there. So reversible gates have more advantages and above-mentioned drawbacks can be minimized.

    The advantages are:

    • Information, like energy, is conserved under the laws of physics.

    • Thermodynamics can be used to tie the irreversibility of a system to the amount of heat it dissipates.

    • .Furthermore, there are evidences to suggest that reversible circuits may be built in an energy lossless way.

REFERENCES:

[1]. [C.H. Bennett, Logical reversibility of computation, IBM J. Research and Development, pp. 525-532, November 1973.

[2]. E. Fredkn, T. Toffoli, Conservative logic, Intl. Journal of Teoretical Physics, pp. 219-253, 1982.

[3]. T. Toffoli, Reversible computing, Tech Memo MIT/LCS/TM- 151, MIT Lab for Comp. Sci.,1980

[4]. VandanaShukla, O. P. Singh, G. R. Mishra, R. K. Tiwari, Novel design of optimized multiplexer circuit using reversible logicInternational conference on computer computing, Dhaka. pp 494-499,2002.

[5]. C.H. Bennett, Logical reversibility of computation, IBM J. Research and Development, pp. 525-532, November 1973.

[6]. R.Garipelly, P.M. Kiran, and A.S. Kumar, A review on reversible logic gates and their implementation, international journal of Emerging Technology and Advanced Engineering, vol. 3, pp417-423, 2013.

[7]. V.KamalaKannan,Shilpakala.V,Ravi.H. N International journal of advanced research in electrical, Electronics and Instrumentation Engineering volume.2,issue 8 august 2013.

[8]. G.VasanthRao, ImmadisettysivaParvathi, Novel design of low power comparator using reversible gates, volume 2, issue 11,november2015.

[9]. Sanjana Delay reducing design for 2 bit reversible comparator unit, volume 1 no.2 December2015.

[10]. SayyadKhajaMoinuddin, Syed Samiuddin, Reversible 2:4 decoder and its application International Journal and Magazine of Engineering, Technology, Management and Research ISSN NO:2348-4845, Volume no:2, issue no:10,October 2015.

[11]. Umesh Kumar and LavishaSahu and Uma sharma, Performance evaluation of reversible logic gates 978-1-5090-5515- 9/16,IEEE2016.

[12]. MojtabaValinataj, MahboobehMirshekar and Hamid Jazayeri, Novel low-cost and fault tolerant reversible logic adders Computers and Electrical Engineering 53,56-72,Elsevier2016.

[13]. Rakesh Kumar Jha, Arjun Singh Yadav An FPGA implementation of energy efficient code converters using reversible logic gates, volume 5,issue 1 January 2016.

[14]. DhoumendraMandal, SumanaMandal and Sisir Kumar Garai, Design of all optical binary one bit comparator using reversible logic gates 978-153861703-8/17, IEEE2017.

[15]. Hari Mohan Gaur, Ashutosh Kumar Singh, UmeshGhanekar, In depth comparative analysis of reversible gates for designing logic circuits,2018.

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