Characterization of Nanoscale MOSFETs using Analytical Technique

Download Full-Text PDF Cite this Publication

Text Only Version

Characterization of Nanoscale MOSFETs using Analytical Technique

Md. Sanawer Alam

PhD Scholar

IFTM University, Moradabad UP, India

Dr. Rabindra Kumar Singh Department of Electronics Engineering, KNIT, Sultanpur,

UP, INDIA

Abstract: A novel RF-MOSFET (Radio Frequency Metal Oxide Semiconductor Field Effect Transistor) model with PTM (Predictive technology model) for 90 nm CMOS ( Complementary Metal Oxide Semiconductor) technology is presented. A simple and accuracy method is developed to directly extract all the high frequency parasitic effect from measured S-parameter biased at zero and linear region. This model is proposed to overcome some of short channel effects at nano-scale highly dopped drain and source based on the conventional small signal MOSFET (Metal Oxide Semiconductor Field Effect Transistor) equivalent circuit, RF (RadioFrequency) characterization of CMOS (Complementary Metal Oxide Semiconductor) has been taken up. The excellent correspondence is achieved between simulated and measured S-parameter (Scattering parameter) from 1GHz to 10 GHz frequency range. Silvaco TCAD (Technology Computer Aided Design) tool is used to describe this model.

Keywords: Nanoscale complementary metal-oxide- semiconductor characterization, Parameter extraction using analytical method.

  1. INTRODUCTION

    A MOSFET device is considered to be short when the channel length is the same order of magnitude as the depletion-layer widths (xdD, xdS) of the source and drain

    For CMOS RFIC development, developing circuits at high frequency and low voltage becomes a challenge, especially

    since most of the MOSFET models are not designed for either low voltage or high frequencies. Undesired interaction with a low resistivity substrate adds to the task of designing RF circuit on CMOS processes [2],[3],[4],[5]. Device characterization and modeling at RF frequencies is necessary to allow accurate prediction of circuit performance prior to fabrication. The ultimate goal in modeling is a versatile model with few parameters ( less than 20 parameters) and good performance in all region of operation including high frequency operation.[5],[6],[7].

    In order to overcome the drawback of previously reported approaches, a novel model is presented to accurately predict the high frequency behavior of RF- MOSFET [4],[5]. A typical advanced MOSFET is shown in Fig.1. The complete new equivalent circuit small signal RF- model is shown in Fig.2.

    RF characterization of CMOS has been taken up based on their respective small signal model. By doing Y- or Z- parameter analysis of their respective model and analytical procedure for parameter extraction has been developed and presented here.[4],[5]

    junction. As the channel length L is reduced to increase both the operation speed and the number of components per chip, the so-called short-channel effects arise.[1]

    Fig:1 Cross-section of a typical advanced MOSFET [1]

    Fig. 2 Small signal RF Model [5]

    The small signal RF model of Fig.2 has been used for analysis and the Y & Z parameters have been found in terms of the circuit parameters. The parameters are Gate resistance (Rg), drain resistance (Rd), source resistance (Rs), gate-to-drain capacitance (Cgd), drain-to-base capacitance (Cdb), gate-to-source capacitance (Cgs), drain-to-source transconductance (gds), and the substrate parameters i.e. substrate resistance (Rsub), substrate capacitance (Cdb).[5],[6],[7],[8].

  2. SPECIFICATION OF 90 nm TECHNOLOGY NODE OF PTM MODEL OF CMOS:[9]

Table-1

Nano- CMOS: Technology node: 90 nm NMOS

Leff

Tox

Vdd

Vth

Rdsw

Ion

Ioff

35

nm

1.4

nm

1.2

V

0.2

V

180

µm

1100

(µA/µm)

50

(nA/µm)

Fig.3 Output characteristics of generated 90nm NMOS

  1. FABRICATION OF NANOSCALE MOSFET

    Here fabrication of nanoscale MOSFET is performed using ATLAS(SILVACO) TCAD tool. LDD ( Lightly Doped Drain) is used to overcome device degradation short channel effects.[6],[11],[12] And improved a lot but still have a chance of improvement. Heavily doped drain and source, lightly doped drain and source extensions and lightest doping of gate. The device structure of fabricated NMOSFET is shown in Fig.5.

    Fig.5 Device Structure of Fabricated MOSFET [10]

  2. ANALYSIS AND PARAMETER EXTRACTION

    )]

    (

    1

    The equivalent small signal RF model is shown in Fig. 2. Circuit analysis of the small signal RF model yielded the following results.

    III. RF MODEL DEVELOPMENT

    In the frequency ranges [Rg

    Cgs

    Cgd

    To have an efficient design environment, design tools with accurate models for devices and interconnect

    parasitics are essential. It has been known that for analog

    and [Lg

    (Cgs

    • C )]1 , a simplified

      gd

      ' '

      and RF applications the accuracy of circuit simulations can

      expression for small signal Y-parameters Y11 , Y 21 ,

      be strongly determined by the device models. Accurate ' '

      device models become crucial to correctly predict the circuit performance.[6]

      For a model to describe the device characteristics accurately, all important model parameters should be extracted from the actually Fabricated NMOS device [10].

      Y12 , and Y 22 of the circuit enclosed by dashed line in Fig. 2. can be derived as: [5],[6][7].

      1. Y-parameters

        The RF model development steps are shown using a flowchart shown in Fig.4

        ' 2

        Y

        R

        11 g

        (Cgs

    • Cgd

      )2 j(C

      • Cgd)

        (1)

        gs

        Y

        g

        '

        21 m

        • j Cgd

          .. (2)

          Y

          12

          gd

          ' j C

          )

          )

          (

          (

          (3)

          g

          ' j

          • j gm RsubCdb

    • jCdb(1 j RsubCsub)

    Fig. 4 Flowchart for Model Development [6]

    Y22 ds

    Cgd

    1 j R

    sub C

    sub

    Cdb

    1 j R

    sub C

    sub

    Cdb

    (4)

    1. Z-parameters

  3. EXTRACTION RESULTS TABLE-2

    Re[Z12 ]

    Rs B

    Cgd

    /( 2 A2 B2 )

    For Vgs = 0.3 V Vds = 0 V , Rs = 3 Rd = 5.95

    Bias point 1

    Vg = 0.3 V, Vd = 1.0 V

    Bias point 2

    Vg = 0.3 V, Vd = 1.5 V

    gm

    3.8 mS

    4.5 mS

    gds

    1.06 mS

    1.241 mS

    Rg

    1.606

    1.38

    Cgs

    319.07 fF

    308.5 fF

    Cgd

    117.01 fF

    112.96 fF

    Rsub

    22 m

    14.49 m

    Cdb

    90.0 fF

    88.12 fF

    gmb

    0.76 mS

    0.9 mS

    (5)

    Im[Z12 ] ACgd /( A B )

    2 2 2

    2 2 2

    (6)

    Re[Z22 ] Rs Rd (Cgs Cgd)B /(

    A B )

    (7)

    Im[Z ] B (

    )2 A(

    )2 /(2 A2 B2 )

    (8)

    22

    Where,

    Rg Cgs

    Cgd Cgs

    Cgd

    A Cgd Cgs Cdb (Cgs Cgd)

    B gds (Cgd Cgs) gm Cgd

    In order to determine the other parameters, they can be shown in terms of real and imaginary part of Y or Z as shown below.

    g

    1. Transconductance,

      21

      Re al(Y ' )

      m

      (9)

      (10)

      (11)

  4. S-PARAMETERS OF FABRICATED

    MOSFET

    S-parameters of this fabricated device at bias point Vg = 0.3 V and Vd = 1.5 V can also be produced as:

    1. Drain-to-source transconductance,

      22

      g

      Re al(Y '

      ds

      ) ; when 0

      (12)

    2. Gate resistance,

      Rg 11 11

      (13)

      Re al(Y ' ) / Im(Y ' )2

    3. Gate-to-drain capacitance,

      [Im(Y ' )] /

      Cgd 12

    4. Gate-to-source capacitance

      [Im(Y ' ) / ]

      (14)

      Cgs 11 Cgd

      (15)

      C

    5. Extraction of Substrate Parameters Rsub , db

    and gmb

    The extraction equations are given as follows:

    Re(Y22 ) g

    g

    g

    R ds

    (16)

    sub

    (Im(Y22

    ) Im(Y12

    ))2

    mb

    (Re(Y22

    )

    ds

    Re(Y22 ) g

    R

    C ds ,

    (17)

    db

    g

    sub

    (Im(Y22

    ) Im(Y12 )

    Fig.6 Generated S-parameters of Fabricated MOSFET

    g

    0.2

    mb m

    (18)

    Short channel effects are studied and hence lightly doped drain and lightly doped source regions are considered to overcome these effects. ATLAS (Silvaco) TCAD tool is used for fabrication of MOSFET of channel length 90nm, gate oxide thickness as 2nm and threshold voltage 0.26V. DC-IV characteristics and S-parameters are generated. Now MOSFET is fabricated and shows the desired characteristics and can be used for further analysis.

  5. MODEL TESTING

    The components in the RF model has been determined, hence the RF model is known. For model testing, S-parameters of the model are generated and compared with the Fabricated NMOS Device S-parameters. The comparison of Fabricated NMOS Device and modelled S-parameters will show that if the Fabricated NMOS Device and modelled plots are close then model is accurate within the permissible limit. The s-parameter is generated from the model using ADS ( Advanced Design

    Systems).

  6. COMPARISON OF GENERATED AND MODELLED S-PARAMETERS

    The comparison of the Modelled and Generated from Fabricated NMOS S-parameters is shown herewith. Fig.6 shows the comparison S-parameters at bias point 1 i.e. Vg = 0.3 V and Vd = 1.0 V.

    Fig. 7(a) Plot for S11 and S12 Vs Frequency at bias point 1

    Fig. 7 (b) Plot for S21 and S22 Vs Frequency at bias point 1

  7. SUMMARY

The MOSFET has been successfully fabricated using ATLAS(SILVACO) TCAD tool. The device is solved for dc-iv characteristics and S-parameters are obtained. To overcome some of the short channel effects at nano-scale lightly doped drain and source have been used.[6],[11] The coupling through the substrate is an important effect for mixed mode high-frequency IC design and should be appropriately accounted. At low frequency (<1GHz), it is good enough to model the substrate by a purely resistive network. However at high frequency (>1GHz), where most of the wireless communication systems operate, both resistive and dielectric losses are important and must be appropriately modeled by a combination of Rsub and Cdb. When this is done and appropriate account is taken of the back gate transconductance effect, a much more accurate RF model is developed, which can be used for evaluation output reflection coefficient in individual transistors as well as carrying out circuit design.

REFERENCES

  1. Fabio D Agostino, Deniele Quereia Project on short channel effect in MOSFET Introduction to VLSI Design (EECS 467), December 2000.

  2. Singh, N.S.S. ; Electr. & Electron. Eng. Dept., Univ. Teknol. PETRONAS, Tronoh, Malaysia ; Hamid, N.H. ; Asirvadam, V.S. Accurate modeling method to evaluate reliability of nanoscale circuits Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on Date of Conference: 3-5 Dec. 2012

  3. C. C. Wu, et al., A 90-nm CMOS device technology with high- speed, general-purpose, and low-leakage transistors for system on chip applications, IEDM Tech. Dig., pp. 6568, 2002.

  4. Rodriguez, A. ; Dept. of Electr. Eng., Univ. of Texas-Pan American, Edinburg, TX, USA ; Huq, H.F. Validation of nano-CMOS Predictive Technology Model tool on NanoHUB.org Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on Date of Conference: 15-18 Aug. 2011

  5. jun liu, xiao-jun xu, ling-ling sun Accurate Modeling and extraction methodology for RF MOSFET valid upto 40 GHz IEEE 2006, Microelectronics CAD centre, Hangzhuo Dianzi University, China.

  6. M.S. Alam and G.A. Armstrong, Extrinsic parameter extraction & RF modeling of CMOS, International Journal of Solid State Electronics, Elsevier Publication,Volume 48, Issue 5, 2004, pp. 669-674.

  7. Lan Wei et al, Parasitic Capacitance Analytical Model and Impact on circuit level performance IEEE Transaction on Electron Device, Vol. 58 No.5, May 2011.

  8. Yu cao, Takashi Sato Michael Ovshanky, Dennis Sylvester and Chenming Hu. New paradigm of predictive MOSFET and inter connect modeling for early circuit simulation Custom integrated circuit cnf pp 201-204. IEEE 2000 ICC.

  9. www.ptm.asu.edu

  10. Online documentation: http://www.silvaco.com/

  11. Markov, S.; Xingsheng Wang; Moezi, N.; Asenov, A. Drain Current Collapse in Nanoscaled Bulk MOSFETs Due to Random Dopant Compensation in the Source/Drain Extensions Electron Devices, IEEE Transactions on Volume: 58 , 2011

Leave a Reply

Your email address will not be published. Required fields are marked *