 Open Access
 Total Downloads : 617
 Authors : Yogesha K G, Dr. Rekha Bhandarkar
 Paper ID : IJERTV5IS050887
 Volume & Issue : Volume 05, Issue 05 (May 2016)
 DOI : http://dx.doi.org/10.17577/IJERTV5IS050887
 Published (First Online): 25052016
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
BinaryWeighted DAC using W2W Current Mirror Topology
Yogesha K G

Scholar, Dept. of ECE NMAM Institute of Technology
Nitte, Karnataka, India
Dr. Rekha Bhandarkar Professor, Dept. of ECE NMAM Institute of Technology Nitte, Karnataka, India
Abstract The paper presents an analysis and design of 3 bit, 4bit and 6bit BinaryWeighted CMOS Digital to Analog Converters (DACs). All the DACs are implemented using various CMOS technologies such as 180 nm, 90 nm and 45 nm with the supply of 1.8 V. The INLs, DNLs and Power dissipation of each DAC is compared and analyzed. As the transistor sizing is scaled down, the area occupied by DACs decreases; resulting in lower power dissipation. Even INLs and DNLs are decreased with transistor scaling. Thus, as the technology is scaled down, the design archives a good tradeoff between low INL, DNL and Power dissipation.
Keywords DAC, INL, DNL

INTRODUCTION
i
i
Progress of Very Large Scale Integration (VLSI) technology helps to implement many mixedsignal Integrated Circuits (ICs) in a single chip, including data conversion circuits [12]. DACs are at the beginning of the analog signal chain, which makes them very important to system
MOS transistor with size identical to M1 or M2 (drain current is Iref/2).
Figure 2. Combining a series and parallel MOSFETs [5].
The merit of the W2W topology significantly reduces the area of the layout for higher bit resolution due to lesser number of MOSFET devices used when compared to normal binary weighted DAC. Assume a MOSFET as a DAC, then an area of the device can be approximated as in equation (1) [5], where is the layout fill factor with < 1.
1
performance [67].
Ai
Wi Li

W2W Current Mirror Topology
The BinaryWeighted DAC is implemented using compact current mirror approach. Fig. 1 shows the binary weighted current mirror implementation using a W2W topology. It utilizes the fact that two identical MOSFETs in parallel (i.e., the effective channel width is twice that of the single MOSFET) and series (i.e., the effective channel width is half that of the single MOSFET) can be combined, as seen in Fig. 2, where device M1and M2 has the same amount of current.
Figure 1. BinaryWeighted current mirror using W2W topology [6].
The currents flowing in the remaining MOSFETs should sum to that of input the value or Iref/2. By observing details in Fig. 2, the remaining MOS transistors can be merged into a
The ratio of Nbit conventional DAC verses W2W binary weighted DAC is given by equation (2), where factor 2N/ is switch size and is always > 1.
N(2 N – 1) 2N/
r
(3N – 1) 2(N 1)/
Identical size (W/L) MOSFET is utilized in the circuit. It obtains a symmetrical layout reducing the mismatch due to alterations in the process. In W2W topology the devices M1, M2 and M3 operate with continual modifications, from the robust inversion region in the weak inversion region [7]. Fig. 3 shows that as the number of bits increases, then the layout, size ratio (conventional binaryweighted verses W2W DAC) also increases.
Figure 3. The ratio (r) of the approximated layout size for a traditional binary weighted and the W2W DAC verses the number of bits.

INL and DNL
The W2W DACs linearity equations are discussed in equation (3) and (4) [5]. In order to sum the errors as zero, the maximum positive and negative mismatch error is assumed at the current source corresponding to MSB (BN1) and the bits from B0 through BN2 respectively. For an Nbit DAC equation (4) gives the worst case INL. Where IK is the mismatch in current source and IKmax, INL is the condition to keep the INL lesser than 0.5 LSB. The transition of the input from 011111 to 1000..00 gives the largest DNL at the midscale.
Figure 4. A 4bit binary weight DAC using W2W current mirror topology.
The inputs B0 B3 are complemented using the inverter and given to the chip, as shown in Fig. 5.
NL
max
I
K , 2
I
K max, INL
I
ref 2 N
Figure 5. Inverter based scheme to provide differential input.

3bit DAC
The schematic diagram of 3bit DAC in 45 nm CMOS technology is shown in Fig. 6. B0B2 are the digital inputs,
DNL
IK 1
1
1
, I
I
ref
where idc (8 uA, input reference current source) and the differential output nodes Vout+ and Vout are all off chip. The
max
2 N
K max, DNL
2 N 1 2
load capacitance C0 and C1 are used at the output node to reduce the glitches. The Fig. 7 shows the simulation results of



THE BINARYWEIGHTED DAC
Fig. 1 shows that the addition of successive stages divides the input current by 2 consecutively, maintaining Iref/2 as the overall sum of currents, which flows through device M1 and M2. 3bit, 6bit and 12bit binaryweighted DACs are shown in Fig. 6, Fig. 8 and Fig. 10 respectively, where the current obtained from current mirror are digitally steered at the output node through the MOS transistor switches. The current drop in primary branch is equal to input current (Iref/2), which is equivalent to the current DACs Most Significant Bit (MSB), while the last two branches drops to Iref/2N.
The current sources can be matched better when the two pair of MOS switches is connected to the same inputs B0 and
B0 . It has to be noted that the input current is equal to Iref/2 as per the condition given in Section I, which is equal to MSB. Equation (3) gives the full scale or maximum output current. It is equal to 2Ã— Iref in (or Iref/2).
3bit DAC.
Figure 6. A 3bit BinaryWeighted DAC.
IFS(max) ref
Figure 7. Simulation Results of 3bit DAC.
Experimental results of 3bit DAC in 180 nm, 90nm and
45 nm are performed and parameter INLmax, DNLmax and power dissipation are tabulated in Table I.
TABLE I. 3BIT DAC PARAMETERS
CMOS
Technology
Parameters
INLmax
DNLmax
Power Dissipation
180 nm
1.86 LSB
0.65 LSB
30.24 uW
90 nm
1.43 LSB
0.607 LSB
27.28 uW
45 nm
0.99 LSB
0.556 LSB
19.79 uW

4bit DAC
Fig. 8 and Fig. 9 shows the schematic and simulation results of the 4bit DAC in 45 nm technology. Where B0B3 is digital inputs and idc (16 uA) is the reference current source. The linearity errors increase due to increasing resolution, even power dissipation also increases. Linearity errors and power dissipation of 4bit DAC in different CMOS technology has been performed and tabulated in Table II.
Figure 8. A 4bit BinaryWeighted DAC.
The parameters INLmax, DNLmax and power dissipation slightly increase compared to 3bit DAC.
Figure 9. Simulation Results of 4bit DAC.
TABLE II. 4BIT DAC PARAMETERS
CMOS
Technology
Parameters
INLmax
DNLmax
Power Dissipation
180 nm
2.0 LSB
1.216 LSB
54.72 uW
90nm
1.2 LSB
1.180 LSB
53.77 uW
45 nm
1.0 LSB
0.983 LSB
37.22 uW

6bit DAC
Fig. 10 shows the schematic of 6bit DAC in 45 nm CMOS technology and Fig. 11 shows simulation results. Where B0B5 are digital inputs and idc (64 uA) is the reference current source. Parameter INLmax, DNLmax and power dissipation are tabulated in Table III. The parameters INLmax, DNLmax and power dissipation slighty increase compared to 3 bit and 4bit DAC.
Figure 10. A 6bit BinaryWeighted DAC.
Technology
Parameters
INLmax
DNLmax
Power Dissipation
180 nm
4.658 LSB
3.10 LSB
223.8 uW
90 nm
4.541 LSB
3.071 LSB
215.2 uW
45 nm
4.203 LSB
2.932 LSB
40.76 uW
Technology
Parameters
INLmax
DNLmax
Power Dissipation
180 nm
4.658 LSB
3.10 LSB
223.8 uW
90 nm
4.541 LSB
3.071 LSB
215.2 uW
45 nm
4.203 LSB
2.932 LSB
40.76 uW
Figure 11. Simulation Results of 6bit DAC. TABLE III. 6BIT DAC PARAMETERS


RESULTS AND DISCUSSION
The parameter INLmax, DNLmax and power dissipation increase with increasing resolution and decreases as technology is scaled down from 180 nm, 90 nm to 45 nm. Each parameter is plotted with respect to different CMOS technology as shown in Fig. 12, Fig. 13 and Fig. 14 respectively.
Figure 12. Resolution versus INLmax for various CMOS technology.
Figure 13. Resolution versus DNLmax for various CMOS technology.
Figure 14. Power dissipation versus resolution for various CMOS technologies.

CONCLUSION

3bit, 4bit and 6bit W2W DAC topologies were discussed and test results presented using various CMOS technologies such as 180nm, 90 nm and 45 nm with the supply of 1.8V. The corresponding maximum DAC INLs and DNLs are discussed and power dissipation of each DAC is compared and analyzed. As the CMOS technology is scaled down, the area occupied by DACs decreases; resulting in lower power dissipation. Even INLs and DNLs are decreased with transistor scaling.
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