Application of BIST Technology – A Review

DOI : 10.17577/IJERTV3IS110108

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Application of BIST Technology – A Review

Kavyashree J

M.Tech, VLSI & embedded system Sahyadri College of engineering & management

Adyar, Mangalore.

Guruprasad A N

    1. ech, digital electronics and communication systems Adhichunchanagiri institute of technology Chickamagalur.

      Abstract – The consumption of low power has become important in communication systems such as laptops, cellular phones etc. At the same time, design of modern technologies and packaging is difficult, and BIST (built-in-self-test) emerged as a solution for the VLSI testing problem. So, the reduction of energy consumption is the most interesting and challenging topic in electronic industry. BIST is a design for testability aimed at the detection of faulty components in a system by incorporating test logic on-chip. BIST is also known for its various advantages such as improved testability, speed of modules and support in system maintenance. Also BIST circuits are used in the current redistributions. This paper includes the reviews of BIST circuits with different implementation techniques.

      Keywords – Built-in-self-test, current redistribution.


        The dissipation in power has become a major objective in design of many application areas, such as wireless communications and high performance computing, that leads to the production of numerous low power designs. At the same time, power dissipation is also becoming a critical parameter during manufacture test, as the more power is consumed by the design than during functional mode of operation. As the throughput of test and manufacturing yield are often affected by test power and also most dedicated test methodologies have emerged over the past decade.

        The present trends in the development of integrated circuitsand new advanced technologies enable integrationof complex digital and mixed-signal systems on a single chip.These complex systems, known as Systems-on-Chip (SOC), caninclude digital, analog, and RF circuits as well as MEMSstructures, micro sensors and another different core. No doubt,testability of the respective parts in such systems is greatlydecreased [1]. Standard test methods cannot be straightforwardlyused to test complex mixed- signal systems. Therefore,several automatic test equipments (ATE), each dedicated toa particular core integrated in the system, would be needed. After discussing test power issues, promising low power test techniques to deal with nanometre system-on-chip (SOC) designs are presented. These techniques can be broadly classified into those that apply during scan testing and those that apply during scan testing and those that apply during builtinselftest(BIST). Few of them are also applicable to test compression circuits or memory designs. In the literature, techniques that reduce power consumption during test application are generally referred to as power

        conscious testing, power aware testing, power constrained testing, or low power testing.

        In [3]and [4] transient response analysis based test techniques wereproposed by converting the OpAmp into a voltage follower.With respect to the fault-free circuit, performance parameterslike overshoot and slew rate deviation were monitored todetect the faults in the OpAmp. In [5], an AC and DCcompacted testing technique was presented by monitoring andanalysing fault signatures through amplitude and offset ofvoltage signals.


        As on today we come across many techniques implemented on BIST using ADC and DAC. B.Kamalasoundari M.E. proposed the Recursive Pseudo- Exhaustive Two-Pattern Generation Using BIST i.e., Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation. That can be given by following circuit diagram,

        Fig.1. Recursive pseudo-exhaustive two-pattern generator

        And also P. Pattunarajam*, G. NaveenBalaji proposed the Economical scan-BIST VLSI circuits based on reducing testing time by means of ADPi.e., Test power reduction done by Arbitrary Density Patterns (ADP) in which the effective usage of the WRP and TDP under adaptive control of clock is used. Weighted random patterns (WRP) and transition density patterns (TDP) can be effectively deployed to reduce test length with higher fault coverage in scan-BIST circuits. Analyse the effect of ADP on fault coverage. (Arbitrary density pattern = Weighted random pattern +Arbitrary density pattern).Adapt the scan frequency to the transition density for power constrained testing. This can be given by,

        Fig.2. Block diagram of TPG

        For scan testing it is important to note that both power and test time contribute to the test cost as well as quality of the test. The lower transition density based vectors though need more number of vectors but the difference between numbers of the vectors needed to detect faults is small. Thus a lower transition density can be chosen deterministically to reach that partial coverage while speeding up the scan clock without crossing the power budget. Once the transition density is known the test application time can be further reduced by dynamically controlling the test clock keeping the test power controlled. Again Jun Yuan and Masayoshi Tachibana proposed A Two-Step BIST Scheme for Operational Amplifier i.e.,this technique can particularly detect the capacitance variation in the compensation capacitor by combining the current-based test with the offset-based test to detect the physical defects in the OpAmp. This can be

        designed as follows,

        Fig.4. Defects in OpAmp

        This is composed of a stimulus generator, response analyser and isolation circuits of analog switches controlled by external controlling signals TM and TMC. The whole test procedure is controlled by these two controlling signals. TM is the test mode start signal; TMC was designed to connect test current to the injecting node to form a test step current.The proposed BIST scheme can also be applied to test other amplifiers on the same chip with different window comparators.The disadvantages of this BIST scheme is large area overhead, but this situation would be improved in the multi-amplifier complicated circuits.

        Fig.3. Implementation of one test per scan vector

        Further, Daniel Arbet, Viera Stopjakov´a, Juraj Brenkus, and G´abor Gyepes proposedOn-chip Parametric Test of R-2R Ladder Digital-to-Analog Converter and Its Efficiency i.e., this deals with the investigation of the fault

        detection in separated parts of a mixed-signal integrated circuit, example by implementing parametric test methods.For the operational amplifier, on-chip and off-chip approaches have been used to compare the efficiency. This can be implemented using the following design,

        Fig.5. Circuit diagram of R-2R ladder

        The R-2R ladder is a resistor network that uses a cascaded structure of current dividers, which generate binary-weighted currents in the respective branches.In ideal case, the dividing ratio should be 2:1 but because of resistors mismatch, in reality, the divisions will be imperfect.

        The most probable fault in the resistor ladder is that the value of a resistor exceeds its tolerance band (parametric fault).These faults can be detected by the measurement and evaluation of current value in therespective current branches.This circuit also ensures that the differential current (difference of IREF1 and IREF2) will flow out to the circuits output.This approach can test the resistor ladder in total eight steps, by shifting the logic 1 from MBS to LSB. Thisis implemented as follows,

        Fig.6. Circuit diagram of R-2R ladder with additional test behaviour (without control logic)

        The main problem of this method is that current in the last branch is in order of nA, which is difficult to sense and measure with necessary precision. Therefore, this test technique might be limited to ladders that use resistors with the resistance value smaller than 10k.Two different parametric test methods have been used for on-chip fault detection in the R-2R ladder digital-to-analog converter.

        So, an experimental circuit, consisting of the DAC, the additional test hardware, and the control logic for switching the DAC between functional and test modes, has been designed in selected CMOS technology.The on-chip total fault coverage might be increased by measuring the amplitude of oscillation.


        The automated test equipment (ATE) required for the conventional factory test of VLSI circuits usually includes highly specific test hardware and probing solutions.Most often this expensive equipment can only be used for one specific product and a reuse for higher level tests or during other test phases than factory test is not possible.As opposed to that, BIST-logic designed for a specific VLSI circuit can be extremely helpful for other test purposes like maintenance and diagnosis or start-up test.

        Table 1.Comparison of generic BIST techniques for


        Table 2.Advantages of BIST over conventional testing

      4. RESULTS


        Built-in Self-Test (BIST) scheme is better than other techniques, but for DFT applications Defect- oriented test methodology gives batter approach.


[1]. T. Jeng-Horng, M.-J. Hsiao and T.-Y. Chang, An embedded built-in-self-test approach for digital-to-analog converters, in Test Symposium,2001. Proceedings. 10th Asian, 2001, pp. 423


[2]. M. H., Test requirements for todays and future circuits: A perspective,in Proceedings of Electronic circuits and Systems, 2005, pp. 1 10.

[3]. K. Arabi and B. Kaminska, Oscillation-test strategy foranalog and mixed-signal integrated circuits, VLSI TestSymposium, Princeton, New Jersey, May 1999, pp. 476 482.

[4]. K. Arabi and B. Kaminska, Design for testability ofembedded integrated operational amplifiers, IEEE Journal of Solid-State Circuits, vol.33, pp. 573 – 581,April 1998.

[5]. Wimol San-Um and M. Tachibana, A Compact On- ChipTesting Scheme for Analog-Mixed Signal Systems UsingTwo-Step AC and DC Faults SignatureCharacterizations, SASIMI 2009, Okinawa. Japan, pp.428433, March 2009.

[6]. J. L. H. Diaz, Test and Design-for-Testability in Mixed-Signal IntegratedCircuits, 1st ed. Springer, October 2004, no.1402077246.

[7]. J. Wibbenmeyer and C.-I. Chen, Built-in self-test for low- voltage highspeedanalog-to-digital converters, Instrumentation and Measurement,IEEE Transactions on, vol. 56, no. 6, pp. 2748 2756, Dec. 2007.

[8]. H. Xing, H. Jiang, D. Chen, and R. Geiger, High-resolution ADClinearity testing using a fully digital compatible BIST strategy, Instrumentationand Measurement, IEEE Transactions on, vol. 58, no. 8, pp.2697 2705, Aug. 2009.B.Kamalasoundari M.E. – Recursive Pseudo-Exhaustive Two-Pattern Generation Using BIST.

[9]. P. Pattunarajam*, G. NaveenBalaji – Economical scan-BIST VLSI circuits based on reducing testing time by means of ADP.

[10]. Jun Yuan and Masayoshi Tachibana – A Two-Step BIST Scheme for Operational Amplifier.

[11]. Daniel Arbet, Viera Stopjakov´a, Juraj Brenkus, and G´abor Gyepes – On-chip Parametric Test of R-2R Ladder Digital-to- Analog Converter and Its Efficiency.

Method used


  • Built-in Self-Test (BIST) scheme for Operational Amplifier (OpAmp)

Fault coverage of 98%

  • The Circuit Under Test (CUT)

Fault coverage of 94.21%

  • Defect-oriented test methodology for mixed analog-digital circuits

Fault coverage 93%

Fault coverage to 99% for application of DFT

  • Built-in self-test (BIST) for external support for testing

Linearity errors are detected in different situations

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