# Adders : The Basic Arithmetic Building Block

DOI : 10.17577/IJERTV9IS080326

Text Only Version

#### Adders : The Basic Arithmetic Building Block

Jaimin Desai

Dept of Electronics Engineering

Shah and Anchor Kutchhi Engineering College Mumbai,Maharashtra, India

Nibha Desai

Dept of Electronics Engineering

Shah and Anchor Kutchhi Engineering College Mumbai,Maharashtra, India

Abstract This paper provides an overview of basic adders used for arithmetic calculations. Different types of adders are presented on the basis of Area they occupy in terms of No. of Gates are used. Adders are being used as the basic building block of arithmetic calculations. The detail literature survey has done for different types of the adders and also compared with each other to find out the suitable adder for a designated task.

Keywords Full Adder(FA), Pi and Gi signals, Calculation, AND gate, OR gate, Delay, Speed, Area, Cost

1. INTRODUCTION

rest of the adders & cost is less as it occupies a smaller area and uses only FAs.

It is the type of adder which was designed to overcome the disadvantages of RCA. The importance about carry lookahead adder is that here delay is much lesser than RCA, the values of sum and carry are calculated by the initial P0 and G0 signals, so there is no need to go through all the FAs. Here, Adder propagates and generates signal which are used to calculate the value of carry. The propagate signal is denoted by Pi and has the formula Pi = Ai + Bi. And generate signal being denoted by Gi with the formula Gi = Ai * Bi [2]. The formula for carry is Ci+1 = Gi + Pi*Ci. Here i is the bit for which we are calculating the carry. Higher speed than RCA, as CLA uses Propagate(Pi) and Generate(Gi) signals, also carry and sum is calculated by using only the first P0 and G0 signals which is the main advantage of this adder and we can derive Ci+2 and other carry outputs from those values. Its performance for calculation is at a faster pace but the area occupied is more than RCA, presence of CLA logic and regular RCA along with P and G signals as seen in Fig.2. Also, here the full adders are little bit modified then we normally see in the regular full adders. Cost is higher than RCA, as it has more wiring tracks and area is more than RCA.

This type of adder is used to overcome the demerits of RCA. Area occupied is more than CLA and twice of RCA, has twice the no.of FAs than RCA & CLA, with 2:1 MUX for selecting the carry. As the name suggest the carry generated is selected on the basis of the Cin provided at the start. Here we use two different carry-in values i.e 0 and 1 as shown in Fig.3 [3]. Traditionally we use one carry value which gets generated from the previous block of the FA, for the calculation of the full adder ahead of it, but here we have carry values of 0 and 1 instead of one carry value. As there are two carry-in values so we use two sets of full adders for calculating the sum and carry for each carry-in values. So, we pre-calculate the sum and the carry values for the particular block. Now on the basis of Cin the sum and carry values are carry forwarded by the Multiplexers, AND and OR gate. And hence we get the sum and carry values. When we consider speed as a factor then it is faster than RCA, carry & sum each have two output values for two possible input values of Cin ie 0 & 1. Depending on the initial value of Cin the value of carry & sum is taken at output. But the delay is more in CSA, although the values are calculated beforehand but the use of twice the no.of FAs along with MUX and AND gate increases the delay. Cost is higher than RCA & CLA, the no.of FAs is double the no.of FAs in RCA, usage of MUX & area occupied is more.

The main function of this type of adder is to skip the carry calculation process. Here adder uses carry lookahead adder for the calculation of Pi and Gi signals as seen in Fig.4. Area is less than CSA, we use FAs, AND logic gates for finding the Propagated signals and 2:1 MUX for selecting the output. All the inputs are processed simultaneously to generate the sum and Pi signals. The important function is performed by the Pi signals as they decide whether to skip the carry calculation or not. After the inputs, the sum and Pi values are generated and adder needs to AND all the Pi values. The output of the AND gate acts as a select line in 2:1 MUX. If the value of the AND gate is 1 i.e. all the Pi signals are 1 then we use Cin as the carry output and adder skips all the FAs to process the calculation to find carry. But if AND gate value is 0 i.e. any one of Pi signal is 0 then the carry is calculated same like in RCA, that is carry is calculated from LSB to MSB. This type of adder uses both RCA and CLA for calculation [4]. It is faster than RCA,CLA,CSA & CSVA adders, depending upon the Pi

signal output from AND logic block the carry is selected. If output of AND logic block is 1 then Cin(skipping the addition via FAs) is selected as carry and if 0 is the output then carry is generated via FAs. Whereas the delay depends on the value/s of Pi & AND logic block, if AND logic block gives output as 1 then calculation over FAs are skipped or else calculation happens via Fs. And when it comes to cost, costly than CSA, has FAs like RCA but only one AND logic block and 2:1 MUX.

Where, Logic levels: L + l(small L) Fanout: 2f+1(one)

Wiring track: 2t

Cost may increase or decrease depending upon few factors, factors like wiring tracks, operators, buffers and logic level decides the cost of the adder. Lesser the components lesser the price.

Fig.6 Processing Component

Fig.7 Buffer Component

8. COMPARISON TABLE

The Table.1 shows the comparison of different types of adders on the basis of few factors like Area, Speed, Delay and Cost which helps us to decide which adders to be used for a specific application. It gives better insights on adders.

Table.1 Comparison of Different Types of Adders

9. CONCLUSION

Adders are used for arithmetic calculations. Different types of adders like RCA, CSA, CLA, CSKA, CSVA and PPA are available. The performance of these adders can be measured in terms of parameters like Area, Speed, Delay and Cost. The detailed literature survey of adders has been done in this paper. And also, they are compared with each other to choose a specific one for a particular requirement. According to our survey we found that PPA is the better adder in performance compared to other adders. We can always have trade-off between few performance factors when we select specific adder as per the needs. The adder can also be implemented using any of CAD tools to observe and analyse different factors like power consumption, fan in, fan out, wiring tracks and logic levels.

REFERENCES

1. Suhel Ranjan Mondal, Monalisa Bhowmik, Santanu Maity, Razia Sultana , Comparative Analysis and Study on 4-bit RCA and CSK using CMOS Logic , International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-4 Issue-6, January 2015.

2. Rajesh, D & Sowmya, S & Subashini, M & Suryaprabha, P & Gowthaman, Naveen Balaji & Suman, Gautami. (2018). Investigations of Carry Look Ahead Adder at V DD =1.0V at 65nm CMOS Technology for High Speed and Low Power Applications.

International Journal of Latest Research in Science and Technology. 7.

3. B.Gopinatp , N.Sangeetha2 , S.Jenifer nancy3 and T.Umarani4 1Asst. Professor Dr. SJS Paul Memorial College of Engineering & Technology,Puducherry. 234Student Dr. SJS Paul Memorial College of Engineering & Technology,Pondicherry. Design and Implementation of High Speed Carry Select Adder. International Journal of Engineering Research & Technology (IJERT) ISSN: 2278- 0181 IJERTV4IS020383 www.ijert.org (This work is licensed under a Creative Commons Attribution 4.0 International License.) Vol. 4 Issue 02, February-2015.

4. P.Lakshmi Priyanka1 P.G. Student Dept. of ECE AITS Kadapa, India, A.Maheswar Reddy2 Dept. of ECE AITS Kadapa, India M.V.Subbaiap Dept. of ECE AITS Kadapa, India K.md.Haneef4 Dept. of ECE AITS Kadapa, India, S.Saleem5 Dept. of ECE AITS Kadapa, India.Carry Skip Adder Using Carry Save Adder Logic. SSRG International Journal of Electronics and Communication Engineering (SSRG_IJECE) Special Issue ICITSET Sep 2018.

5. Junhyung Um, & Taewhan Kim. (n.d.). Utilization of carry-save- adders in arithmetic optimization. Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454). doi:10.1109/asic.1999.806498.

6. Sung-Mo(Steve)Kang Korea Advanced Institute of Science and Technology University of California at Santa Cruz, Yusuf Leblebici Swiss Federal Institute of Technology-Lausanne, Chulwoo Kim Korea University-Seoul. CMOS Digital Integrated Circuits Analysis and Design. McGraw Hill Education (India) Private Limited

7. Er. Aradhana Raju, Richi Patnaik, Ritto Kurian Babu, Purabi Mahato Department of ECE, Silicon Institute of Technology, Bhubaneswar, Khurda (Dist), Odisha,. Parallel Prefix Adders- A Comparative Study For Fastest Response .