 Open Access
 Total Downloads : 375
 Authors : M. Yerri Veeresh, A. Mallikarjuna Prasad, U. Chaithanya
 Paper ID : IJERTV2IS90646
 Volume & Issue : Volume 02, Issue 09 (September 2013)
 Published (First Online): 23092013
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
A Strategy of High Voltage Gain Switched – Capacitor DCDC Converter with Reduced Component Rating and Count Fed DC Drive system
1 M. Yerri Veeresh, 2 A. Mallikarjuna Prasad, 3 U. Chaithanya
1Post Graduate Student, SJCET, Yerrakota, Yemmiganur. 2Associate Professor, SJCET, Yerrakota, Yemmiganur. 3Assistant Professor. SJCET, Yerrakota, Yemmiganur.
Abstract This paper presents a strategy of bidirectional switchedcapacitor dcdc converter with high voltage gain for industrial applications. In contrast to the conventional flying capacitor dcdc converter and multilevel modular capacitor clamped dcdc converter, the proposed converter is completely modular with low component power rating, small switching device count, low output capacitance requirement and simpler gate drive. Therefore, a small and light weight converter with high voltage gain and high efficiency can be achieved. This paper discusses the construction and operation of new converter along with the comparison of conventional converters. Finally, proposed converter is fed to dc motor to verify its performance characteristics. Simulation results are presented to validate the concept proposed.
Keywords Dcdc power conversion, switchedcapacitor, efficiency, modular, voltage gain.

INTRODUCTION
Nowadays, power converters plays a vital role in industrial applications and the new kind of converters was developing to achieve good performance with reduced loss and high efficiency. Switchedcapacitor dcdc converters have become popular due to their attractive features such as magneticless structure and high efficiency. Since they can be easily integrated without bulky magnetic components, the power density of dcdc converters can be significantly boosted.
The flying capacitor dcdc converter [1][4] has some potential features to be used in automotive applications such as hybrid electric vehicles to manage power transfer between different voltage level buses. A bidirectional 3X (i.e., the voltage gain, Vout/Vin is 3) dcdc converter is shown in Fig.1. However with proper PWM control, it can have three voltage ratios instead of fixed 3:1 ratio. But, for convenience the dcdc boost conversion for 3X is presented.
Fig.1. Flying capacitor dcdc converter with voltage conversion ratio of three.
In construction, flying capacitor (FC) dcdc converter requires 2N switching devices and N capacitors in incremental order of range for a voltage conversion ratio of N times (NX). From Fig.1. of 3X voltage ratio, the converter circuit requires 6 switching devices and 3 capacitors. A phase leg of complimentary switches Sjp and Sjn are connected to connect a capacitor across it for each conversion ratio. The voltage source or battery is connected at the midpoint of switching devices Sjp and Sjn.
The operation of FC when the desired ratio is 3X, the converter circulates from switching states I, II to III as shown in Figs.2. (a), (b) and (c) with 1/3 duty ratio per state. In State I, C1 is connected the battery/voltage source Vin then Vc1 = Vin. In state II, the charged capacitor C1 is in series with the battery Vin and connected to C2 then Vc2=Vc1+Vin. In State III, the charged capacitor C2 is in series with the battery Vin and connected to C3 then Vc3=Vc2+Vin. After these three states, the capacitor voltages will be balanced automatically. As a result, the output
Fig.2. Switching Patterns for 3X mode: (a) Switching State I, (b) Switching state II, (c) Switching State III.
voltage is three times the input voltage. The corresponding switching states are summarized in Table1.
Table 1: Sequential conduction of switches and capacitors of FC.
Switching States
Sequential Conducting Switches
Operations or Capacitor Charge
I
S1p
S2n
S3n
Vin
C1
II
S1n
S2p
S3n
Vin
+ C1
C2
III
S1n
S2n
S3p
Vin
+ C2
C3
The Pulses Should be generated as per above sequence. It is clear that, S1p as to conduct with 33% pulse width and start at 0 Sec phase delay. S2p as to conduct with 33% pulse width and start at 33% Sec phase delay. S3p as to conduct with 33% pulse width and start at 66% Sec phase delay. S1n as to conduct with 66% pulse width and start at 0 Sec phase delay. S2n as to conduct with 33% pulse width at 0 Sec phase delay and again at 66% Sec phase delay with 33% pulse width. S3n as to conduct with 66% pulse width and start at 66% Sec phase delay.
This topology is not suitable of high voltage gain since switching scheme is complicated and is not sufficient as the conversion ratio increase i.e., switching states are equal to conversion ratio N. Thus the operating frequency is limited to low when conversion ratio is high or its operation is difficulty at high frequency. The conducting switches in each subinterval are N thus lead to excessive voltage drop across the switches/diodes. Then the dynamic switching loss is also high.
In contrast to the conventional flying capacitor multilevel dcdc converter (FCMDC), Multilevel Modular capacitor clamped dcdc converter topology [5][8] is completely modular and requires a simpler gate drive
circuit. The MMCCC as shown in Fig.3.(a) is composed of three cells plus a switch S4a and a capacitor C4 connected to the output. In boost mode, it steps up the voltage from the low voltage input (defined as Vin) to the high voltage output (defined as Vout). A basic modular block is shown in Fig.3.(b).
In construction, the switch Sja (j = 1, 2, 3, 4) creates a path for charging the capacitor Cj in one of two alternate switching states. The capacitor C1 is charged by the input, Vin, and the other capacitor Cj (j = 2, 3) is charged via the addition of Cj1 and Vin. A phase leg of complementary switches Sjp and Sjn (j = 1, 2, 3) from each basic cell is in parallel with the input source Vin, in order that Cj can be directly connected to the positive (or negative) terminal of the input through just one switch Sjp (or Sjn). The switching states are reduced from four to two, since the current path becomes independent. The above review explains why the MMCCC has shorter current paths and lower current stress than the FC converter as shown in Fig.1. From another point of view, the MMCCC can be reverted to the similar form as the FC circuit and can be redrawn as in Fig.4.
In operation, interestingly, the MMCCC will perform the entire operation only in two subintervals. In the first subinterval, the capacitor C1 is charged by voltage source or battery Vin directly and at the same time the capacitor C3 is charged through the series combination of battery Vin and capacitor C2. Similarly in the second sub interval, the capacitor C2 is charged with the series combination of battery Vin and capacitor C1 and also the capacitor C4 is charged by series combination of battery Vin and capacitor C3 with the proper selection of switches to be switched in the circuit. The corresponding switching states are summarized in Table 2.
The Pulses generation is as per switching sequence given in table1. It is clear that, S1a, S1n and S2p, S3a, S3n has to be conduct with 50% pulse width with a

(b)
<>Fig.3. (a) Original MMCCC with a voltage conversion ratio of four. (b) Basic Model.
bidirectional power flow management. Even though it suffers from such as the MMCCC require extra N2 switching devices compared with FC dcdc converter. The MMCCC have 3N2 switching devices rather than 2N in conventional FC structure. Both MMCCC and FC require increased capacitor voltage with increment of the voltage conversion ratio. The different voltage rating requirement and maximum voltage rating of the capacitors pose challenges on component selection, size and efficiency when a high voltage gain is desired.


PROPOSED CONVERTER
The proposed switched capacitor dcdc converter [9] has overcome the limitations made in the both flying capacitor (FC) dcdc converter and multilevel modular capacitor clamped dcdc converter (MMCCC)
Fig.4. MMCCC in the similar form as the flyingcapacitor circuit.
Table 2: Sequential conduction of switches and capacitors of MMCCC.
Switching States
Sequential Conducting Switches
Operations or Capacitor Charges
I
S1a
S1n
Vin
C1
S2p
S3a
S3n
Vin
+ C2
C3
II
S1p
S2a
S2n
Vin
+ C1
C2
S3p
S4a
Vin
+ C3
C4
phase delay of 0 Sec. S1p, S2a, S2n and S3p, S4a has to be conduct for remaining 50% pulse width with a phase delay of 50% Sec.
The MMCCC topology has many advantageous features such as high frequency operation capability, low input/output current ripple, lower onstate voltage drop and
with low switching device and capacitor power rating, small switching device count same as the FC converter, and low output capacitance requirement with the same switching scheme followed for MMCCC, thus proposed converter is most suitable for high voltage gain.
Fig.5.(a) shows the proposed switchedcapacitor dcdc converter with a voltage conversion ratio of six (named 6X). It can also function as a buck when the energy flows in the opposite direction. It is composed of three cells. In boost mode, it steps up the voltage from the low voltage input (defined as Vin) to the high voltage output (defined as Vout). The new converter can also viewed in another way as shown in Fig.6. Inside each module, a phase leg of complimentary switches Sjp and Sjn (j=1,2,3) and a pair of capacitors Cja and Cjb are connected together at their respective mid points. Externally, another phase leg Sja and Sjb is in parallel with the input voltage. The capacitor Cja is connected through the switches Sja and Sjn during charging along with necessary combination switches. Similarly capacitor Cjb is connected through the switches Sjb and Sjp during charging respectively.
(a) (b)
Fig.5. (a) Proposed 6X switchedcapacitor dcdc converter. (b) Basic Model
switches S2p, S3a and S3n, as simplified in Fig.8.(b). In the lower path, the capacitor C1b is in series with the input to charge the capacitor C2b through the switches S1n, S2p and S2b, as simplified in Fig.8.(c). During this time C3b is discharged by the load current.
In the similar way the switching state II as shown in Fig.7.(b), the complementary switches are gated on so that the capacitors C2a, C1b, C3b that are discharged in the first switching state become charged in the second switching state, while the capacitors C1a, C3a, C2b become discharged. In the lower path, the capacitor C1b is charged to Vin by the input through devices S1b and S1b, as simplified into an equivalent circuit in Fig.8.(d). The capacitor C2b is in series with the input to charge the
Fig.6. Another view of Proposed 6X switchedcapacitor dcdc converter.
Fig.5.(b) shows the basic model of proposed converter. Each modular block has two equal voltage rating capacitors and three switching devices for a conversion ratio of two. The terminal P+Vin and PVin are connected to the positive and negative polarities of the voltage source or battery respectively. The terminals PC(j 1)a+ and PC(j1)b are connected to the positive and negative terminal of previous capacitors output voltage respectively. The PCja+ and PCjb are the present capacitors output voltage connected to next module switching device terminals.
This converter alternates between two switching states with 50% duty ratio for each state. The switching devices marked in solid line are onstate devices and current paths, the remaining devices in dashed lines are off state devices. The corresponding equivalent circuits are shown in Fig.8.
In the switching state I as shown in Fig.7.(a), in the upper path, the capacitor C1a is charged to Vin by the input through devices S1a and S1n, as simplified into an equivalent circuit in Fig.8.(a). The capacitor C2a is in series with the input to charge the capacitor C3a through the
capacitor C3b through the switches S2n, S3b and S3p, as simplified in Fig.8.(e). In the upper path, the capacitor C1a is in series with the input to charge the capacitor C2a through the switches S1p, S2n and S2a, as simplified in Fig.8.(f). During this time C3a is discharged by the load current. The corresponding switching states are summarized in Table 3.
Table 3: Sequential conduction of switches and capacitors of proposed converter.
Switching States
Sequential Conducting Switches
Operations or Capacitor Charges
I
S1a
S1n
Vin
C1a
S2p
S3a
S3n
Vin
+ C2a
C3a
S2p
S2b
S1n
Vin
+ C1b
C2b
II
S1p
S1b
Vin
C1b
S3p
S3b
S2n
Vin
+ C2b
C3b
S1p
S2a
S2n
Vin
+ C1a
C2a
Fig.7. (a) Switching state I. (b) Switching State II.
The Pulses Should be generated as per above sequence given in table 3. From the above, it is clear that, S1a, S1n, S2p, S3a, S3n and S2b has to be conduct with 50% pulse width with a phase delay of 0 Sec. S1p, S1b, S3p, S3b, S2n and S2a has to be conduct for remaining 50% pulse width with a phase delay of 50% Sec.
Fig.8. Equivalent circuits for two switching states. (a) Charging C1a. (b) Charging C3a. (c) Charging C2b. (d) Charging C1b. (e) Charging C3b. (f) Charging C2a.
Combining the voltage relations in the two switching states and neglecting the voltage drop, one can get the following voltage relations:
Vcja = Vcjb = j * Vin, j = 1, 2, 3. (1)
The proposed converter is beneficial such as the switching devices required is only 2N for conversion ratio of N, thus it has low component switching devices. The capacitors required is N as that of FC and MMCCC but the capacitor voltage required is lesser since the two similar capacitor ratings equal to input voltage are enough for output voltage to be double instead of one capacitor with the input voltage rating and the other is double the input rating as in FC and MMCCC. The power loss is very less due to low component switching devices, low capacitor power ratings in addition with two symmetric short charge pumps. The voltage (or current) stress is low since device cunt is less and thus low TDPR. The bidirectional operation is possible along with simpler switching scheme. Thus it is modular structure make it use for high voltage gain applications at lower cost.

COMPARISON
In the comparison, Table 4, the most suitable converter is denoted by the bold letters in all comparative aspects. From the table 4, it is clear that the number of switching devices required is less as 2N in both flying capacitor and proposed converter. The number of switching states and number of switches to be conduct to charge a capacitor is maximum of 3 only in both multilevel modular capacitor clamped converter and new converter. The number of capacitors required is N which is same in all the three converters but the highest capacitance required is less as (N/2)*Vin and total capacitance required is also less as (((1+N/2)N)/2)*Vin in only proposed converter. Thus in all aspects mentioned above the proposed converter is efficient, least cost, less losses converter for high voltage gain applications.
Table 4: Comparison of FC, MMCCC and Proposed Converters.
Converter
No. of Switching Devices
No. of Switching States
No. of Switches to be conduct to charge a capacitor
No. of Capacitors Required and Highest Capacitance range (Vin=12V)
Total Capacitance Voltage Rating
Flying
(1+N)N * Vin
Capacitor
2N (12)
N (6)
N (6)
N and N*Vin
2
(For N=6)
(6 and 72V)
( = 252V)
MMCCC
(1+N)N * Vin
(For N=6)
3N2 (16)
2 (2)
At Most 3
N and N*Vin
2
(At Most 3)
(6 and 72V)
( = 252V)
Proposed
(1+N/2)N*Vin
Converter
2N (12)
2 (2)
At Most 3
N and (N/2)*Vin
2
(For N=6)
(At Most 3)
(6 and 36V)
( = 144V)
Now, the proposed converter is employed to feed the dc motor to study its performance characteristics. The motor chosen was the separately excited dc motor with the desired parameters as: Rating of 5 hp, Voltage of 240V, Current of 16.2 A and speed of 1220rpm. To drive this motor the 6X proposed converter is having a input voltage Vin of 40V is used then the output voltage Vout will be a constant of 240V. The separately excited dc motor is one of the most important drives in industrial application. The study of dc motor characteristics is illustrated in the simulation results.

COST CONSIDERATIONS
The cost considerations of the proposed converter are compared with its conventional converters in the aspects as the TDPR, the capacitor voltage stress, current rating, and capacitance requirement. TDPR is an indication of how much total silicon area is needed for the semiconductor devices. Here, it is based on the product of the maximum voltage imposed on the device and the average current flowing through it over the duration when the device conducts. Note that neither the peak current nor RMS current is used.

If the 3X FC dcdc converters are extended to an NX structure, all the 2N devices would have to sustain the voltage equal to the input voltage and the input current. Its TDPR is the same as the traditional boost converter
TDPRFC = 2N*(Vin*Iin) = 2N Pin where Vin is the input voltage and Iin is the input current.

The MMCCC have switching states reduce to two. The charge current into one capacitor is the discharge current from its preceding capacitor, except that the
output capacitor has half the charge and discharge currents. Also, considering that the average charge current of one capacitor in half switching period equals its average discharge current in the other half switching period, the average current through each switching device is 2Iout in one of the two switching states. There is (N2) switches sustain twice the input voltage, as stated earlier. Thus, the TDPR is
TDPRMMCCC = 2N*Vin * 2Iout + (N2) * 2Vin * 2Iout
= ((8N 8) / N) Pin, N= 2, 3, 4.

For the new converter, the (N2) switches in the complementary phase leg convey the sum of the current in two charge pump paths, 4Iout, which is twice the current through the rest switches. It is not hard to find the voltage stress of each switch. Hence, the TDPR can be derived as:
TDPRNEW = (N2)Vin*4Iout+(2+2)Vin*2Iout
+ (N2) * 2Vin * (2Iout)
= ((8N 8) / N) Pin, N= 2, 4, 6.
Fig.9. Normalized total device power rating versus voltage boost gain.
Fig.10. Simulation model file of 6X proposed converter fed dc separately excited motor.
The above equations clearly demonstrate that unlike the conventional FC structure, the new converter has no penalty of TDPR even with fewer devices than the MMCCC. The ratio of the TDPR and the input power is plotted with respect to voltage gain in Fig.9. It is quite interesting that this ratio for the new converter will get saturated as N approaches infinite. This property implies that the proposed converter requires less silicon area than the FC dcdc converter does. the voltage ratings for the FC and the MMCCC are the same, the voltage rating for the new
converter is reduced nearly by half as illustrated in table 4.
1
S3n S2n S1n S1p S2p S3p
S3n S2n S1n S1p S2p S3p
0.5
00 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 104
x 104
1
0.5
00 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 104
x 104
1
0.5
00 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 104
x 104
1
0.5
00 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 104
x 104
1
0.5
00 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
x 10
x 10
1 4
0.5
00 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1


SIMULATION RESULTS
The proposed switched capacitor dcdc converter along with the conventional flying capacitor dc dc converter and multilevel modular capacitor clamped dc dc converters have been designed with the common switching frequency of 10 KHz and input voltage of 12V.
Time
Fig.11.Simulated results of gate pulses of 3X FC Converter.
Vc1
Vc1
20
15
10
x 104
The capacitance of capacitor at the corresponding input voltage Vin is chosen in the order of 500uF, 240uF, 120uF and 60uF as C1, C2, C3 and C4 respectively for all three converter designs. The simulation results are shown for three different converters to justify to content.
Fig.10. shows the simulation model file of 6X proposed converter fed dc separately excited motor. The proposed converter fed dc separately excited motor is chosen as the separately excited dc motor with the desired parameters as: Rating of 5 hp, Voltage of 240V, Current of
16.2 A and speed of 1220rpm (= 127.758 rad/sec).
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Vc2
Vc2
30
25
20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Vc3
Vc3
40
35
30
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time
Fig.12.Simulated results of capacitor voltages of 3X FC converter.
1
(V)
(V)
0.5
0
S1a, S3a, S2p, S1n, S3n
20
Vc1b
Vc1b
15
10
Vc2b
Vc2b
30
25
25
0 1 2
S1p, S3p, S2n, S2a,
1
(V)
(V)
0.5
0
S4a
x 104
20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
40
Vc3b
Vc3b
35
30
0 1 2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time
Fig.13. Simulated results of gate pulses of 4X MMCCC.
Vc1
Vc1
20
15
10
x 104
Time
Fig.17.Simulated results of lower leg capacitor voltages of proposed converter.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Vc2
Vc2
30
25
20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
40
Vc3
Vc3
35
30
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
50
Vc4
Vc4
45
40
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time
Fig.14.Simulated results of capacitor voltages of 4X MMCCC.
80
78
Vout
Vout
76
74
72
70
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time
Fig.18.Simulated result of combined capacitor voltages of output capacitors of proposed converter.
1
(V)
(V)
0.5
S1a, S3a, S2p, S2b, S1n, S3n
400
Armature Voltage(V)
Armature Voltage(V)
300
0
0 1 2
200
1
(V)
(V)
0.5
S1p, S3p, S2n, S2a, S1b, S3b
x 104
100
0
0 1 2
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time
Time
x 104
Fig.15.Simulated results of gate pulses of 6X proposed converter.
20
Vc1a
Vc1a
15
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
30
Vc2a
Vc2a
25
20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Vc3a
Vc3a
40
35
30
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time
Fig.16.Simulated results of upper leg capacitor voltages of proposed converter.
Fig.19.Simulated result of armature input voltage of proposed converter fed dc motor.
140
120
Speed(rad/sec)
Speed(rad/sec)
100
80
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10
Time
Fig.20.Simulated result of speed characteristics of the proposed converter fed dc motor.
350
Armature Current(A)
Armature Current(A)
300
250
200
150
100
50
0
0 1 2 3 4 5 6 7 8 9 10
Time
Fig.21.Simulated result of armature current characteristics of the proposed converter fed dc motor.
600
500
Torque(Nm)
Torque(Nm)
400
300
200
100
0
VII. REFERENCES

M. Xu, J. Sun, and F. C. Lee, Voltage divider and its application in the twostage power architecture, in Proc. 21st Annu. IEEE APEC, 2006, p. 7.

F. Zhang, L. Du, F. Z. Peng, and Z. Qian, A new design method for highpower highefficiency switchedcapacitor DCDC converters, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 832840, Mar. 2008.

W. Qian, F. Z. Peng, M. Shen, and L. M. Tolbert, 3X DCDC multiplier/divider for HEV systems, in Proc. IEEE Appl. Power Electron. Conf. Expo., 2009, pp. 11091114.

W. Qian, H. Cha, F. Z. Peng, and L. Tolbert, A 55 kW variable 3X DCDC converter for plugin hybrid electric vehicles, IEEE Trans. Power Electron., vol. 27, no. 4, pp. 16681678, Apr. 2011.

F. H. Khan and L. M. Tolbert, A multilevel modular capacitorclamped DCDC converter, IEEE Trans. Ind. Appl., vol. 43, no. 6, pp. 16281638, Nov./Dec.
0 1 2 3 4
5
Time
6 7 8 9 10
2007.
Fig.22.Simulated result of torque characteristics of the proposed converter fed dc motor.
Fig.23.Simulated result of speed vs armature current characteristics of the proposed converter fed dc motor.
VI. CONCLUSION
The proposed strategy of high voltage gain switchedcapacitor dcdc converter is compared with conventional switchedcapacitor dcdc converter as counterpart along with the validate simulation results of each converter. Thus the proposed converter is completely modular with less power loss due to the two symmetric short paths of charge pumps, less component power rating, small switching device count, low TDPR, reduces total capacitor voltage ratings, lowers capacitance and ripple current requirement of the output capacitors, simpler gate drive and high frequency operation. Finally, a small and light weight, high voltage gain, high efficiency and low cost proposed switched capacitor dcdc converter is most suitable for industrial applications.

D. Cao and F. Z. Peng, Zerocurrentswitching multilevel modular switchedcapacitor DCDC converter, IEEE Trans. Ind. Appl., vol. 46, no. 6, pp. 25362544, Nov./Dec. 2010.

W. Qian , D. Cao, J. G. CintrÃ³nRivera, M. Gebben,
D. Wey, and F. Z. Peng, A SwitchedCapacitor DC DC Converter With High Voltage Gain and Reduced Component Rating and Count, IEEE Trans. Ind. Appl., vol. 48, no. 4, July/August 2012.
M. Yerri Veeresh received the B.Tech. in Electrical and Electronics Engineering from JNTU Anantapur, in 2009. Currently, he is pursuing M.Tech. in Power Electronics and Electrical Drives from the same university.
His research interests are Power converters, Renewable Energy Systems, FACTS Applications and drive controllers.
A.MALLIKARJUNA PRASAD has
obtained his B.E from MADRAS University in the year 2001. He has obtained his M.E from Sathyabama University in the year 2004. He has 9 years of teaching experience. Presently he is a research scholar in JNTU, KAKINADA. He is working in the area of high power density dcdc converters.
U.CHAITHANYA has obtained his B.Tech from JNTU Ananthapur in the year 2008. She has obtained his M.Tech from JNTU Ananthapur in the year 2010. He has 3 years of teaching experience. She is working in the area of high power electronics applications.