 Open Access
 Total Downloads : 412
 Authors : Chinchu V, Mrs. Madhuri Sahal
 Paper ID : IJERTV3IS071263
 Volume & Issue : Volume 03, Issue 07 (July 2014)
 Published (First Online): 29072014
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
A Comparative Study of Costas Loop and DPLL for Carrier Synchronization
Chinchu V
Dept. of Electronics and Communication Engineering Manipal University Jaipur,
Jaipur, India.
Mrs. Madhuri Sahal
Assistant Proffesor,
Dept. of Electronics and Communication Engineering Manipal University Jaipur,
Jaipur, India
AbstractThis paper presents comparison of a simple costas loop and DPLL for carrier recovery. Synchronization is basically the process of frequency and phase aligning of remote oscillators. The first task is carrier acquisition which includes forming a frequency and phasematched replica of the local oscillator for the process of down conversion. A local oscillator in detector is forced to oscillate in both phase and frequency with respect to the carrier oscillator at the transmitter. Timing recovery is the second task focused on collecting a set of aligned input samples time and the replica template.
The presence of carrier phase error causes signal to rotate. For larger rotation, the symbol signal space projections lie in a wrong decision region. Hence there occurs a decision error even if a perfect timing recovery scheme is applied for zero additive noise. Carrier synchronization aims to detect the phase of carrier. Simulation results are presented for evaluating the behavior of costas loop and DPLL.
KeywordSynchronization, Carrier recovery, Costas loop, DPLL, Frequency estimator, Phase Estimator
I.INTRODUCTION
Generally transmitted signal is modified by the channel. Here the channel is assumed to be an additive white Gaussian noise (AWGN) channel. A delay also occurs at the receiver due to the time required for propagation of signal. It leads to sampling at instances in suboptimal time. Along with the relative movement between the transmitter and receiver causes a Doppler shift, imperfections in their local oscillators also tend signal to rotate in the signal space by a constant frequency offset [5].
The received signal is hence a modified version of transmitted signal due to these effects. The role of synchronizer is to estimate the fequency offset and delay occurred at channel, along with the phase offset and then to remove or reduce these modifications. Sent data symbols are then detection by the synchronizer [7].

THE COSTAS LOOP
In todays fast paced world, increase in the communication systems demand for high data rate tends operating frequency to millimeter wave region. Hence with modulation schemes like ASK and PSK, high data rate at larger bandwidth is applicable.
Communication system has a hierarchy of synchronization problem when dealing with these high data rates and high frequencies is the problem of carrier recovery. Synchronizer detection includes recovery of carrier offset present in RF signal with respect to a reference phase and frequency.
Baseband signal requires high speed A/Dconverters which in turn increases power consumption as well as design complexity [7]. For frequency exceeding several GHz, delay line will be in tens of millimeters. The length of delay elements determines the data rate [8]. For BPSK signal circuit is required which works with twice the carrier frequency since a frequency multipler is used. Hence for millimeter range of frequency costas loop is used [6].
A. Operation
J. Costas proposed the Costas loop as a phase tracker for AM signals [9, 5] which was later modied to demodulate PSK signals [2], [6].The operation of the Costas loop is shown in Fig. 3.
BPSK modulated RF signal X is given by:
X = I(t)sin (t + ) + Q(t)cos(t + ) (1) Where I(t) and Q(t) are symols having value of Â±1,
which varies at symbol rate. This signal is then passed
through a multiplier which multiplies signal with LO of same frequency and an instantaneous phase of and a LO with 90 phase shift. After passing through loop filter the signals are:
ZI(t) = I(t)cos Q(t)sin (2)
ZQ(t) = I(t)sin + Q(t)cos (3)
With = . The Output of the limiters for phase error of  < 45Â° is:
LI(t) = I(t) (4)
LQ(t) = Q(t) (5)
Fig .3. Schematic of discrete time equivalent of costas loop
The error signal is given by:
E(t) = ZQLI ZILQ
= I2(t)sin + Q(t)I(t)cos I(t)Q(t)cos + Q2(t)sin
= 2 sin
2 (for very small ) (6)
Hence, a phase error signal is obtained, along with VCO adjustment for maintaining the phase and frequency lock.

DPLL
The role of PLL is to synchronize the received signal frequency and phase using a feedback control circuit. Using negative feedback it locks the frequency and phase of the signal. DPLL is a modified PLL which contains a frequency estimator for estimation of large frequency offset followed by a phase estimator for phase estimation. This scheme overcomes the drawbacks of costas loop and PLL such as narrow frequency tracking, high frequency ripple and overshoot. The DPLL frequency estimator has the ability for high accuracy estimation of frequencies with large range that is from zero to half the sampling frequency. The output of frequency estimator is then used to control a phase estimator, a low noise PLL. Fig. 4 shows the complete structure of this mechanism. The output of this structure is the estimated phase and the estimated frequency.

Frequency Estimator
Fig. 5 shows the block diagram of the DPLL frequency estimator. It resembles a PLL structure except that the phase detector in PLL is changed to frequency detector, LPF to an accumulator and VCO to a quadrature numerically controlled oscillator (NCO) [1]. The frequency detector component consists of multipliers, adders, subtractors, differentiator and squaring circuit. Discrete time implementation of frequency estimator is
explained in Fig. 5. Mathematical expressions for frequency estimator, stability and power estimator is provided here [4].
Fig 4. Operation of DPLL architecture.

Frequency estimation
The input signal and the signal generated by the oscillator are:
XI(t) = cos(2fct+i) (7)
XQ(t) = sin(2fct +i) (8)
I(t) = cos(2fot +o) (9)
Q(t) = sin(2fot +o) (10)
Where fc, fo, i and o are input and output frequencies and phases respectively, t is the sampling time.
M ultiplication of both the input signal with both the signals generated by oscillator result in two quadrature signals (RxI (t), RxQ (t)) given as:
RxI(t) = XI (t )I (t ) + XQ (t)Q (t)
= cos(2ft + ), (11) RxQ (t) = XI (t)Q(t) XQ (t)I(t)
= sin(2ft + ) (12)
Fig. 5. Discrete time model of Frequency estimator.
Where f = fc fo, = i o. The quadrature signals (RxI (n), RxQ (n)) is then passed through differentiator circuit.
Where, fc is the center frequency. Accumulator saturates as soon as the NCO generated frequency and input frequency becomes equal.
=
 ( 1 Ã— 1
= 2 sin 2 + +
Hence at i (nt) = 0 (nt);
= = 2 = ct (20)
cos 2 + (13)

Phase Estimator
A low noise DPLL phase detector is used here [3]. A

=
( 1 Ã— 1
simple PLL cannot remove completely high frequency ripples that are present in signal.
The aim of DPLL structure is to use a first order
= 2 cos 2 + sin 2 (14)
The differentiator output is
LPF which provides system stability along with the ability to remove he ripples.
() = { ( + ) ( + )} Ã—
(i + ) (21)
= Ã— =
= 2 2 2 +
+
2 2 +
Where i and are radian frequency and p h a s e of signal generated from NCO respectively, kd is the
= 2f = (15)
The signals (rI (n), rQ (n)) a l s o at the same time passes through squaring circuit. The output of squaring circuit can be considered as power of input signal.
= 2 + 2
multiplier gain. First stage estimates the frequency. So at i
= i ,
= sin 2 + + +
+
(2 2 2) (22)
From (22) from the high frequency is subtracted by a new term before passing to LPF. Hence, the LPF in this
2 2 +
=
+ 2 2 +
mechanism have to remove only the residual of subtraction in turn of removing entire high frequency term as in a simple PLL. Hence, the first order LPF removes the
= 1 (16)
The output of divider is
= () = (17)
( )
The scaling of frequency difference is done until the
residual and enhances the stability of DPLL. The resulting signal from LPF is:
2
= ( ) (23) At (i ) << 1, then
frequency generated b y oscillator and input frequency
= (
) (24)
becomes same.
2
The scaled output is
( ) = ( ) ( 1 ). (18)
Where, Âµ is a variable which controls stability of the system. I t s r a nge i s 0 Âµ < 1. For small values of Âµ, the system is more stable but takes long settle time, for greater values of Âµ settling time decreases.
Output of accumulator controls NCO output. Feedback loop in estimator continues until input frequency and frequency generated by NCO becomes equal.
The NCO equation is
This signal controls the phase of NCO generated signal, and the DPLL continues the variation of the phase until locking occurs and i = .


RESULT ANALYSIS
Simulations are carried out for comparing the working of costas loop and DPLL for receiver synchronization.
The performance of costas loop carrier synchronization mechanism for a simple BPSK signal is illustrated. The input signal is set at a carrier frequency fc of 500 KHz and sampling frequency fs = 1/t as 20MHz. BPSK signal with 100 samples are generated.
=0
= + 1 ()
(19)
Close view of the synchronized received signal is shown in fig. 6. The constellation diagram of received signal is shown in fig. 7.
The comparison of receiver synchronized signal with a generated signal along with some offset is given in Fig. 8. In Fig. 8, signal plotted in blue is input signal and the signal plotted in red shows the synchronized received signal
Fig. 6. Carrier synchronised received signal, blue shows reiceved signal and red shows error signal
Fig. 7. Constellation diagram of synchronized BPSK received signal
Fig. 8. Input and output plot
The costas loop is having disadvantages of long settling time and instability. The DPLL mechanism for frequency and phase estimation used here can overcome these problems. This scheme also overcomes the problem for recovering the signal with higher offsets.
To illustrate the mechanism of DPLL frequency and phase estimations are done. An input signal with a carrier frequency fc of 6KHz and sampling frequency fs of 20 kHz is used with different carrier offset. Fig. 9(a) shows the plot of frequency tracking using the DPLL frequency estimator. The phase estimator for phase tracking is given in Fig. 9(b).
Here frequency offset fo of 1KHz and phase offset of 22.5Â° (/8) is used. The output of frequency estimator with different value of which represents stability is given in Fig. 5. From Fig. 5 we can see that as value of varies the settling time also varies. For larger value of , the settling time is low, while for smaller vale of settling time is higher.
Fig. 9: (a) Frequency tracked by frequency estimator in DPLL. (b) Phase tracked by phase estimator in DPLL
Fig. 10: Frequency tracked by frequency estimator in DPLL for different values of .
Hence the higher stability can be achieved by increasing the value of .
The comparison shows that DPLL is more stable with less settling time. It is faster and has wide range. The costas loop works for a lower offset in compared to DPLL and has a disadvantage of time delay.

CONCLUSION
Comparison of complete time domain simulations on Costas loop and DPLL synchronization mechanism is presented in this paper. The operation of both the tracking methods is presented here. The costas loop for carrier recovery is applicable only at lower carrier offset. This disadvantage can be overcome while using DPLL frequency and phase estimator.
DPLL frequency and phase estimator is having a low settling time in compared to Costas loop and hence is more stable.

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Umberto Mengali and Aldo N. D Andrea, Synchronization Techniques for Digital Receivers, Plenum Press, New York, 1997.
ACKNOWLEDGMENT
The author is grateful to Mr. M. K. Vijayan Pillai, Scientist G, NPOL and Mrs Kala Vijayan for their support throughout the work.
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