True Time Delay (TTD) Beam Steering using Low-Compute Microcontrollers

True Time Delay (TTD) Beam Steering using Low-Compute Microcontrollers

Norin Roby Issac (1), Kshitij Pandey (2), Rajesh GD (3), Aadyot Nandan (4), Prashant Patavardhan (5)

(1,2,3,4,5) RV Institute of Technology and Management, Bengaluru

Roopa Kulkarni6, Mandar Jatkar (7)

(6,7) Dayananda Sagar Academy of Technology and Management, Bengaluru

Abstract – Beam steering is a method for controlling the effective direction of the radiation pattern of an array of transducers by controlling their relative phase and amplitude. This allows for the creation of radiation patterns with directed lobes. Tradi-tional beam steering methods utilise custom hardware to control phase and amplitude; however, these approaches typically require microcontrollers to continuously track and update phase in real time, which demands high clock speeds and instruc-tion throughput, resources that low-compute microcontrollers do not have. This paper proposes a system for implementing true time delay (TTD) beam steering using a reference sine wave, comparator and toggle flip flop that allows a microcon-troller to perform TTD beam steering using only voltage inputs, without needing to compute or track timing continuously, and discusses the implementation of such a system on an FPGA, with microcontroller like inputs, producing TTD square waves.

Keywords: Beam steering, comparator, FPGA, low- compute microcontroller, reference sine wave, toggle flip flop, true time delay (TTD)

1. INTRODUCTION

   Beam steering is a fundamental technology used to steer a wavefront electronically, without the use of physical actu-ators or any physical movement. This is achieved through the careful alteration of the relative phase and amplitude of an array of radiating elements, which results in a super-position of their waves interfering to form directed lobes. This high speed, high accuracy steering ability makes beam steering useful in modern day 5G and 6G Wi-Fi sys-tems, military radars and medical factors and radiation pat-terns. Conventional microcontroller-driven beam steering requires the controller to continuously compute and update phase values in real time, typically via a timer interrupt or polling loop that must execute every clock cycle to track timing accurately. This places a direct demand on the mi-crocontrollers clock speed and instruction throughput: a low-compute microcontroller, meaning one with a limited clock speed and correspondingly limited ability to perform several timing calculations per second, cannot reliably sus-tain this kind

   of continuous real-time tracking. This paper proposes a system in which the microcontroller instead cal-culates a single threshold voltage per phase-shift update, and hands off the actual timing generation to a compara-tor and toggle flip flop, removing the need for continuous computation entirely. Results highlighted beam-squint vul-nerabilities of phase shifters and imaging devices. Current beam steering systems use microcontrollers or FPGAs to adjust phase and amplitude across an array of elements, with the latest technologies including the use of optical phased arrays that apply the concept of beam steering to the near-infrared domain for use in LiDARs, the use of intel-ligent, reconfigurable metasurfaces to perform beam steer-ing and the integration of AI into beam steering systems to analyse returning waves.

2. PAPER ORGANIZATION

   The remainder of this paper is organized as follows. Section 3 presents a literature survey of existing beam steering and true-time-delay approaches, situating the pro-posed system relative to prior phase-shifter, optical, and metasurface-based methods. Section 4 describes the sys-tem design and architecture, detailing how a reference sine wave, comparator, and toggle flip flop are combined to generate phase-shifted square waves from a single micro-controller voltage input. Section 5 covers the implemen-tation of this architecture, including circuit- level simula-tion in LTSpice and logic-level implementation in Verilog on an FPGA. Section 6 presents the results and discus-sion of these simulations. Section 7 outlines the limita-tions and scope of the work, clarifying that the results presented are based on simulation and educational-grade FPGA demonstration rather than physical hardware char-acterization. Section 8 concludes the paper, and the Refer-ences section lists the sources cited throughout.

3. LITERATURE SURVEY

   Beam steering in phased arrays is strongly limited by beam squint when conventional phase shifters are used over wide bandwidths, which is why true-time-delay beam steering has become the preferred solution for broadband systems. Longbrake [2] clearly establishes this motivation by comparing phase-shifter arrays with TTD-based beam steering and showing that delay

   networks can preserve steering accuracy across frequency, although practical im-plementations still face insertion loss and hardware com-plexity. At the array level, Alchami et al. further show that element placement affects steering behavior, since nonuni-form arrays can produce narrower beams but demand larger phase shifts, whereas ULA structures are easier to control because they require smaller phase differences. Once the need for TTD is established, the next challenge is imple- mentation using hardware that is compact and power effi-cient. Jung et al. [7] demonstrated a wideband TTD phase shifter in 28 nm CMOS with discrete phase states, proving that hardware-based delay control is possible in a compact form, even though continuous tuning is still limited. In parallel, Frankel et al. [4] and Rideout et al.

   [5] show optical TTD approaches that deliver precise wideband beamform-ing,2 but these methods are relatively complex and intro-duce cost, insertion loss, and integration overhead. These works are important because they define the upper end of beamforming performance, against which a low-compute microcontroller-based solution can be positioned as a sim-pler and more accessible alternative.

   For practical control and calibration, Ong et al. [6] and Nakamoto et al. [10] are especially useful because they show that beam quality is highly sensitive to calibration, phase accuracy, and element errors. Ong et al. emphasize that miscalibration can shift the main beam at wide band-widths, while Nakamoto et al. demonstrate that compen-sation of element field and phase errors can improve direc-tivity and reduce sidelobes. Together, these studies support the idea that even if the delay hardware is simple, the steer-ing controller must still generate accurate timing and apply careful calibration.

   Low-cost implementations also support the feasibility of this direction. Gaviola et al. [1] showed that an Arduino Due can generate time-shifted PWM for beam steering in a speaker array, while Marzo et al. [6] introduced Ultraino as an open phased-array framework for real-time ultrasonic control. Although these are not TTD beamformers in the strict RF sense, they are useful background examples be-cause they demonstrate that low-cost controllers can man-age synchronized steering signals for array systems.

4. SYSTEM DESIGN AND ARCHITECTURE

   The phase shifter unit uses a TTD system as seen in

   [2] to implement phase shifts without introducing beam squint. To overcome the expense and complexity of tra- ditional beam steering methods and implement TTD beam steering, we propose a system that uses a sine wave as a timing reference, to generate square waves that are shifted in time. The system consists of a reference sine wave gen-erator, which enerates a sine wave of a known frequency and hence predictable voltage levels at a given time, a com-parator that generates a high or low

   output depending on its inputs, and an edge triggered toggle flip flop, chosen because its edge selectivity ensures square waves with uni-form periods are generated, and setting the toggle input to logical high continuously toggle inputs between high and low. The reference wave and microcontroller voltage input are fed into the comparator, whose output is in turn fed as a clock signal to the toggle flip flop (Figure 1). To implement a given phase shift, the microcontroller calculates the volt- age level of the sine wave at the given phase and sets the comparator threshold voltage accordingly. The equations

   1.1 and 1.2 govern the phase delay and threshold voltage.

   T = /(2F) (1.1)

   th max )

   V = V · ( 1 + sin(2FT ) (1.2)

   T desired time shift

   F reference sine wave frequency

   The reasoning behind these equations is as follows to im-plement a phase shift, we first need to know the time delay to be applied. This is done through equation 1.1, which calculates the time corresponding to the given phase delay. Equation 1.2 uses this time delay to calculate the voltage level of the reference sine wave at that time and biases it by half the sine wave amplitude so that all input voltage levels are positive. It is to be noted that the sine wave must also be biased to be entirely positive.

   Figure 1: Block Diagram of the proposed system

5. IMPLEMENTATION

   Implementation of the circuit began with simulation in LTSpice, with D flip flops being reconfigured to function as T flip flops, and operational amplifiers being used as comparators (Figure 2). The simulation demonstrated suc-cessful phase shifting with the variation of voltage inputs to the comparators (Figure 3). This simulation also high-lighted the need for a system reset switch to synchronise the flip flops before changing threshold voltages to implement a phase shift. Hardware implementation was carried out on an FPGA by replacing the analogue comparator compo-nent with a digitised version that represented voltage inputs as discrete binary

   steps. The master sine wave was also replaced with a stepped waveform generator. Both these changes were implemented using Verilog code, which de- fined the comparator as a module whose output goes high when the first input from the sine wave generator is equal to or greater than the threshold voltage input from the micro-controller, and the stepped waveform generator as a counter that alternates between counting upwards and downwards. After simulation of the Verilog system in Icarus Verilog (Figure 4) the code was dumped onto an FPGA whose out-puts were fed to LEDs to visually demonstrate the phase shifted waves (Figure 5 (a) & (b)).

   intersection points indicating where the threshold voltages were set, and also indicating that all waves maintain a uniform period and phase relationship throughout the circuits operation. The Verilog simulation of the discretised circuit (Figure 4) demonstrates similar re-sults, with out1 and out2 maintaining a definite phase delay and duration. Both mixed analogue-digital (LTSpice) and analogue only (Verilog and FPGA) simulations point to a functional, usable system.

   Where:

   Figure 2: Simulated Circuits

   (a) (b)

   Figure 5: FPGA Simulation, microcontroller input simulated with switches, input is 1110, a hypothetical binary voltage level

   (a) out1 is off while out2 is on (b) both out1 and out2 are on once the time delay corresponding to the input voltage level has

   elapsed

   Desired phase delay

   Vth Threshold voltage

   Vmax Maximum sine wave amplitude

   Figure 3: LTSpice Outputs

   Figure 4: Icarus Verilog Simulation

6. RESULTS AND DISCUSSION

   The proposed system consisting of a reference sine wave generator, comparators and T flip flops were first simulated in LTSpice. The simulation results, (Figure 2), show the outputs with threshold voltages set to 0.9, 0.8, 0.7 and 0.6 V for four different phase shifter units (Figure 4). The out-puts of the comparators are overlapped with the reference sine wave, with the

7. LIMITATIONS AND SCOPE

   This work validates the proposed TTD beam steering ar-chitecture through circuit-level (LTSpice) and logic-level (Verilog/FPGA) simulation, using an educational-grade FPGA for demonstration purposes. As such, the results presented here characterize the functional correctness and timing behavior of the proposed architecture in simula-tion, rather than physical hardware performance. Phys-ical characterization of timing accuracy, including com- parator propagation delay, flip-flop jitter, and temperature-dependent drift, was outside the scope of this work and is identified as a direction for future development, alongside integration with a physical antenna array to demonstrate an end-to-end beam steered radiation pattern.

8. CONCLUSION

The paper successfully proposes and validates, through simulation, a system for implementing true- time-delay (TTD) beam steering with low-compute microcontrollers, by allowing a microcontroller to output a single voltage representing the required time delay corresponding to the desired phase shift, rather than continuously computing and tracking timing in real time. The proposed system was successfully implemented on an FPGA and demonstrates shifted square wave generation, using basic building blocks of digital electronics. By reducing the microcontrollers task from continuous real-time phase tracking to a single calculation and voltage output per update, this approach al-lows even microcontrollers with limited

clock speed and processing throughput to interface with the proposed sys-tem to perform TTD beam steering.

REFERENCES

1. A. D. S. Gaviola, M. Rivai, and H. Kusuma, Audio beam steering with phased array method using Arduino Due microcontroller, in Proc. 2018 International Conference on Information and Communications Technology (ICOIACT), Yogyakarta, Indonesia, Mar. 2018, pp. 597600, doi: 10.1109/ICOIACT.2018.8350683.

2. M. Longbrake, True time-delay beamsteering for radar, in Proc. 2012 IEEE Nat. Aerosp. Electron. Conf. (NAECON), Dayton, OH, USA, Jul. 2012, doi: 10.1109/NAECON.2012.6531062.

3. F. H. Ahmed and S. K. Khamas, Large- and

4. small-scale beam-steering phased array antennas using variable phase BLC for millimeter-wave applications, Sensors, vol. 25, no. 12, p. 3714, 2025, doi: 10.3390/s25123714.

5. C. Fan, M. Caleap, M. Pan, and B. W. Drinkwater, A comparison between ultrasonic array beamforming and super resolution imaging algorithms for

6. non-destructive evaluation, Ultrasonics, vol. 54, no. 7, pp.

   18421850, 2014, doi:

7. 10.1016/j.ultras.2013.12.012.

8. N. Alchami, K. Kolpatzeck, B. Husain, Y. C. Kara, and A. Czylwik, Comparative study of true time delay beam steering with antenna arrays at THz frequencies, in Proc. 49th Int. Conf. Infrared, Millimeter, and Terahertz Waves (IRMMW-THz),

   Montre´al, QC, Canada, Sep. 2024, pp. 12, doi:

9. 10.1109/IRMMW-THz60956.2024.10697885.

10. A. Marzo, T. Corkett, and B. W. Drinkwater, Ultraino: An open phased-array system for narrowband airborne ultrasound transmission, IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 65, no. 1, pp. 102 111, 2018, doi: 10.1109/TUFFC.2017.2769399.

11. M. Jung, H.-J. Yoon, and B.-W. Min, A wideband true-time- delay phase shifter with 100% fractional bandwidth using 28 nm CMOS, in Proc. EEE Radio Frequency Integrated Circuits Symposium (RFIC), Los Angeles, CA, USA, Aug. 2020, pp. 59 62, doi: 10.1109/RFIC49505.2020.9218479.

12. R. Ong, S. Raju, and M. K. Raja, Impact of phase shifter design on beam squinting in phased array, in Proc. IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting (APS/URSI), Singapore, Dec. 2021, pp. 121122, doi: 10.1109/APS/URSI47566.2021.9704319.

13. M. Y. Frankel, R. D. Esman, and M. G. Parent, Array transmitter/receiver controlled by a true time-delay fiber-optic beamformer, IEEE Photon. Technol. Lett., vol. 7, no. 10, pp. 12161218, Oct. 1995, doi: 10.1109/68.469718.

14. N. Nakamoto, T. Takahashi, Y. Konishi, and I. Chiba, Phase Optimization for Accurate Beam Forming of Phased Array with Element Field Errors at Every Phase Shift, in 2013 IEEE International Symposium on Phased Array Systems and Technology, Waltham, MA, USA, Oct. 2013, pp. 693697, doi: 10.1109/ARRAY.2013.6731902.

AUTHOR BIOGRAPHIES

Norin Roby Issac is a student of RV In-stitute of Technology and Management (RVITM), Bengaluru, currently pursuing a Bachelor of Engineering in Electronics and Communication Engineering. His in-terests include beam steering, digital and analogue design.

Kshitij Pandey is a student of RVITM currently pursuing Bachelor of Engineer-ing in Electronics and Communication. His research interests include beam form-ing, electrical and electronic networks, semiconductors and IoT.

Rajesh G.D. is a student of RVITM cur-rently pursuing Bachelor of Engineering in Electronics and Communication. His research interests include beam forming, electronic networks and IoT.

Aadyot Nandan S is a student of RV In-stitute of Technology and Management (RVITM), Bengaluru, currently pursu-ing a Bachelor of Engineering in Elec-tronics and Communication Engineering. His interests include software engineer-ing, open-source development, and com- puter systems.

Dr. Prashant Patavardhan received his B.E. in Electronics and Communi-cation Engineering from Karnataka Uni-versity in 1995. He earned his M.Tech. in Digital Electronics and Communica-tion Systems from Visvesvaraya Techno-logical University (VTU), Belagavi, in 2001, graduating as the University Top-per. He was awarded the Ph.D. degree by VTU, Belagavi in 2011. With over 29 years of academic experience, he has served in various teaching, research and academic leadership roles, including as professor and head in the Department of Electronics and Communication En-gineering at RV Institute of Technology and Management (RVITM), Bengaluru, Dayananda Sagar University, Bengaluru, and KLS Gogte Institute of Technology (KLS GIT), Belagavi. Throughout his career, he has made significant contri-butions to academic administration, cur-riculum development, outcome-based ed- ucation, research supervision and institu-tional quality enhancement. His research interests include biometrics, signal, im-age and video processing, artificial neu-ral networks, fuzzy logic, pattern recog-nition, embedded systems and intelligent computing. He has published more than 30 research articles in international jour-nals and has presented his research at several national and international confer-ences.

Roopa R. Kulkarni is an academician and researcher in the field of electron-ics and communication engineering. She holds a strong background in VLSI de-sign, semiconductor devices, and emerg-ing nanotechnologies. Her research in-terests include low-power system de- sign, graphene-based devices, and ad-vanced transistor technologies for next-generation computing systems. She has contributed to several scholarly publi-cations in reputed journals and confer-ences, focusing on innovative circuit de-sign and optimization techniques. She is actively involved in teaching, mentoring students, and guiding research projects at the undergraduate and postgraduate lev-els. Her work emphasizes bridging theo-retical concepts with practical implemen-tations in modern electronic systems.

Mandar Jatkar is an academician in the field of electronics and communication engineering, with a strong focus on VLSI design and semiconductor technologies. He has extensive experience in teach-ing and research, particularly in areas such as ASIC design, embedded systems, and modern chip design methodologies. His research interests include low-power VLSI design, system-on-chip (SoC) ar-chitectures, and emerging trends in the semiconductor industry. He has been actively involved in organizing technical events, panel discussions, and workshops to bridge the gap between academia and industry, especially in the domain of VLSI careers and innovation. He is com-mitted to mentoring students and guid-ing them toward industry-ready skills, while also contributing to academic re-search through publications and collabo-rative projects.