 Open Access
 Total Downloads : 314
 Authors : K.L.N.Chaitanya, K.Srividya Savitri , R.Shirisha
 Paper ID : IJERTV2IS1455
 Volume & Issue : Volume 02, Issue 01 (January 2013)
 Published (First Online): 01022013
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Space Vectors Modulation for Dual Output Con verters
Space Vectors Modulation for Dual Output Converters
K.L.N.Chaitanya Â¹ 
K.Srividya Savitri Â² 
R.Shirisha 3 
PG Student 
Assistant Professor 
Assistant Professor 
CMR College of engg & technology 
CMR College of engg & technology 
CMR College of engg & technology 
AbstractRecently, nineswitch inverter and nineswitchz source inverter have been proposed as dual output inverters. In this paper, the space vector modulation (SVM) of nineswitch in verter and nineswitchzsource inverter is proposed. The proposed method increases the sum of modulation indices up to 15% in con trast with the conventional, scheme in which the sum of modulation indices is equal or less than one. The extra voltage available for a given input dcvoltage, translates to a higher torquea critical fac tor for defining the capacity of products in marketplace. Also, in order to further reduce the cost of power devices and also thermal heat effect, and to reduce the number of semiconductor switch ing, specific SVM switching pattern is presented. This feature will be advantageous for highpower inverter applications where cost and efficiency are key decision factors. Furthermore, a novel SVM is proposed for minimizing total harmonic distortion. The per formance of the proposed SVM for both nineswitch inverter and nineswitchzsource inverter is verified by simulation. Experimen tal results validate the simulation results as well as the superiority of the proposed SVM.
Index TermsNineswitch inverter, nineswitchzsource in verter, space vector modulation (SVM).

INTRODUCTION
NVERTERS are used as dc/ac converter and power controller for ac load such as motor drivers. In many cases, there are two or more ac loads, which require independent control. The conventional solution is to use separate inverters. This increases cost and volume of system. A dual output inverter has been presented in [1] using only nine semiconductor switches (see Fig. 1). This inverter is known as nineswitch inverter and is also used as an ac/ac converter in [2] and [3]. The nineswitch inverter is composed of two conventional inverters with three common switches. In nineswitch inverter, sum of modulation index of two outputs must be less than or equal to one. Therefore, voltage amplitude of outputs is smaller, compared with two separate inverters [4]. To remedy this problem, this paper proposes using an impedance source (zsource) network in front of nineswitch inverter as a dc/dc boost converter (see Fig. 2). Zsource network was used as frontend boost converter for a conventional inverter in [5], for the first time. This inverter was called zsource inverter and has been proposed for fuel cell, photovoltaic, and wind
turbine systems [6][8]. The zsource network also was used in other converters such as threelevel inverters [9], [10].
In [1], carrierbased pulsewidth modulation (PWM) methods have been proposed for nineswitch inverter. This paper pro poses space vector modulation (SVM) methods for the afore mentioned nineswitch and nineswitchzsource inverters
Fig. 1. Nineswitch inverter.
Fig. 2. Nineswitchzsource inverter.
. In order to reduce number of semiconductor switching and total distortion harmonic (THD), some specific switching patterns for SVM are proposed.
This paper is organized as follows. Section II describes the carrierbased PWM control method for nineswitch inverter. Section III describes the proposed SVM for nineswitch inverter, as well as two special SVMs with minimum switching number and THD. The proposed SVM is developed for nineswitchz source inverter in Section IV. Section V describes maximum gain. Finally, Section VI presents simulation and experimental results.

CARRIERBASED PWM METHOD
The carrierbased PWM control method for nineswitch in verter is shown in Fig. 3. There are two reference signals (upper and lower) for each phase. The upper and lower reference sig nals are related to upper and lower outputs respectively. The
Fig. 3. Carrierbased PWM method for nineswitch inverter.
Fig. 4. Carrierbased PWM method switching vector.
gate signal for upper switch of a leg is generated by comparing the carrier signal and upper reference signal of the related phase (Vref U J ). Similarly, the gate signal for lower switch is generated from the carrier signal and lower reference signal of the related phase (Vref LJ ). The gate signal for mid switch is generated by the logical XOR of the gate signals for upper and lower switches. With this method, always two switches are ON in each leg.
Fig. 4 shows carrierbased PWM method switching vectors. There are six vectors in each switching cycle for both outputs: two nonzero vectors, one zero vector 0 0 0, two nonezero vectors and one zero vector 1 1 1 {two activeshort zero (0 0 0)two activelong zero (1 1 1)}. In an active vector, output load is connected to the dc input source, while in a zero vector, the output load is shortcircuited. When one of the outputs has an active or short zero (0 0 0) vector, the other output has long zero (1 1 1) vector.

SVM FOR NINESWITCH INVERTER
In regard to Fig. 3, each leg can be in three different semi conductors ONOFF position. These position can be called {1},
{0}, and {1}, as is illustrated in Table I. In Table I, J refers to leg A, B, or C and U , M , L refers to upper, mid, and lower semiconductor, respectively.
TABLE I SEMICONDUCTORS ONOFF POSITION OF LEGS
Fig. 5. Typical SVM switching vector sequence.
TABLE II
SVM SWITCHING VECTORS
The combination of switching vector of both outputs in Fig. 4 creates a specific sequence as shown in Fig. 5. This sequence is used to design SVM method. There are 12 vectors in each switching cycle: {two upper active (VAU )zero (VZ )two upper active (VAU )zero (VZ )two lower active (VAL )zero (VZ )two lower active (VAL )zero (VZ )}. The switching vec tors are listed in Table II. The vectors V1 V6 are upper active vectors. In these vectors, the upper output is in active state, and the lower output is in zero state. There is an inverse logic in lower active vectors (V7 V12 ). In zero vectors (V13 V15 ), both outputs are in zero state.
Table II does not include all possible variations of switching states {1}, {0}, and {1}. Since a vector including {1} and
{0} connects both loads to the dc source at the same time, the loads lose their independence and they cannot have independent frequencies. This is the reason for avoiding a vector that includes combinations of {1} and {0}.
In none of the switching vectors as listed in Table II, both outputs are not in an active state at the same time. However, in vectors including both {1} and {0} such as {1, 1, 0}, both outputs are in active state. These vectors are ignored because there are not all combinations of active vectors for both outputs. For example, if upper output be in active vector (1 1 0), lower output can be in vectors (0 0 0), (1 0 0), (0 1 0), or (1 1 0) as
shown in Fig. 6. However, vectors (0 1 1), (0 0 1), and (1 0 1) are not available for lower output. Therefore, outputs cannot be controlled independently.
Fig. 6. Available switching vectors of nineswitch inverter while upper output
is in active vector (1 1 0). Fig. 8. SVM with reduced number of semiconductor witching.
T2 =
3 mU T sin(U ) (6)
2
T3 =
3

mL
T sin
L
L
3
(7)
T4 =

mL T sin(L ) (8)
2
Fig. 7. Space vector diagrams for nineswitch inverter. (a) Upper output. (b) Lower output.
To = T T1 T2 T3 T4 (9)
where T1 , T2 are the time interval of upper active vectors, T3 , T4 are time of lower active vectors, To is time of zero vectors and T is switching period. mU and mL are upper and lower modulation indices, respectively, and defined by
To determine the proper active vectors, two space vector di agrams are proposed as shown in Fig. 7. The diagrams (a) and
(b) are used to determine the upper and lower active vectors,
mU = 2 Vref U
Vi
V
(10)
respectively. The SVM active vectors are determined with re gard to location of upper reference signal (VÂ¯re f U ) in the diagram
m L = 2
ref L . (11)
Vi

and lower reference signal (VÂ¯re f L ) in the diagram (b). The reference signals for the upper and lower outputs are defined as
VÂ¯ref U = Vref U U (1)
The sum of active vector time intervals must be less or equals to T . Thus, the following constrain must be satisfied (see Appendix):
where
VÂ¯ref L
= Vref L L
(2)
(mU
2
+ mL )
3
1.155. (12)
U = 2fU t + U (3)
L = 2fL t + L (4)
where fU , fL are the frequencies, and U , L are the phases. All zero vectors V13 , V14 , and V15 can be used for zero states. The type of zero vectors can be selected based on control goals and optimizations such as minimum number of semiconductor switchings.
The switching time intervals of vectors are calculated as
Equation (12) clearly indicates that in the proposed SVM scheme, sum of modulation indices increases about 15%a very important feature to provide higher torque for a given input dcvoltage. In the case of washing machines, the above capability translates to higher machine capacity (in terms of cloth load) at high spin speed (e.g., 1800 r/min)an important product feature in marketplace.
A switching vector sequence for the proposed SVM is shown in Fig. 8. This switching sequence is developed to reduce the number of semiconductor switching. The zero vectors are placed
T1 =
3
2 mU
T sin
U
U
3
(5) just between two upper and lower active vectors. In upper active vectors, legs are in state {1} or {0} and in lower active vectors,
Fig. 9. SVM with reduced THD.
legs are in state {1} or {1}. If V13 zero vector is placed between the active vectors, minimum number of switching is required. While if V14 or V15 zero vectors are used, number of switching is increased.
There are two odd active vectors (V1 , V3 , V5 , V8 , V10 , and V12 ) and two even active vectors (V2 , V4 , V6 , V7 , V9 , and V11 ) in a switching sequence. In an even active vector, two legs are in state {1}, while in an odd active vector only one leg is in state
{1}. If even active vectors are placed next to V13 , number of switching will be reduced even more (see Fig. 8).
There are other possible switch generation methods too, e.g., a switching method, to reduce THD. To minimize THD, active vectors for each output should be centrally placed within the switching period [11]. Fig. 9 shows a switching vector sequence that shifts active vector into center of switching period, hence reducing THD. In this sequence, zero vectors are inserted be tween active vectors. In Fig. 9, V14 is inserted between upper active vectors and V15 is inserted between lower active vectors.


NINESWITCHZSOURCE INVERTER SVM
The nineswitchzsource inverter is shown in Fig. 2. This inverter has an extra zsource network including two inductors (L1 and L2 ), two capacitors (C1 and C2 ) and a diode (D). The zsource network is similar to a dc/dc boost converter with [12]
TABLE III
SHOOTTHROUGH VECTORS OF NINESWITCH ZSOURCE INVERTER
TABLE IV
ONOFF POSITION OF SEMICONDUCTOR SWITCHES IN STATE {2}
Fig. 10. Nineswitchzsource inverter SVM with reduced switching.
when the inverter has a zero state. Table III shows all the vectors that the inverter includes zero state and the zsource network has a shootthrough state. These vectors are known as shoot
Vi = B Vo
(13)
through vectors. There is a new state (state {2}) in Table III. The ONOFF position of switches of a leg in state {2} is shown
where Vo is input dc voltage and Vi is output of zsource network.
B is known as boost factor and is given by following equation:
in Table IV. All vectors of Table III can be used for generating
1
B = 1 2(TSC /T )
(14)
a shootthrough state.
Fig. 10 shows a SVM vector sequence for nineswitch inverter
where TSC is shootthrough time. In the shootthrough times, the output of zsource network is shorted through the switches of the inverter. During shootthrough state, since the inverter (output of zsource network) is shorted, inverter cannot have an active vector. Therefore a shootthrough state can only occur
with reduced number of switching. The sequence is a modi fied version of Fig. 8. Two shootthrough vectors are placed in both sides of zero vector (V13 ). Here, the shootthrough vec tor close to upper active vector is called upper shootthrough vector (VSCU ) and the shootthrough vector close to lower
TABLE V
DETERMINING UPPER AND LOWER SHOOTTHROUGH VECTOR WITH REDUCED NUMBER OF SWITCHING
TABLE VI
DETERMINING UPPER AND LOWER SHOOTTHROUGH VECTOR WITH REDUCED THD
According to (12), in nineswitch inverter, sum of modulation indices should be smaller than 1.15. If the same amplitude for both ac outputs is desired, we have
Vac U m a x = Vac L m a x =
Vi
. (17)
2 3
If amplitude of one of the outputs is set to zero, maximum amplitude of other output can be increased
Vac
= Vi (18)
m a x
m a x
3
For nineswitchzsource inverter, the magnitude of peak phase voltage of ac outputs can be expressed by
Fig. 11. Nineswitchzsource inverter SVM with reduced THD.
Vo
VacU =
B 2
(19)
active vector is called lower shootthrough vector (VSC L ). All
mU
VacL =
BmL
Vo . (20)
2
vectors listed in Table III can be used as the upper and lower shootthrough vectors. However, vectors V27 , V30 , and V33 are preferred because those vectors have only one state {2} and need less switching. As shown in Fig. 10, even active vectors are placed close to shootthrough vectors (the reason described in Section III). In even active vectors, two legs are in state {1} and one leg is in state {0} or {1}. On other hand, in shoot through vectors V27 , V30 , and V33 , two legs are in state {1} and one leg is in state {2}. To reduce the number of switching, the two legs in state {1} must have the same state in an even active vector and shootthrough vector close to it. Table V can be used for shootthrough vectors selection.
For reducing THD, switching sequence shown in Fig. 11 is developed for nineswitchzsource inverter. Similar to Fig. 9, zero vectors and shootthrough vectors are inserted between similar active vectors. Table VI can be used for shootthrough vector selection with reduced THD.
The voltage gains can be defined by [13]
GU = BmU (21)
GL = BmL . (22)
Boost factor is limited by voltage rating of semiconductor switches (VS ). For a given voltage rating, maximum boost factor can be calculated by
Bmax = VS . (23)
Vo
Maximum voltage gain is determined by:
Gma x = Bma x mma x B (24) where mma x B is the maximum possible modulation index, when
B is at its maximum value. If the same ampltude for both ac outputs is desired mma x B can be calculated by

MAXIMUM GAIN mma x B =
1 (1/Bmax + 1) . (25)
The magnitude of peak phase voltage of ac outputs of nine switch inverter can be expressed by
2 3
Thus
1
VacU = mU Vi
2
(15)
Gma x = (Bma x + 1). (26) 2 3
V = m Vi . (16)
acL L 2
If amplitude of one of the outputs is set to zero, maximum possible modulation index for other output can be determined
Fig. 12. Maximum voltage gain (Gm a x ) versus Vo (for nineswitch inverter) or Vi (for nineswitchzsource inverter) for a given switch voltage rating (VS ). (a) Nineswitch inverter: equal maximum amplitudes. (b) Nine switchzsource inverter: equal maximum amplitudes. (c) Nineswitch inverter: maximum am plitude for one of the outputs. (d) Nineswitchzsource inverter: maximum amplitude for one of the outputs.
TABLE VII SIMULATION PARAMETERS
Fig. 13. (a) Line voltage of nineswitch inverter (simulation). (b) Line voltage of nineswitch inverter (experimental), (50 V/DIV, 10 ms/DIV).
by
Thus
mma x B = 1
3
1
1
Bmax
+ 1 . (27)
Gma x =
3
(Bma x + 1). (28)
Fig. 12 shows maximum possible voltage gains for a given switch voltage rating.

SIMULATIONS AND EXPERIMENTAL RESULTS
The proposed SVMs are simulated for nineswitch inverter and nineswitchzsource inverter. Prototypes of both converters also were built using DSP for verifying the proposed SVMs. Two similar resistive loads with LC filters are connected to the outputs of inverter. Simulation parameters are listed in Table VII.
The nineswitch inverter with input dc source of 150 V is simulated and implemented with reduced number of switching SVM. Figs. 13 and 14 show lineline voltage and phase voltage of both outputs, respectively. It can be seen that both outputs have expected frequencies. The load current is shown in Fig. 15. It can be seen that the load currents have nearly sinusoidal waveforms.
Fig. 14. (a) Phase voltage of nineswitch inverter (simulation). (b) Phase voltage of nineswitch inverter (Experimental), (50 V/DIV, 10 ms/DIV).
In second simulation, a zsource network including L1 = L2 = 2 mH and C1 = C2 = 2.2 mF was added to nine switch inverter. An input dc source of 100 V is used. To boost input voltage to 150 V, TSC /T was set to 0.166 considering (14). The output of zsource network (Vi ) is shown in Fig. 16. As expected, Vi magnitude changes between 0 and 150 V, respectively. Fig. 17 shows zsource network capacitor voltages. The voltage is equal to expected value of 125 V. Capacitor voltage is 0.5 (VO + Vi ), as described in [5].
Fig. 15. (a) Output currents of nineswitch inverter (simulation). (b) Output currents of nineswitch inverter (experimental), (2 A/DIV, 10 ms/DIV).
Fig. 16. Output voltage of zsource network (simulation).
phase voltage of both outputs, respectively. The load current is seen in Fig. 20.
Number of switching of semiconductors for nineswitch in verter and zsourcenineswitch inverter using carrierbased PWM and the proposed SVMs are shown in Table VIII. Number of switching for 0.1 s with parameters of Table VII is calculated. As seen in Table VIII, number of switching is considerably re duced using proposed SVMs.
Fig. 21 shows THD of load current versus load current magni tude for four different cases: 1) carrierbased PWM, 2) minimum number of switching SVM, 3) reduced THD SVM, and 4) six switch inverter with SVM. Note that, for six switch inverter, dc bus voltage is set to 75 V, while for nineswitch inverters; dc bus voltage is set to 150 V. It is seen that the reduced THD SVM has best harmonic performance for nineswitch inverters. As seen in Fig. 21, sixswitch inverter has better harmonic performance.
Fig. 17. (a) Capacitor voltage of nineswitchzsource inverter (simula tion). (b) Capacitor voltage of nineswitchzsource inverter (experimental), (50 V/DIV, 1 ms/DIV).
Fig. 18. (a) Line voltage of nineswitchzsource inverter (simulation). (b) Line voltage of nineswitchzsource inverter (experimental), (50 V/DIV,
10 ms/DIV).
Fig. 19. (a) Phase voltage of nineswitchzsource inverter (simulation).

Phase voltage of nineswitch zsource inverter (experimental), (50 V/DIV, 10 ms/DIV).
Fig. 20. (a) Output currents of nineswitchzsource inverter (simulation).
(b) Output currents of nineswitchzsource inverter (experimental), (3 A/DIV, 10 ms/DIV).
TABLE VIII
NUMBER OF SEMICONDUCTOR SWITCHING
Fig. 21. THD of load current of nineswitch inverter and sixswitch inverter.
Main reason is that in nineswitch inverter, active vectors are not centered within the switching period.


CONCLUSION
In this paper, the SVM of nineswitch inverter and nine switchzsource inverter was proposed. Switching sequence of the proposed SVM is composed of the upper active vectors, the lower active vectors and the zero vectors. The upper and lower active vectors are determined via two space vector diagram. The proposed SVM increases sum of modulation indices up to 15%, an important feature in providing higher torque for a given input dcvoltage. The proposed SVM is also developed for nine switchzsource inverter via extra shootthrough vectors. For both inverters, two SVM algorithms are developed to reduce THD and number of semiconductor switching.
The proposed SVMs were simulated for both nineswitch in verter and zsource nineswitch inverter. An experimental setup was developed using a digital signal processor (DSP). The per formance of the proposed SVMs was verified using computer simulation, and it was validated using experimental data.
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K.L.N. Chaitanya received the Bachelor degree from Vasavi College of Engineering in Year 2010 and the Master degree from CMR College of Engineering and Technology in Year 2012. His research interests include applications of advanced electrical drives and power electronics.
K Srividya Savitri received the Bachelor degree from Sridevi Womens Engineering College in Year 2006 and the Master degree from Jawaharlal Nehru Technological University in Year 2009. She is currently working as Assistant Professor in the Department of Electrical and Electronics Engineering, CMR College of Engineering and Technology, Hyderabad. Her research interests include inverters, motor drives, inverterbased distributed generation, hybrid electric vehicle, and FACTS.
R. Shirisha received the Bachelor degree from SR Engineering College in Year 2006 and the Master degree from Vagdevi College of Engineering in Year 2011. She is currently working as Assistant Professor in the Department of Electrical and Electronics Engineering, CMR College of Engineering and Technology, Hyderabad. Her research interests include modeling, analysis, design and control of power electronic converters/system