 Open Access
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 Authors : Gajendra K A, Prasanth N, Naveed Anjum, Dr. H R Bhagyalakshmi , Likhith B P
 Paper ID : IJERTV3IS050951
 Volume & Issue : Volume 03, Issue 05 (May 2014)
 Published (First Online): 22052014
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Programmable Current Gain CMOS Amplifiers
Naveed Anjum, Likhith B P, Gajendra K A, Prasanth N
Electronics and communication, BMS College of Engineering, Bangalore, India
Dr. H R Bhagyalakshmi
Asso. Prof., Electronics and communication, BMS College of Engineering, Bangalore, India
Abstract In many systems, a wide range of gain variation is required. So a gain control circuit is essential. One common topology (GC) is based on opamp with resistive array gain stages. High linearity and constant wide bandwidth are achieved by using high gain amplifier with low input impedance and resistor network feedback. The voltage gain is varied by controlling the input switched MOSFETs. In this paper, the Programmable gain amplifier (PGA) with variable current gain and maintaining a constant bandwidth is presented.
Keywords Gain and Bandwidth, Linearity, Noise, Switched resistor, transconductance.

INTRODUCTION
In most of todays modern mixed signal applications, a variable gain amplifier is required to maintain a reasonable signal level. The PGA needs to have smaller than 74dB Total Harmonic Distortion (THD) over the signal spectrum. To accommodate large input signal swing, attenuation of signal may be required [1]. The PGA needs to maintain its high linearity and low noise over the entire signal bandwidth as well as the gain range. Variable MOS transconductors are used to realize high speed PGAs in the disk drive applications.[2][3]. Non linear characteristics of the trans conductors limit the linearity of PGA. Although closed loop architectures with resistornetwork feedback can achieve high linearity [4], earlier designs show tradeoff among bandwidth, gain range, linearity and power dissipation.
This paper describes a programmable current gain stage with a negative feedback loop for a two stage low impedance op amp. Section II analyzes various PGA architectures which serve as a background. The new PGA architecture is described in Section III. Section IV shows the experimental results, and conclusions are given in Section V.

BACKGROUND
Various topologies used in feedback loop for varying the gain discussed later are current divider[8], source coupled pair topology, degenerative resistor and resistor network topology. Figure 1(a) is a current divider, Control voltage Vc is used to determine the dividing ratio. Realization of linearindB gain setting is difficult due to the quadratic characteristic of the current divider. The input transconductance limits the linearity which generates Ii. The transconductance of the source coupled pair in Figure 1(b) can be changed by varying the bias current of the transistors [5]. The gain and the input referred noise of the circuit are proportional to gm and reciprocal of sqrt(gm) of the input transistors, respectively.
When the input signal is weak, the large bias current is needed to obtain large gain and low noise performance. When the input signal is large, the low biasing current can degrade the linearity. Figure 1(c) shows a topology with resistive array gain stage for an opamp. In this technique generation of linear variable analog control resistors are difficult. However, it is popular in digital controlled VGA[3]. Figure 1(d) uses high gain current mode amplifier with low impedance and the gain is varied by changing R1 and R2. In this topology Rf1 and Rf2 are fixed resulting in constant closed loop bandwidth throughout the gain range.
Figure 1. Different topologies for gain variation.
To facilitate digital gain control variable resistors are realized using the linear resistors in series in figure 2a with MOSFET switches biased in triode region. Similarly implementing feedback resistors in parallel fashion with MOSFET switch as shown in figure 2b.
Figure 2. MOSFET switched resistive feedback.

ARCHITECTURE OF PROGRAMMABLE CURRENT GAIN AMPLIFIER
The implementation of Programmable Current Gain Amplifier uses an op amp and a negative feedback loop with current mirror and array of switched MOS resistors. The op amp has a two stage structure and serves the purpose of reducing the input impedance of the amplifier. This also reduces the variations of input impedance for different input signal currents to minimize the signal distortion and to improve the linearity.
Figure 3: Programmable current gain amplifier
The feedback consists of multi staged current mirror. The input impedance of the gain amplifier mainly depends on the transconductance value of feedback transconductor M3 which is operated in the subthreshold region. Thus the input impedance can be formulated as
Where A is the gain of op amp and gm is the transconductance of M3. Also we have
Where I is the current in M3, n is weak inversion slope factor and UT is the thermal voltage.
Since gm is directly proportional to I, resistance Rin is inversely proportional to the current through the MOSFET M3. From figure 3, the impedance is proportional to the sum of biasing current Ibias and input current signal flowing into the programmable current gain amplifier Iin. Hence Rin can be shown as
The switches S1 and S2 are used to vary the number of MOS devices connected parallel to the current mirror, thereby varying the gain. When the switch in each branch turns on, the parallel connection number of NMOS and PMOS is increased and current gain is reduced. When the switches turn off, the current gain is increased. Using two switches, the current gain can be varied in 4 steps.
Figure 4. Equivalent circuit (a) when S1 and S2 both are OFF, (b) when S1 is OFF and S2 is ON, (c) when S1 is ON and S2 is OFF (d) when both S1 and
S2 are ON
The current gain of the PGA depends on the MOS size ratio. Depending on the values of switches S1 and S2, the gain can be varied in 4 steps and the equivalent circuit for each is shown is Figure 4
III. SIMULATION RESULTS
The simulation results in Figure 5 show variation in current amplification ratio for different switch configurations. By using 2 switches, 4 step variation in current gain is obtained. For further variation in current gain, we can use more switches and more parallel branches. For example, 3 switches can be used to vary the gain in 8 steps.
100.00
Gain (dB)
75.00
50.00
25.00
0.00
1 2
4
3
2
1
1: S1 OFF and S2 OFF 4 3
2: S1 OFF and S2 ON
3: S1 ON and S2 OFF
4: S1 ON and S2 ON
ACKNOWLEDGMENT
We would like to extend our gratitude to Dept of Electronics and Communication, BMSCE. We would also like to thank our parents for all their encouragements
REFERENCES

I. Mehr, P. C. Maulik, and D. Paterson, A 12bit integrated analog front end for broadband wireline networks,IEEE J. SolidState Circuits, vol. 37, pp. 302309, Mar. 2002.

R. Gomez and A. Abidi, A 50 MHz CMOS variable gain amplifier for magnetic data storage systems,IEEE J. SolidState Circuits, vol. 27,pp. 935939, Dec. 1992.
10.00 100.00 1.00k 10.00k 100.00k 1.00M 10.00M
Frequency (Hz)
Figure 5: Current gain variation
V. CONCLUSION
PGA using amplifier with low input impedance and resistornetwork feedback can achieve constant bandwidth and high linearity. The current gain is varied by controlling the input switched MOSFETs. Using more switches, large combinations of gain can be achieved. This can be implemented in many small signal acquisition systems with low distortions.

R. Harjani, A lowpower CMOS VGA for 50 Mb/s disk driv read channels, IEEE Trans. Circuits Syst. II, vol. 42, pp. 370376, June 1995.

J. Guido, V. Leung, J. Kenney, J. Trackim, A. Agrillo, E. Zimany, andR. Shariatdoust, Analog front end IC for category I and II ADSL, in Symp. VLSI Circuits Dig. Tech. Papers, 2000, pp. 178181.

P. Orsatti, F. Piazza, and Q. Huang, A 71MHz CMOS IFbaseband strip for GSM,IEEE J. SolidState Circuits, vol. 31, pp. 104108, Jan. 2000.