 Open Access
 Total Downloads : 1069
 Authors : P.Veeramanithangam , P.Ganesh , R.Kalaiarasi , T.Manokaran
 Paper ID : IJERTV1IS8007
 Volume & Issue : Volume 01, Issue 08 (October 2012)
 Published (First Online): 29102012
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Power Stress Reduction In SingleStage Power Factor Correction By AC/DC Fly Back Converter
P.VEERAMANITHANGAM1, P.GANESH2, R.KALAIARASI3, T.MANOKARAN4
1, 2, 3 PG Scholar II year PED, Department of Electrical and Electronics Engineering, Sri Subramanya College of Engineering and Technology,
Sukkamanaikanpatti Palani, Dindigul, India.
4Department of Electrical and Electronics Engineering, Sri Subramanya College of Engineering and Technology, Sukkamanaikanpatti, Palani, Dindigul, India.
Abstract
This paper discusses the major issues that exist in the singlestage ac/dc converters with power factor correction (PFC) and presents a novel converter based on a quasiactive PFC scheme. Two additional windings wound in the transformer of a conventional dc/dc fly back converter are used to drive and achieve continuous current mode operation of an input inductor. In addition, direct energy transfer paths are provided through the additional windings to improve the conversion efficiency and to reduce the dc bus capacitor voltage below 450 V for universal line applications. The proposed converter can be easily designed to comply with IEC 6100032 Class D requirement and to achieve fast output voltage regulation. By properly tuning the converter parameters, a good tradeoff between efficiency, dc bus capacitor voltage stress, and harmonic content can be achieved. Operating principles, analysis, and experimental results of the proposed method are presented.

Introduction
RECENTLY, many highfrequency active power factor correction(PFC) topologies and current shaping techniques for ac/dc converters have been developed
[1] to meet standards such as IEC 6100032. In conventional converter design, a two stage scheme was usually employed insimultaneously performing PFC and fast output regulation by using two independentcontrollers and optimized power stages. However, the cost and complexity of the converter increases with the increased component count. A costeffective solution known as a singlestage PFC (S2PFC) converter was developed, in which the PFC stage and the dc/dc converter are combined into one stage [2][4]. These S2PFC converters usually use a boost converter to achieve PFC with discontinuous conduction mode (DCM) operation. A detailed review of the S2PFC topologies using DCM boost converter is presented in [3].Some other integrated S2PFC schemes are also implemented using DCM buckboost or buck converter [5][9]. Generally, the power factor (PF) of a conventional twostage converter is much higher than the singlestage scheme. However, the input current harmonics of S2PFC converters still can meet the regulatory standards. Although the singlestage scheme is attractive in lowcost and lowpower applications due to its simplified power stage and control circuit, major drawbacks such as low efficiency, high dc bus voltage stress, and working in DCM of the input PFC stage still exist. The DCM operation gives a lower total harmonic distortion (THD) of the input current compared to the continuous current mode (CCM). On the other hand,the CCM operation yields a slightly higher efficiency compared to the DCM operation [19].
To overcome the drawbacks of the singlestage scheme, several converters with input currentshaping have been presented [10], [11], in which a high frequency ac voltage source is connected in series with the rectified input voltage to shape the input current. The variable switching frequency control technique that
is proposed in [12] can reduce the dc bus voltage stress. The method is unable to suppress the dc bus voltage below 450 V for universal line applications (100240 V ac), and it complicates the design of the inductive components due to the widerange switching frequency operation. Some alternative designs using additional coupled feedback windings are introduced in [13][20], wherein the dc bus capacitor voltage is reduced below 450 V. Nevertheless, the feedback windings also induce a dead angle in the input current, hence resulting in a high line current distortion. The coupled feedback winding concept is also implemented using a center tap transformer and a synchronous rectifier to improve the PF and efficiency [21].The converter is operated at the boundary of the DCM and CCM using a variable frequency controller to reduce theswitching turnon loss. In addition, a dead angle still exists in the input current wave form.The topologies proposed in [22] and
[23] overcome the dc bus capacitor voltage stress using the parallel PFC concept.In this paper, a new quasiactive PFC circuit is presented. The circuit is based on adding two auxiliary windings coupled to the transformer of a cascaded dc/dc flyback converter. The PFC cell is placed between the input rectifier and the lowfrequency filter capacitor, capacitor, which is a similar approach to the conventional activePFC design but without an active power switch. Since the dc/dc converter is operated at high switching frequency, the auxiliary windings produce a highfrequency pulsating source such that the input current conduction angle is lengthened and the inputcurrent harmonics is reduced. Furthermore, the highfrequency pulsating source requires smaller size components, resulting to a lower cost. The input inductor current can be designed to operate in CCM. By properly designing the converter parameters, a good tradeoff between efficiency, dc bus capacitor voltage stress, and harmonic content can be achieved. The structure and operating principles of the proposed converter are presented in Section II. The design example and the experimental results are presented in Section III. Section IV gives the conclusion.

Proposed QuasiActive PFC Circuit
The proposed quasiactive PFC circuit is discussed in this section. As shown in Figure 1, the circuit is comprised of a bridge
Figure 1.Proposed quasiactive PFC circuit diagram.
Figure 2. Input inductor current IL4 illustrating its conduction modes during half line current period.
rectifier, a boost inductor L4, a capacitor C3, an intermediate dc bus capacitor C1, and a discontinuous input current power load (a DCM fly back converter in this case). Two auxiliarywindings L3 and L5 are added to the primary side of the transformer in order to shape the input current. In the proposed quasiactive PFC scheme, the dc/dc converter section is not directly involved in the PFC; it simply offers a driving power by applying a series of discontinuous current pulses. Compared to the circuit reported in [35], the proposed circuit shown in Figure 1 is different in two ways: the dotted convention of the third winding (L3) of the fly back transformer is reversed, and an additional winding L5 is inserted. If the third winding (L3) is wound such that the dotted terminal of L3 is similar to L1 and L5 and opposite to the secondary winding L2, the circuit operation and analysis will be fundamentally different. Consequently, these changes will bereflected mainly on the input inductor L4 which operates in CCM/DCM, as shown in Figure 2.Compared to [35], the input inductor alwaysoperates in DCM. Although the DCM gives lower THD of the line current, however, CCM operation required a smaller EMI filter, and the harmonic content of the line current can still be maintained below the IEC 6100032 Class D requirements. Furthermore adding the winding L5 in the proposed circuit offers more flexibility in maintaining the dc bus capacitor voltage VC1well below 450 V for universal line flexibility in maintaining the dc bus capacitor voltage VC1well below 450 V for universal line applications . s a result, the voltage stress across the power switch can be reduced. In addition, two direct energy transfer paths are provided by the two feedback windings, which can improve the conversion efficiency. When the switch is
turned on, part of the energy
Figure 3. Equivalent circuits for the three stages of operation of the proposed pfc circuit
.rom the input inductor is directly transferred to the transformer. When the switch is turned off, part of the energy.from the input is transferred to the secondary output capacitor through the winding L3. As a result, the conversion efficiency is expected to remain high, as achieved in Furthermore, the size of the capacitor C3 in series with the winding L3 is smaller
To simplify the analysis, the following assumptions are made.

All semiconductor components are ideal.

The power transformer is ideal (no leakage flux). 3)The voltages across the capacitors are constant.
4) The switching frequency is much higher than the line frequency. Therefore, the input voltage is constant during a switching cycle.

Operation stages
This section presents the principle of operation of the proposed PFC circuit. A typical input inductor current produced by the circuit is shown in Figure 2. It can be seen that, during a half cycle of the supply, the waveform of the input current iL4 always has two parts, namely, the DCM and CCM parts.When vin < VC3, the current iL4 is low, and hence, the input inductor L4 operates in DCM. With the increase of the input voltage such that vin VC3, the inductor current increases and becomes continuous (CCM). At steady state, the topology has three operating stages, as shown in Figure 3. The key switching waveforms for bothCCM and DCM parts are shown in Figs. 4 and 5, respectively. Stage 1 (tot1): At t = to, the switch (SW) is turned off, and diode D1 is reverse biased due to (VC1 + VL5), which is always higher than vin. The inductor L4 absorbs energy from the input source, and therefore, the current iL4 is increased linearly. During this stage, the capacitor C3 is charging. Meanwhile, diode D2 is forward biased, and the load absorbs energy from both the magnetizing inductor through primary winding n1 and the input voltage through the
auxiliary winding n3. Therefore, there is a DPT from the input source to the load during this
Figure 4. Key switching waveforms of the proposed PFC with CCM operation
Figure 5. Key switching waveforms of the proposed PFC with DCM operation.
period. As a result, the efficiency is improved. This stage ends when the secondary current i2 becomes zero at (t = t1)
Stage 2 (t1t2): During this stage, the switch (SW) and both diodes D1 and D2 are turned off. The input current continues to flow through the circuit formed by vin, L4, L3, and C3. The capacitor C3 is still charging at this stage. The current iL4 slightly decreases when vin
< VC3 (for DCM part) and is constant when vin VC3 (for CCM part).This stage ends when the switch (SW) is turned on at t = t2.
Stage 3 (t2t3): At t = t2, the switch (SW) is turned on, and diode D1 is conducting. Therefore, the stored energy in L4 and C3 is transferred to the primary windings n1 and n5, so more energy is stored in the magnetizing inductor of the transformer. Hence, the primary winding current increases linearly. In addition, when vin < VC3 (DCM part), the dc bus capacitor C1 discharges its energy to the transformer primary winding. Note that, because vin is low, the current iL4 will decrease to zero (DCM) before the switch is turned off. Once iL4 = 0, the capacitors C3 and C1 continue to supply the energy to the primary windings of the transformer. However, when vin VC3 (CCM part), the input voltage is high enough such that it can provide most of the energy to the primary windings n1
and n5 and also to the bulk capacitor C1. Therefore, when the switch (SW) is turned on, the current difference between iD1 and i1 will charge the dc bus
4 = [(3 A
2
4
301(1 +
)+(3 5 ) d (d
+d )] (7)
capacitor C1.At t = t3, the switch (SW) is turned off again, and the primary current i1 decreases to zero. Therefore, D1 is turned off due to (VC1 + VL5), and the output diode D2 is forward biased. The current i3
2 1 1 3 2 3
where A=d1 d1 + d2 + d3(d2 + d3)]
Substituting for 30from (2) into (7) yields
reverses its direction again, where it is equal to iL4, and
= [(
v
A+3 5 )
(B)] (8)
the switching cycle repeats.
4
24
3
in 1
1

SteadyState Analysis
The voltage conversion ratio of the proposed converter can be estimated from the voltsecond balance on inductances and theinputoutput power balance. Consider the waveforms shown in Figure (5)
Where B=d3 d1 + d2 + d3(d2 + d3)
In Figure 5, it can be seen that d1 + d2 = 1 d3
A=d1 1 d3 + d3(d2 + d3), and
B=3 1 3 + 3(2 + 3).
The discharging time 3 can be found from (1) as
From the voltsecond balance on L4, it yields
( +30 3)1 = 3 2 + (1(1 + 5
3
= ( 3 ) 1 +2 +3 0 1 .
1
1 1+ 5
or
) ) 3(1)
1
3 =
( 3 ) 13 +( 3 1 3
whered1 is the ontime of the output diode D2, d2 is the
1
1 1+ 5
(9)
time period when the switch (SW) and both diodes D1 .
1
and D2 are turned off, and d3 is the ontime of the switch (SW).
From the voltsecond balance on L3, it yields
= ( 1 + 5 = ( 3 )
Therefore , for the DCM part of the input current 4, 3
3. At the boundary condition
3 = 3 (10)
3 0 1
1
1
or
3 3
1
1 3
Substituting (10) into (9) yields
301 = (1 3 3 = ( 3 5 )13(2)
1
From the voltsecond balance on L1(Lm)
()= = 3. (11)
Substituting (10) and (11) into (8) yields the input current atthe boundary condition
=
(3)
= [ + ]
3 0 1
1 3
From (2) and (3), we can derive
3=1+5 – 3 = 3 5 3 = 1 (4)
=
(
3
)
1
1
1
1
3
= (
= ( 1 –
24
Now, the average inductor current
1)2 (1 d1). (12)
3 d3
4
=
+
Substituting (4) into (12) yields
24
3 3 0
1 1 2
5
in = 4 = 3 35 13
+ 1 1 + 3 2
24
1 3 5
1
1
+ 3 (5)
wherevin = Vmsin(t). The average input power is given by
From (2), we have
1 3 1
= + ( 3 5)
Pin
=
0
1
2
4 =
[(3 30 1(1 + 2+(1 +
= 3 35 (14)
24
44 13+5
1
())Ã—3(2 +3)] ()
whereVmis the peak value of the input voltage. The averageoutput power of the DCM flyback converter
[26] is given by0
2
= 1 2 (15)
2 3
In a half line cycle, the input energy is equal to the outputenergy at steady state such that Pin = Po. Therefore, the dc buscapacitor voltage is written as
=
3 5
(16)
+Ã—(
1 )
From (16), it can be seen that the dc bus voltage VC1 is independent from the load changes, and it is a function of theinductance values, turn ratios, and inputvoltage. Therefore, high voltage stress can be overcome byproperly designing the ratio of the inductance ratio Lm/2L4 and the number of turns n1, n3, and n5.


Design Example and Experimental Results
The performance of the new quasiactive PFC circuit shown in Figure 1 was designed and experimentally verified. The main design objectives of the proposed circuit can be divided into two directions. First, it achieves low THD of the line current to comply with the IEC 6100032 Class D standard with a CCM operation of the input inductor (L4) as much as possible. Second, it limits the voltage stress of the dc bus capacitor VC1 below 450 V for a universal input voltage (100240 Vac). From the preceding analysis in Section II, assuming that the secondary winding n2 = 1, it is found that the number of turns (n1, n3, and n5) and the inductors ratio Lm/2L4 are the key design parameters. Specifically, the turns ratio (n3/n1) has a significant impact on both the quality of the input current and the dc bus capacitor voltage. The DCM flyback converter was designed for Vin,rms (100240 V), Vo = 50 V, and output power of 80 W, and the overall efficiency of 86% is assumed.The switching frequency is 100 kHz, and the maximum duty cycle is 0.45
Fig 6.Average input current waveform for a half line cycle and difference turns ratio(3)
1
Figure 7. Input voltage and current waveforms showing the effect of the numberof turns n5
Figure 8. THD of the input current as a function of the turns ratio (n3/n1).
Based on (8) and (9), Figure 6 shows the average input current waveform for a half line cycle as a function of the turns ratio (n3/n1) for an input voltage of 100 V. It is assumed that all of the other parameters are constant. It can be seen that, to reduce the dead angle of the input current and to provide a continuous current flow, the turns ratio (n3/n1) must be greater than or equal 0.5. In addition, the number of turnsn5 also affects the dead time of the input current, as shown in Figure 7. The higher the number of turns (n5) is, the bigger the dead time will be. Therefore, the turns ratio (n3/n1) and (n5) must also be selected such that the input current delay times (ta and tb) are approximately equal to zero. Figs. 8 and 9 show the calculated
Figure 9 Input PF as a function of the turns ratio (n3/n1).
Figure 10. Calculated dc bus capacitor voltage versus turns ratio (n3/n1) forVin = 240 V. (a) n5/n2 = 0.15. (b) n5/n2 = 0.3.
THD and PF of the input current as a function of the turns ratio (n3/n1) for input voltages of 100 and 240 V. It can be observed that the turns ratio (n3/n1) controls the quality of the input current. The higher the turns ratio is, the lower is the THD, and the higher is the PF obtained. However, based on (16), a higher
Figure 11. Calculated dc bus capacitor voltage versus turns ratio (n3/n1) for Vin = 100 V.
Figure 12. Turns ratio n5/n2 withn3/n1 = 0.6. (a) Vin = 240
V. (b) Vin = 100 V.
turns ratio (n3/n1) means a higher dc bus capacitor voltage(VC1) stress. Figure 1012 show the relationship between the dc bus capacitor voltage and circuit parameters, turns ratio (n3/n1) and (n5/n2), and inductance ratio (k = Lm/2L4) for input
Figure 13. (a) Measured input voltage (Vin; 100/Div) and filtered input current(Iin; 1 A/Div) for Vin = 100 V. (b) Corresponding harmonics content(THD = 22%).
Voltages of 240 and 100 V, respectively. It is shown in Figs. 10 and 11 that, for a given value of k and n5, if the turns ratio n3/n1 >0.6, the relationship between the dc bus capacitor voltage and the turns ratio becomes nonlinear, and a small change in the turns ratio results in a very high capacitor voltage stress. Therefore, a tradeoff between the input current quality and the dc bus capacitor voltage must be made. For a universal input voltage, the maximum capacitor voltage must be limited to 450 V. Therefore, in Figs. 6 and 811, for the range of k = 12 and for a turns ratio value of n5/n2. Finally, Figure 12 shows the relationship between the turns ratio n5/n2 and the dc bus capacitor voltage (VC1)
for a turns ratio n3/n1 = 0.6. It can be seen that, for given values of k and turns ratio (n3/n1), a higher turns ratio (n5/n2) leads to a lowercapacitor voltage (VC1). However, a higher turns ratio (n5/n2) may induce a dead time in the input current, as shown in Figure 7. Therefore, k = 2and n3/n1 = 0.6 and n5/n2 = 0.2 are selected in this design, which ideally give VC1 408 V for Vin = 240 V. However, practically, the voltage VC1 could be lower due to unavoidable circuit losses. In addition, a capacitor with a voltage rating of 450500 V could be used since it is available in the market. The conventional fly back transformer is constructed with the number of turns n1 = 46, n2 = 15, n3 = 28, and n5 = 3and magnetizing inductance Lm = 200 H. The input inductor L4 = 50 H. The capacitor values are selected as C1 =
Fig 14. Measured input voltage (v in ;100/div) and filtered input current(b)corresponding harmonic current
Fig 15. Measured waveforms for Vds (switch voltage) 47
F/500 V and C2 = 2Ã— 470 F.
Assuming thatVc3 = 100 V, Pin,min = 15 W, Vrms
= 240 V (worst cases cenario) , t = 10 ms (half of the half line period for discharge),and then C3 6.25 F. Therefore, C3 = 4.7 F/450 V is selectedsuch that VC3 follows the input voltage, and the capacitor has to be discharged much faster than the 50Hz input. Based on the aforementioned design example, the converter was built using the following components: the diode bridge
= KBU8J, D1 = MUR1560, D2 = MUR1510, and SW
= SPW22N60C3. Figure 13(a) shows the measured waveforms of the input voltage and input current for a100Vac input voltage. The harmonic content of the input current compared to Class D regulation
standard is shown in Figure 13(b). Similarly, Figure 14(a) and (b) shows the
Figure 16. Measured waveforms for Vds (switch voltage),
IL4, and ID2. (a) CCM operation. (b) DCM operation
Fig 17. Transient response for a step load change measured input voltage, input current, and harmonic content forVin = 240 V. It can be observed that the standard specification IEC 6100032 Class D is easily fulfilled. Figure 15 shows the measured waveforms of the rectified input voltage, capacitor voltage C3, dc bus voltage VC1, and input inductor currentiL4. It can be observed that, when vin < VC3, the inductor current is in DCM, and when vin = VC3, the current is in CCM. Figure 16(a) and (b) shows the key waveforms of the switch voltage (Vds), input inductor current IL4, and output diode current ID2 for both operation modes, i.e., CCM and DCM, respectively. Figure 17 shows the transient response of the converter for astep change of load from 50% to 100%. As can be observed, afast dynamic response is obtained. Figure 18 shows the measured efficiency of the converter for a range of loads and three different input voltages. It can be observed from the figure that the efficiency of the converter is above 85% for higher loads.
Figure 18.DC bus capacitor voltage VC1 versus load power for different inputvoltages.
Figure 18 shows the measured dc bus capacitor voltage VC1 fora range of load and input voltage variations. It can be seen that the capacitor voltage can be maintained below 450 V by properly designing the number of turns (n1, n3, and n5) and the inductors ratio (k).Finally, Table I summarizes the comparison of several singlestage ac/dc converters presented in [13] [15], [19], [21], [25], and [32] with the proposed converter in terms of circuit implementation and performance. The main advantage of the proposed converter over the topologies presented in Table I is that the proposed converter presents a highquality CCM input current with the lowest THD = 22%. Usually, in a singlestage converter, there is always a tradeoff between the CCM operation and THD of the line current, where, by the CCM operation, it usually causes high harmonic current. Furthermore, in all ofthe published approaches listed in the table, increasing the turns ratio of Nau/Npcan reduce the input PF by inducing a dead angle in the line current, whereas in the proposed converter, the higher the turns ratio n3/n1 is, the higher is the PF. However, the turns ratio cannot be arbitrarily large because of the maximum limit of the dc bus capacitor voltage. The maximum dc bus capacitor stress is VC1 = 400 V for the proposed converter, and it can be maintained always below 450 V by properly selecting the number of turns (n1, n3, and n5) and the inductors ratio Lm/L4. Although the dc bus voltage stress in the circuits presented in [14], [15], [19], [21], and [25] is lower than 400 V, those solutions penalized the current qualitywith high THD. The proposed converter can also be designed to achieve a dc bus voltage stress which is lower than 400 V,but the THD of the input current will increase slightly due toa small dead angle in the input current waveform. Therefore
,the design parameters are optimized to maintain a low THDwithout any dead angle and tolimit the capacitor voltage stress below 450 V.In addition, the proposed converter achieves ahighefficiency (>82%) due to the DPT paths provided by thetwo auxiliary windings.conversion efficiency in [15] and[21] is almost.similar to the proposed converter. Nevertheless,their harmonic currents are considerably higher, and they alsorequire a variable frequency control.

Conclusion
In this paper, a new quasiactive PFC circuit has been presented.In the proposed scheme, auxiliary windings are addedto the transformer of a dc/dc DCM flyback converter. Sincethe dc/dc converter is operated at high switching frequency, theauxiliary windings produce a highfrequency pulsating source such that the input current conduction angle is lengthened and the input current harmonics is reduced. The input inductor can operate in DCM+CCM. The singlestage PFC circuit has high efficiency when it operates in CCM. Hence, by properly designing the converter parameters, a high efficiency can be obtained while maintaining the total current harmonic content well below the IEC 610003
2 Class D standard specifications. The operating principles, analysis, and experimental results ofthe proposed method have been presented.
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