- Open Access
- Total Downloads : 16
- Authors : Neethu M, Lincy K
- Paper ID : IJERTCONV3IS12025
- Volume & Issue : NCICCT – 2015 (Volume 3 – Issue 12)
- Published (First Online): 30-07-2018
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License: This work is licensed under a Creative Commons Attribution 4.0 International License
Performance Enhancement of Complex Multiplier using Vedic Sutras
Department of Electronics and Communication Engg, Jawaharlal College of Engineering Technology, Palakkad, Kerala, India
Asst Professor, Dept of ECE,
Jawaharlal College of Engineering Technology, Palakkad, Kerala, India
Abstract Vedic mathematics is the ancient system of mathematics based on simple rules and principles. It reduces the complexity in current system of mathematics to very simple one. It works similar to how a human mind works. Vedic mathematics has a lot of algorithms to compute complex mathematical operations. Now a day, application of Vedic Mathematics got increases in the field of applied electronics. Among the arithmetic operations multiplication is an important arithmetic which is used frequently. Its application involves convolution, digital signal processing, Fast Fourier Transform (FFT). All the signal and data processing operations involve multiplication. Speed is one of the important constraints in the multiplication operation. Increase in speed can be achieved by reducing the number of steps in the computation process. The speed of multiplier determines the efficiency of such a system. Multipliers based on Vedic Multiplication reduce the delay, memory usage and power consumption. This paper deals with the application of logical algorithms mentioned in Vedas to modify the functioning of conventional multiplier. The simulation of two relevant sutras is done using ModelSim software and its performance analysis using Xlinix software.
Index Terms Multiplier, Vedic Sutras, Nikhilam sutra, Urdhava tiryagbhyam sutra
It may be defined the paper title Performance Enhancement of Complex Multiplier using Vedic Sutras, as an effort to analyze how a multiplier can be improved in terms of operational speed, memory usage and power consumption by accompanying the logical algorithms of different Vedic sutras and to quantify it by comparative performance analysis with the conventional multiplier.
Vedic mathematics is a part Adharva Veda, the last of four Vedas .The word Vedic is derived from the word Veda. Which means the fountain-head and illimitable store-house of all knowledge. Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja (1884- 1960) introduced Vedic Mathematics. Swamiji developed sixteen sutras (formulae) and thirteen Upa-sutras (sub formulae) after extensive research. Vedic mathematics is not a mere mathematical wonder, it is pure logical. These Sutras along with their brief meanings are enlisted below.
Ekadhikina Purvena By one more than the previous One
Nikhilam Navatashcaramam Dashatah All from 9 and last from 10
Urdhava-tiryagbhyam Vertically and crosswise
Paraavartya Yojayet Transpose and adjust
Shunyam Saamyasamuccaye When the sum is same that sum is zero
(Anurupye) Shunyamanyat If one is in ratio, the other is zero
Sankalana-vyavakalanabhyam By addition and by subtraction
Puranapuranabyham By the completion or non- completion
Chalana-Kalanabyham Differences and Similarities
Yaavadunam Whatever the extent of its deficiency
Vyashtisamanstih Part and Whole
Shesanyankena Charamena The remainders by last digit
Sopaantyadvayamantyam The ultimate and twice penultimate
Ekanyunena Purvena By one less than the Previous one
Gunitasamuchyah The product of sums is equal to the sum of products
Gunakasamuchyah The factors of sum is equal to the sum of factors.
SUTRAS OF INTEREST
Among the sixteen sutras of Vedic mathematics three are dealing with multiplication. One is exclusively to find squares. The rest two are discussed here. Urdhava tiryagbhyam sutra is the only one yet tried by any research work for the similar studies. The adaption of both together is supposed to be a challenge in this work. The two sutras of interest are briefed below.
Nikhilam Navatashcaramam Dashatah Sutra
This sutra by name means, All from 9 and the last from 10. The Nikhilam Sutra can be used to multiply any number, but is very effective when applied to numbers nearer to the powers of 10. The procedure of multiplication using the Nikhilam involves minimum number of steps, space, time saving and only mental calculation. The nearest 10n of both multiplicands is taken as the base of operation. The numbers taken can be either less or more than the base considered. The
difference between the number and the base is termed as deviation. Deviation may be positive or negative. Let N1 and N2 be two numbers near to a given base in powers of 10, and D1 and D2 are their respective deviations from the base. Then N1 x N2 can be represented as
Consider two n bit numbers X and Y. K1 and K2 are the exponent of X and Y respectively. X and Y can be represented as:
X = 2 K1 Â± Z1 (1)
Y = 2K2 Â± Z2 (2)
Y * 2K -K = (2K Â± Z ) (2K -K )
1 2 2 2 1 2
1 2 2 1 2
1 2 2 1 2
= (2K2 * 2K -K ) Â± (Z * 2K -K )
= 2K Â± Z * 2K -K
1 2 1 2
X*Y * 2K1-K2 = X * (2K1 Â± Z2 * 2K1-K2) (4)
After substitutions and solving the equation becomes, P= XY = X*Y*2K1-K2 / 2K1-K2
= 2K (X Â± Z * 2K -K ) Â± Z Z
2 2 1 2 1 * 2
Fig .1: Formulation of Nikhilam sutra.
If R. H. S. contains less number of digits than the number of zeros in the base, the remaining digits are filled up by giving zero (or zeroes) on the left side of the R. H. S. If the number of digits is more than the number of zeroes in the base, the excess digit (or digits) is to be added to L. H. S. of the answer.
E.g. 1: 986 X 989 = 975154, here nearest power of 10 is 1000, which is taken as base.
= (Number Base)
(986+ -011) or
(14 x 11)
E.g. 2: 994 X 988 = 982072. Base is 1000
= (Number Base)
(994+ -012) or
(6 x 12)
1) ARCHITECTURE OF NIKHILAM MULTIPLIER
The mathematical expression for the "Nikhilam Navatascaramam Dasatah" algorithm is given below. The Nikhilam algorithm is divided into three fundamental parts namely, (i) Base Selection Unit (ii) Exponent Determinant (iii) Complex Multiplier Unit.
Fig. 1: Architecture of Nikhilam Multiplier
Urdhava Tiryagbhyam Sutra
Urdhava tiryagbhyam is the general formula applicable to all cases of multiplication and also in the division of a large number by another large number. It literally means Vertically and crosswise. This sutra is useful for the multiplication of two decimal numbers also. Logic is explained via two examples.
E.g. 1: (48 X 47) = 2256
Step (i): (8 X 7) = 56; 5, the carried over digit is placed below the second digi.
Step (ii): (4 X 7) + (8 X 4) = 28 + 32 = 60; 6, the carried over digit is placed below the third digit.
Step (iii): (4 X 4) = 16; Write it completely. Step (iv): Respective digits are added.
The above described procedure can be adapted to any number of digits.
Since there is a parallel generation of the partial products and their sums, the processor becomes independent of the clock frequency. Thus the multiplier will require the same amount of time to calculate the product and hence is independent of the clock frequency. The advantage here is that parallelism reduces the need of processors.
URDHAVA 2 X 2 MULTIPLIER
Let us consider two data inputs, each of length 2 bits; say A1, A0 and B1, B0. The output can be of four bit length, say P3, P2, P1, and P0.
Fig. 3. Block diagram of Urdhava Sutra Multiplier
In Vedic multiplier, P0 is obtained by vertical multiplication of data bits A0 and B0, P1 is obtained by addition of crosswise bit product i.e. A1B0 and A0B1 and next P2 is obtained by adding the product vertical data bits A1 and B1 with the carry generated from the previous addition during P1. P3 is the nothing but carry generated in calculation of P2. This part is the operation of 2×2 multiplier block.
Fig. 4: Circuit diagram for 2bit Urdhava Sutra Multiplier
URDHAVA 4 X 4 MULTIPLIER
As number of bits increases in input, a small modification is required. Divide the total number of bits of each input into two equal parts .Now let us design 4×4 multiplications with inputs as A3A2A1A0 and B3B2B1B0. The result obtained by multiplication the two inputs are represented as P7P6P5P4P3P2P1P0. Let us divide the inputs A and B into two equal parts as mentioned above, say A3A2 and A1A0 for input A and B3B2 and B1B0 for input B. Take two bits at a time by using the basic principle of Vedic multiplication and using 2 bit Vedic multiplier block. The final result is obtained by adding the outputs of 2Ã—2 bit multipliers in a specific way. Hence three ripple carr y adders are required at final stage; is given in Figure 5. By observing the algorithm, it is clear that 4 x 4 bit multipliers are designed from 2 X 2 bit blocks. The design includes 4 2 x 2 multipliers and 3 Ripple Carry Adders.
Fig. 5. 4X 4 Urdhava multiplier
Since the Nikhilam sutra is simple only when the numbers to be multiplied as nearer to the bases, that faster formulation is supposed to limit for such numbers. And all other multiplication may be done using Urdhava sutra formulation.
It is not found the ModelSim software being used in this kind of projects. The ModelSim software is licensed to support designs written in VHDL. Xilinx ISE (Integrated Software Environment) is a software tool produced by Xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize their design. Hence the simulation using ModelSim and performance analysis using Xlinix, a much powerful tool, are proposed.
SCOPE OF THE WORK
Various researchers are ongoing around the world to adapt the Vedic Mathematics into modern computing technology. Yet the researchers are based only on one sutra. In this paper collaboration of two sutras i.e., Urdhava Tiryagbhyam Sutra
and Nikhilam Navatashcaramam Dashatah Sutra are applied simultaneously for the performance enhancement of the multiplier. The performance analysis is done in xilinix software. The concept is that, the initial conditions are set at the start (say) at around 20% from the nearest base as the Nikhilam limit. If the inputs lie inside Urdhva limit, Urdhava based multiplier will perform the multiplication and if the inputs lie inside Nikhilam limit, Nikhilam based multiplier will perform the multiplication. This is extended for all higher order cases. This proposed architecture is aimed at achieving faster results. Also, when one multiplier is ON, the other is OFF.
RESULT AND DISCUSSION
The entire algorithm in this paper was simulated and their functionality was examined by ModelSim software. The performance Analysis was done using Xilinix Software.
CONVENTIONAL MULTIPLIER UNIT
Figure 6 shows the waveform of a conventional multiplier system. In this multiplier, two inputs are stored in the registers x & y. Both x& y are 8-bit registers. The register N represents a 8-bit register which has the same value stored in register y. The clock pulse is also given, so for every clock pulse, it will produces the multiplied values of two input numbers. The multiplied value is stored in the output register multi. The ModelSim simulated result is shown below.
Fig. 6. Conventional Multiplier Unit
NIKHILAM NAVATASHCARAMAM DASHATAH SUTRA MULTIPLIER
Figure 7 shows output of the proposed multiplier unit. The two 8-bit input numbers which has to be multiplied is stored in the registers A1& A2. The clock pulse is also given as an input. Here multiplying two 8-bit numbers, so the output will be a 16-bit binary number. The output is stored in a 16-bit register indicated by the name result. The intermediate
registers sub1, sub2 etc includes the various operation associated in order to reach the final output value.
Fig. 7. Nikhilam Navatashcaramam Dashatah Sutra Multiplier
I would like to thank my guide Ms. Lincy K, assistant Professor, department of electronics and communication engineering Jawaharlal college of engineering and technology Palakkad for her unwavering support and valuable suggestions.
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