Nonoverlapping Clock Generator with Optimized Falling/Rising EDGE Delay for Analog to Digital Converter Application

Download Full-Text PDF Cite this Publication

Text Only Version

Nonoverlapping Clock Generator with Optimized Falling/Rising EDGE Delay for Analog to Digital Converter Application

Neeraj Agarwal, Neeru Agarwal

ESS Department, NTHU, R.O.C

Abstract:-The non-overlapping clock signal generator are key elements in highly precise and switching sensitive circuits. An on chip non-overlapping clock signals are used to suppress the clock skew effect in highly noise sensitive circuits. A set of nonoverlap clock is designed and implemented from a global overlapping clock using 0.18 m CMOS technology. The proposed clock generator is designed to introduce delay in rising or falling edge of a clock pulse instead of giving equal delay in rising as well as falling edge of clock pulse. In this work, various methods and design consideration are discussed for implementation of nonoverlapping clocks. These nonoverlapping clocks have wide application in A/D converter, Phase-locked loop (PLLs), Switched capacitor circuit and Band gap reference circuit blocks etc. Inverter delay chain subblocks sizing for appropriate loading along with speed and area consideration is discussed in details. The multiple nonoverlapping clock configuration are designed and implemented for four nonoverlapping clocks output from a single overlapping off chip clock. This clock generator is designed for the 3.3 V 5 V supply voltage.

Keywords: Nonoverlapping clock generator, clock skew, pahse- locked loop (PLL)


In state of the art analog and mixed signal design circuits blocks, clock generators play an important role in various sub-blocks of the circuit. The precise sequenced clock signals are integral part of high frequency circuits. In principle, clock signals should have negligible rise and fall times, constant duty cycles, with absence of any clock skew. In practical circuit environment, clock signals show finite rise/fall time, clock skew and varying duty cycle. The effective suppression of clock skew is very much required. Otherwise, it may lead to serious issues in high frequency and switching sensitive circuits blocks. Like a noisy clock in the phase locked loop (PLL) may create unwanted jitter noise.[1]-[5]This jitter may remove the locking condition of PLL and severely affect on its performance and stability. On the other hand, nowadays switched capacitor circuits operation is highly depended on the accurate clocking sequence with predefined delay in the switching action.

Inclusion of nonoverlapping and predefined delay in rising or falling edge of the clock pulse in the switched capacitor circuits ensure the sufficient timing gap/delay between two switching sequence. So that, at a time only required signal becomes high and other remains in low condition. The propagation delay of the signal is defined by the no of

inverter chain and their sizing in the main non-overlapping circuit. There is always a trade off between large delay by using the large number of inverter chain and power consumption. A large inverter chain for delay also increases the chip area i.e costing. As an alternate, transmission gates are used with inverters to reduce the number of inverter stage.[2][6]-[10] The use of transmission gate along with inverter chain may reduce the delay in practicality as transmission gate provide parallel processing of input signal through pmos or nmos.

In analog and mixed signal designing, switched capacitor circuits are most commonly used circuit because of compact design and reliable circuit operation. Switched capacitor circuits are further used in analog to digital converter (ADC) block, dynamic comparators, filters, sample and hold circuits etc. In switched capacitor circuit, nonoverlapping clocks are applied to charge or discharge the capacitor to perform the sample and hold operation.[11]-[15] By using the unique sample and hold operation, switched capacitor circuits can perform the integration, multiplication and summer operation and transfer this circuit operation with a inbuilt amplification at the output.

A clocking sequence by arranging different number of inverters in inverter chain is shown in the Figure 1. We can create nano seconds delay by arranging multiple inverters in the inverter chain. In this kind of inverter chain, we can get equal delay in rising as well as falling edge of respective clock pulse. A customize delay only in the rising or falling edge is not possible by using the inverter chain delay clock only. By using odd no of inverters, a logic 1 to logic 0 clock pulse can be obtained and by using even number of inverter, a logic 0 to logic 1 clock pulse can be obtained. For getting, a large propagation delay, large number of inverters are required to include in the inverter chain. To include large no of inverters, it is required to have proper sizing inverters for high speed and low area achievement. It is shown below.


In a switched capacitor circuit, delay in particular clock edge is required. Clock edge timing circuit diagram

Fig 1. The Conventional inverter chain for generating clock sequence




Fig 2. Conventional inverter chain simulation graph

In above clock timing diagram pulse B is designed to appear its rising edge before the rising edge of pulse A and C. By using multiple inverters for pulse B, a propagation delay of approx. 10~60 ns can be obtained.


The proper sizing/aspect ratio of the inverters is important design parameter of conventional clock delay generator circuit to maintain the equal rise and fall time as well as to maintain the signal strength. An example is shown below for a four inverter chain aspect ratio.


overlapping clocks. These two non-overlapping clocks have equal delay for rising and falling edge of the pulse. To customize the delay in rising or falling edge of the pulse, we designed CKT2 circuit. It is shown in Figure 5.

These two nonoverlapping clocks out 3 and out 4 are obtained from CKT have opposite phase with no delay. As shown in the Figure 5, out 3 and out 4 further goes to two next sub-blocks. Each sub-block contains inverters and one transmission gate to produce desired delay in the falling or rising edge. A universal clock is applied to CKT1 and CKT2 for both circuit switching. In sub-ckt1, two inverters are inserted before out 5 to generate required delay in the falling edge. While the signal going for rising edge does not has any inverter delay.

After that we want to generate delay at the falling edge of S1, S2 switch. When clk is high the TG1 will on and at the same time TG2 will be off and will get the out 6 with no delay at rising edge. When clk will low TG2 will on and at the same time TG1 will be off. We will get out6 with delay at falling edge. We are using two TGs for out 6 because when clk is high, only TG1 will on and get out 6 with no delay at the rising edge. When clock will low, only TG2 will on and TG1 will be off and get the out 6 with delay at the falling edge. After combining these two outputs, we get a clock pulse out 6, which has a delay in falling edge and no delay in the rising edge, when compared with out 3. We can also generate a clock pulse without any delay in the rising or falling edge. Out 7 represents such clock pulse. For creating a



We know area of inverter =


desired rising or falling delay in the opposite clock out 4, it


= ln [ ]


For output load Cload = 1 pF

Cin1 = 7.5612 fF, Cg,tot = 5.7016 fF + 1.8596 fF

=> = ln [ ] => = ln(132.2541) 4.88


=> = (132.2541)1/4 = 3.39 3.4

goes in to sub-ckt 3 where two inverter chain is inserted before out 8 to produce delay in the falling edge. Out 4 rising edge has no delay and we want to generate delay at the falling edge of S4, S5 switch. When clk is high the TG1 will on and at the same time TG2 will be off and get the out 9 with no delay at rising edge. When clk will low TG2 will on and at the same time TG1 will be off and get out 9 with delay at falling edge. We are using two TGs for out 9 because when

A°=(wp1/wn1) A1=(wp2/wn2) A2=(wp3/wn3) A3=(wp4/wn4)

clk is high only TG1 will on and get out9 with no delay at the

in1 out1

out2 out3 out

rising edge. When clock will low









Fig. 3. Aspect ratio simulation for four inverter chain

0 (1) = 3 , 1 (2) = 10 , 2 (3) = 39 , 3 (4) =



1 1

2 3

3 10




This clock generator circuit is designed and implemented in 0.18m technology using HSPICE EDA tool. Mostly, nonoverlapping clock generator is designed and implemented by using an off chip overlapping clock. Here, we are generating four nonoverlapping clocks. In the proposed clock circuit, we can produce different delay in the rising or falling edge of clock pulse. This design is distributed in two sub blocks. (i) CKT1 (ii) CKT2 In CKT1, it is producing two nonoverlapping clocks of same frequency from a single


Fig. 4. CKT1 diagram












Output with delay at the falling edge

It is good to take minimum size inverters and transmission gate for the nonoverlapping clock design. The inverter delay can change the nonoverlapping period.









out7 Sub-ckt2







1 tg5







Out9 with delay



0 Sub-ckt3

Figure. 6 Simulated results of the nonoverlapping clock generator circuit



Fig. 5. CKT2 diagram



only TG2 will on and TG 1 will be off and get the out 9 with delay at the falling edge and after combining two waveforms, we get a clock pulse out 9 with a desired delay in the falling edge only. Sub-ckt 4 gives an opposite clock pulse out 10 without any delay in its rising or falling edge. A detailed simulation graph is shown in the following Figure () and Figure (). We can increase or decrease delay by using even number of inverter chain. For a large clocking system, sufficient buffer stages are also included to maintain the signal strength.


The nonoverlapping clock generator is simulated for different rise and fall delay in the clock pulse. Its simulation graph is shown in the Fig. 6. Further Fig. 7 and Fig. 8 shows the zoomed waveform with different delay in the rise and fall edges. We can increase or decrease customize delay by increasing the number of inverters or by optimizing the existing inverter size. Simulated delay is summarized as follows and shown in Fig. 7.

Out6 Out7 80.96 ps Rising delay Out9 Out7 -44.87 ps Rising delay Out6 Out9 36.09 ps Falling delay Out9 Out10 26.17 ps Falling delay

Fig. 7 Delay in rise/fall edge of nonoverlapping clock pulse

Fig. 8 Delay in rise/fall edge of nonoverlapping clock pulse

The clock generator rise and fall edge delay optimization simulation graph shows a flexible delay design circuit from fs to ps required for high frequency circuits. Proper size optimization of pmos and nmos aspect ratio and the

transmission gate size ensures smooth and desired delay introduction in the clock pulse sequence.


A non overlapping clock generator circuit to introduce and optimize the rise or fall edge delay in the clock pulse is presented in this work. This nonoverlapping clock circuit can be integrated in various high frequency circuits for 3.3 V to 5 V supply range. In addition to it, the output clock signals dissipate low power. The simulation results shows that a customized delay of few fs to ps can be introduced in the clock sequence sensitive circuit like switched capacitor circuit, phase-locked loops (PLLs) design.


  1. B. Razavi, "Design of Analog CMOS Integrated Circuits. McGraw -Hill, first edition 2002.

  2. P. E. Allen and D. R. Hollberg, CMOS Analog Circuit Design, Oxford University Press, second ed. 2002.

  3. 3. R. J. Baker, H. W. Li, and D.E. Boyce", CMOS Circuit Design, Layout, and Simulation. Institute of Electrical and Electronic Engineer, Inc. 1998.

  4. H. J. Hsu and S. Y. Huang, A low-jitter ADPLL via a suppressive digital filter and an interpolation-based locking scheme, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 1, pp. 165170, Jan. 2011.

  5. W. Chung-Yi and W. Jieh-Tsorng, "A background timing-skew calibration technique for time-interleaved analog-to-digital converters," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 53, pp. 299-303, 2006

  6. C. T. Wu, W. C. Shen, W.Wang, and A. Y. Wu, A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm, IEEE Trans.Circuits Syst. II, Exp. Briefs, vol. 57, no. 6, pp. 430434, Jun. 2010.

  7. X. Zhu, B. Zhang, Z. Li, H. Li, and L. Ran, Extended Switched- Boost DC-DC Converters Adopting Switched- Capacitor/Switched-Inductor Cells for High Step-up Conversion, IEEE J. Emerg. Sel. Top. Power Electron., vol. 5, no. 3, pp. 1020 1030, 2017

  8. Y. C. Shih and B. P. Otis, "An Inductor less DCDC Converter for Energy Harvesting With a 1.2-v Bandgap-Referenced Output Controller," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 12, pp. 832-836, Dec. 2011.

  9. X.-P. Yu, Y. Fang, and Z. Shi, 2.5 mW 2.73 GHz non- overlapping multiphase clock generator with duty-cycle correction in 0.13 m CMOS, Electron. Lett., vol. 52, no. 14, pp. 12611262, 2016

  10. A. Cervera, M. Evzelman, M. M. Peretz, and S. Ben-Yaakov, A High Efficiency Resonant Switched Capacitor Converter with Continuous Conversion Ratio, IEEE Trans. Power Electron., vol. 30, no. 3, pp. 13731382, Mar. 2015

  11. with wide correction range and high precision, Electron. Lett., 2014, 50, (11), pp. 792794

  12. S. Mondal and R. Paily, An efficient on-chip switched-capacitor based power converter for a micro scale energy transducer, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 63, no. 3, pp. 254258, Mar. 2016

  13. S. A. Zahrai et al., "Design of clock generation circuitry for high- speed subranging time-interleaved ADCs," 2017 IEEE International Symposium on Circuits and Systems (ISCAS),

    Baltimore, MD, 2017, pp. 1-4

  14. H. Chandrakumar and D. Markovic, A high dynamic-range neural record- ´ ing chopper amplifier for simultaneous neural recording and stimulation, IEEE J. Solid-State Circuits, vol. 52, no. 3, pp. 645656, Mar. 2017.

  15. A. Samiei and H. Hashemi, A chopper stabilized, current feedback, neural recording amplifier, IEEE Solid-State Circuits Lett., vol. 2, no. 3, pp. 1720, Mar. 2019.

  16. X. T. Pham, D. N. Duong, N. T. Nguyen, N. Van Truong, and J.-

W. Lee, A 4.5 G -input impedance chopper amplifier with embedded DC-servo and ripple reduction loops for impedance bosting to sub-Hz, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 1, pp. 116120, Jan. 2021.

Leave a Reply

Your email address will not be published. Required fields are marked *