Modelling and Analysis of Standalone Solar Photovoltaic System integrated with Reduced Switch Multilevel Inverter

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Modelling and Analysis of Standalone Solar Photovoltaic System integrated with Reduced Switch Multilevel Inverter

Gulshan Pradhan

Dept. of Electrical Engg., Vishwavidyalaya Engineering College, Lakhanpur,

CSVTU, Bhilai, Chhattisgarh, India.

Deman Kosale

Dept. of Electrical Engg., Vishwavidyalaya Engineering College Lakhanpur,

CSVTU, Bhilai, Chhattisgarh, India.

Abstract: Renewable power generation becomes more popular nowadays due to the low availability of fuels. This paper proposes an integration of DC sources with reduced switch count multilevel inverter topology for photovoltaic system to achieve a good quality output waveform. The proposed configuration requires less number of power semiconductor devices when compared to conventional multilevel inverter configurations for generating higher output voltage level. Power electronics converters are gaining importance due to the reliable performance of grid-connected solar system or standalone solar system. In this paper nine levels cascaded H- bridge Multi-level inverter (CHB-MLI) is analyzed. The effectiveness of this multilevel inverter is investigated by replacing the input dc source in cascaded inverter bridge with separate PV array and boost converters. This PV fed seven and fifteen levels MLI is analyzed in two ways: (i) with equal magnitude of input voltage source to inverter and (ii) with unequal magnitude of input voltage source. Results are verified in MATLAB/SIMULINK environment by performing simulation.

Keyword: Photovoltaic (PV) array; Multilevel Inverter (MLI); Pulse width Modulation (PWM); Boost Convertor; Solar energy.

  1. INTRODUCTION

    In present days, to manage the issue posed by customary fuel sources, that are exhaustion of petroleum products, air changes, nursery impact, and so forth, different nations are hoping to create more measures of energy from inexhaustible sources [1]. Biofuel, sunlight based, hydro and wind are the significant candidates of sustainable power. Among these, sunlight based and winds are more conspicuous. Sun based energy establishment has developed rapidly in the course of recent years in India. The explanation behind this development is the different benefits given by sun oriented like marked down cost, non- contaminated, low upkeep cost, nonstop accessibility during the daytime [2]. Variables which cause the decrease in sun powered expense are expanding proficiency, advance assembling strategies, and so forth In [3]-[4] numerical displaying of PV is introduced and how PV attributes shift with variety in climate factors like that irradiance, temperature, and so forth likewise depicted.

    The keystone to exploit the sun oriented photovoltaic sources is the inverter. It plays an indispensable part in energy change measure from DC to AC in any network or grid associated system. In past decade, multilevel inverter topologies is more well known in sustainable power

    application. For the most part three sorts of all-inclusive staggered inverter geographies like diode cinched MLI, flying capacitor MLI and the fell H-Bridge MLI is used for high voltage and high force application [5]. In diode clamped MLI, the check of diode raises followed by the expansions in yield voltage level, though in flying capacitor MLI, the capacitor tally has its strength. The cascaded H-Bridge MLI has less number of switches and separate DC sources [6]. Decreased switch multilevel inverter geographies have created to conquer the disadvantage of regular staggered inverter geographies in regards to the part check. Various topologies of staggered inverters are clarified in a detailed manner way in [7]. Each type enjoys its benefits and demerits. A likely disadvantage of every one of these topologies is high number of independent floating DC voltage sources that makes their down to earth utilize very problematic. Hence, in this paper chiefly concentrate to wipe out the usage of numerous DC sources in multilevel inverter with lesser count of semiconductor switches.

    To obtain the needed output voltage each transformer secondary is to be cascaded. The use of the transformer will rise system price and space. To overcome the above problems, PV based multilevel inverters (MLI) are used. Due to simplicity, flexibility and requiring the least number of components cascaded H-bridge multilevel inverter (CHB- MLI) is mainly used. With this, it is possible to get less distorted voltage by simply raising the number of output voltage levels without using any transformer. Hence this paper presents an approach for improving the power quality of PV fed inverter output voltage.

    This paper emphasizes the analysis of a seven and fifteen level MLI for a standalone PV system with lesser count of semiconductor switches. This analysis is performed by considering two configurations (i) Symmetrical configuration that is with equal input voltage magnitude to each bridge and (ii) Asymmetrical configuration in which unequal input voltage magnitude is supplied to each bridge. The investigation is carried out to calculate the THD of the output voltage waveform. Further passive LC filters are used for the improvement of power quality.

  2. THE FRAMEWORK OF PROPOSED SYSTEM The solar PV standalone water pumping system

    framework is depicted in Figure 1. It comprises of a PV array with boost circuit, followed by eight-switches seven and fifteen-level inverter and with an AC R-L load. The proposed

    multilevel inverter with reduced switches is used to provide pulse width modulated single phase voltage to the input of AC loads which are inductive in nature.

    Fig. 1 Single Phase Proposed MLI integrated with PV array

    1. PV ARRAY Modelling and MPPT

      The photovoltaic cells are made of customized PN junction diode that converts the visible light into DC, and this process is referred to as photovoltaic effect. The PV modules combined in parallel or series to generate higher voltage and currents [8]. The PV unit can be represented by two model: single diode model (SDM) and the double diode model [9]-[10]. The SDM model is the most prevailed model that has less complexity and achieve accurate results. It represents the individual PV cell; a PV module consists of many cells or an array that includes many modules together. The mathematical equation describing the PV system is expressed in equation[11].

      Fig. 2: Single diode PV cell

      TABLE I: SINGLE PV MODULE DETAILS

      Parameters

      Values

      Open circuit voltage (Voc)

      44 V

      Short circuit current (Isc)

      8.1 A

      Maximum power point voltage (Vm)

      34.7 V

      Maximum power point current (Im)

      7.8 A

      Maximum Power (Pm)

      260.7 W

      + ( )

      [

      = 0

      {

      [ ] [ ]

      + ( )

      ]

      1

      }

      Fig. 2: P-V and I-V characteristics of single solar cell.

      where,

      (1)

      ( )

      The variation of the irradiance level, panel temperature and IV characteristic of a PV array, led to variation in MPP, (as it is the function of the irradiance level,

      Ipv is the current produced by incident light (Amps),

      Io is the leakage current of a diode (Amp),

      q is the charge of an electron (1.60217 × 1019C), k is the Boltzmann constant (1.38065 × 1023 J/k), is he diode ideality constant (1 < a < 1.5),

      Rs is the equivalent PV array series resistance (), Rp is the equivalent PV array parallel resistance (), Nsr is the number of cells in series,

      Npr is the number of cells in parallel,

      T is the PN junction temperature (K), and

      Vt is the PV array thermal voltage (Volts).

      ambient temperature, efficiency of the heat exchange process and operating point of the panels)[12]-[14]. It makes necessary to track continuously the MPP to maximize the power output from a PV system, for a given set of operating conditions. In P&O method, the MPPT algorithm is based on output power the calculation of the PV and change in power by sampling both the PV Array current and voltage. The tracker observes change in voltage (V) and the voltage is incremented or decremented periodically of the PV panel. If the perturbation leads to an increase (decrease) in differential change in power (P) of PV, then the subsequent perturbation is generated in the same (opposite) direction [15]-[18]. The variation of duty cycle fed to dc chopper is varied until the maximum power point has been achieved. This variation produces oscillation in system which can be minimized by reducing the step size of perturbation. The various values of irradiance and cell temperatures, the PV array exhibit different characteristic PV curves having different maximum power point. The voltage value at point

      where maximum power corresponds maximum voltage in the curve is supplied to the DC-DC converter for its operation. The below figure depicts the P&O MPPT algorithm[19].

      Start P&O Algorithm

      Measure V(k), I(k)

      P(k) = V(k)*I(k)

      P = P(k) P(k-1)

      output varies with same architecture. When compared to traditional inverters achieving same levels that is possible with single structure requires high number of required components like semiconductors (switch, IGBT) and dc sources, to raise the number of steps. number of current path components which can increases the total conduction loss and degrade the overall efficiency thereby [25].

      1. Symmetrical Topology: For this state the value of DC sources in converter are taken equal in magnitude. Switching conditions and levels of the projected topology in symmetrical mode are illustrated in Table II.

        Yes

        No

        V(k) – V(k-1) > 0 No

        P > 0

        Yes

        No

        V(k) – V(k-1) > 0

        Yes

        TABLE II. VOLTAGE LEVEL AND SWITCHING STATE OF THE 7- LEVEL MULTILEVEL INVERTER WITH EQUAL DC

        VOut

        S1

        S2

        S3

        S4

        S5

        S6

        S7

        S8

        S9

        Vdc

        0

        1

        1

        0

        1

        0

        0

        1

        0

        2Vdc

        0

        1

        1

        0

        0

        1

        1

        0

        0

        3Vdc

        0

        1

        1

        0

        0

        1

        0

        0

        1

        0

        1

        0

        1

        0

        1

        0

        0

        1

        0

        -Vdc

        1

        0

        0

        1

        0

        1

        0

        0

        1

        -2Vdc

        1

        0

        0

        1

        1

        0

        1

        0

        0

        -3Vdc

        1

        0

        0

        1

        1

        0

        0

        0

        1

        VOut

        S1

        S2

        S3

        S4

        S5

        S6

        S7

        S8

        S9

        Vdc

        0

        1

        1

        0

        1

        0

        0

        1

        0

        2Vdc

        0

        1

        1

        0

        0

        1

        1

        0

        0

        3Vdc

        0

        1

        1

        0

        0

        1

        0

        0

        1

        0

        1

        0

        1

        0

        1

        0

        0

        1

        0

        -Vdc

        1

        0

        0

        1

        0

        1

        0

        0

        1

        -2Vdc

        1

        0

        0

        1

        1

        0

        1

        0

        0

        -3Vdc

        1

        0

        0

        1

        1

        0

        0

        0

        1

        VOLTAGES

        Increase PV Voltage

        Decrease PV Voltage

        Decrease PV Voltage

        Decrease PV Voltage

        Update V(k-1) = V(k)

        P(k-1) = P(k)

        Increase PV Voltage

        Fig. 3 Flowchart of P&O MPPT algorithm

    2. MULTILEVEL INVERTER

      The Fig. 4. demonstrates the basic topology of multilevel inverter proposed in this paper. The multilevel converter consists of nine switches (IGBT) which gets energized by three sources neighboring them. The synthesized output from MLI can be achieved by providing different paths to the connected sources for conduction with help the of switching pattern of power switches [20]. A variation in values can be considered for the sources. Therefore, two sections, symmetrical and a-symmetrical, are organized to explicate the proposed structure. Modularity is the other important features of the mention structure, so it can be used in high-voltage applications [21]-[24].

      1. A-symmetrical Topology: For this state the value taken for operation will be unequal in magnitudes of DC sources. Hence the level achieved here will be higher than symmetrical one. Switching conditions and levels of the projected topology in a-symmetrical mode are illustrated in Table III.

      TABLE III. VOLTAGE LEVEL AND SWITCHING STATE OF THE 15- LEVEL MULTILEVE INVERTER WITH UNEQUAL DC

      VOLTAGES

      S3 S5

      S1

      Va

      S2

      S4 S6

      Vb S8

      VOut

      S1

      S2

      S3

      S4

      S5

      S6

      S7

      S8

      S9

      Vdc

      0

      1

      1

      0

      1

      0

      0

      1

      0

      2Vdc

      1

      0

      0

      1

      0

      1

      1

      0

      0

      3Vdc

      0

      1

      0

      1

      0

      1

      1

      0

      0

      4Vdc

      0

      1

      1

      0

      0

      1

      1

      0

      0

      5Vdc

      1

      0

      0

      1

      0

      1

      0

      1

      0

      6Vdc

      0

      1

      0

      1

      0

      1

      0

      1

      0

      7Vdc

      0

      1

      1

      0

      0

      1

      0

      1

      0

      0

      0

      1

      0

      1

      0

      1

      0

      0

      1

      -Vdc

      1

      0

      0

      1

      0

      1

      0

      0

      1

      -2Vdc

      0

      1

      1

      0

      1

      0

      1

      0

      0

      -3Vdc

      1

      0

      1

      0

      1

      0

      1

      0

      0

      -4Vdc

      1

      0

      0

      1

      1

      0

      1

      0

      0

      -5Vdc

      0

      1

      1

      0

      1

      0

      0

      0

      1

      -6Vdc

      1

      0

      1

      0

      1

      0

      0

      0

      1

      -7Vdc

      1

      0

      0

      1

      1

      0

      0

      0

      1

      VOut

      S1

      S2

      S3

      S4

      S5

      S6

      S7

      S8

      S9

      Vdc

      0

      1

      1

      0

      1

      0

      0

      1

      0

      2Vdc

      1

      0

      0

      1

      0

      1

      1

      0

      0

      3Vdc

      0

      1

      0

      1

      0

      1

      1

      0

      0

      4Vdc

      0

      1

      1

      0

      0

      1

      1

      0

      0

      5Vdc

      1

      0

      0

      1

      0

      1

      0

      1

      0

      6Vdc

      0

      1

      0

      1

      0

      1

      0

      1

      0

      7Vdc

      0

      1

      1

      0

      0

      1

      0

      1

      0

      0

      0

      1

      0

      1

      0

      1

      0

      0

      1

      -Vdc

      1

      0

      0

      1

      0

      1

      0

      0

      1

      -2Vdc

      0

      1

      1

      0

      1

      0

      1

      0

      0

      -3Vdc

      1

      0

      1

      0

      1

      0

      1

      0

      0

      -4Vdc

      1

      0

      0

      1

      1

      0

      1

      0

      0

      -5Vdc

      0

      1

      1

      0

      1

      0

      0

      0

      1

      -6Vdc

      1

      0

      1

      0

      1

      0

      0

      0

      1

      -7Vdc

      1

      0

      0

      1

      1

      0

      0

      0

      1

      S9

      Vc S7

      LOAD

      Fig.4. Schematic view of proposed Multilevel Inverter

      In terms of magnitude of dc sources, the multilevel inverters are separated into two structures symmetric and a- symmetric respectively. The value of dc sources in symmetric structure are equal in value to each other while in asymmetric topology these values are different as a result

  3. MLI SWITCHING SCHEME

    Various modulation strategies are used for the generation of firing pulses of MLI. Space vector modulation and Carrier-based modulation are the most prominent topologies, especially in case of high switching frequency. Space vector modulation becomes difficult as the number of voltage level increases. So mainly carrier-based modulation

    method is used. In carrier-based modulation scheme, carriers are arrangement either by level shifting techniques or by phase shifting techniques [25]. In Level shifting techniques generally, three arrangements that are in-phase Disposition (PD), Alternative Phase Disposition (APOD) and Phase opposition Disposition (POD) are considered. In this paper, Phase disposition carrier-based modulation scheme is used as depict in Fig. 5. In this scheme, carriers are in phase with equal frequency and magnitude. In level shifting techniques, to generate firing pulses for L level inverter Lv -1 carriers are required. Carriers are equally divided into two parts: one is for above the zero reference and other are placed below the zero reference [26]. In PD carrier scheme, sinusoidal pulse is compared with the triangular carrier to generate the Boolean outputs, which produce suitable firing pulses for inverter switches.

    The Fig. 5 express the SPWM technique for above stated strategy for both fed by PV sources for mentioned MLI topology. It is likely to achieve voltage levels figured in Table I and II by properly firing the switches in the as shown in below figure for the seven and fifteen level multilevel inverter. The firing pulses are generated by multicarrier pulse width modulation procedure. For implementing this method, as shown in Fig. 5, a standard sinusoidal wave is compared with 14 levels of triangular wave to create the firing pulses for each switch in the stated multilevel inverter. A traditional SPWM with triangular carriers can explained an n Level MLI, (n-1) carriers are required [27].

    Fig. 5 Phase Disposition carrier arrangement for 15-level output voltage

  4. SIMULATION RESULTS AND ANALYSIS

    The simulation analysis of seven and fifteen level MLI with PV system is performed using MATLAB / Simulink. Here a load of resistance of 100 ohm and inductance of 1 mH is taken as ac load. Table-II shows the parameters used for simulation. The obtained simulation results for standalone PV system with nine levels CHB-MLI is discussed as follows:

    In Fig. 6, the output voltage of PV module is connected at the Boost converter input to obtain a boosted steady output. The reproduction after effects of the yield energy of the module input energy of the Boost converter and the yield energy of Boost converter for various sunlight-based irradiance after recreation are seen i the below waveform. The MPPT algorithm with conjunction with DC/DC boost converter is able to maintain increased voltage level when supplied power from the PV array at constant irradiance and temperature satisfying STC conditions.

    Fig.6 Output waveforms of PV array and DC/DC boost converter

    Case I: Symmetrical MLI

    In this scheme, the projected symmetrical structure having the values V1=V2=V3= 100V PV source and the switches as per states shown Table I and simulated. Fig. 7 and 8 shows the output voltage mentioned 7-level structure. The performance of the topology proposed can be observed in the results obtained.

    Fig.7 Simulated output voltage waveform for stated 7-level MLI.

    Parameters

    Symmetrical

    Asymmetrical

    Input voltage to proposed MLI

    Va = 100 V Vb = 100 V Vc = 100 V

    Va = 50 V Vb = 150 V Vc = 150 V

    Switching Frequency

    5 kHz

    Load

    R = 100 & L = 1 mH

    Parameters

    Symmetrical

    Asymmetrical

    Input voltage to proposed MLI

    Va = 100 V Vb = 100 V Vc = 100 V

    Va = 50 V Vb = 150 V Vc = 150 V

    Switching Frequency

    5 kHz

    Load

    R = 100 & L = 1 mH

    TABLE IV. DESIGN PARAMETER FOR SIMULATION

    Fig. 8 Magnified view of output waveform for 7-level MLI

    The figure 8 shows the zoomed view of 7 level MLI output with lesser ripples for achieving the proposed output without any distortion.

    Case II: Asymmetrical MLI

    The same structure is stimulated for achieving higher level by replacing the equal PV sources with unequal in magnitudes i.e., V1=50V, V2=V3=150V that provides maximum 343V on the output side of inverter. The results are satisfactory and also quite comparable to each other, which validates the performance of the projected structure. The figure 10 shows the zoomed view of 15 level MLI output with lesser ripples for achieving the proposed output without any distortion.

    Fig. 9 Simulation output voltage waveform for stated 15-level MLI.

    Fig. 10 Magnified view of output waveform for 15-level MLI.

  5. CONCLUSION

In this paper, PV fed multilevel PV standalone system has been modelled and analyzed for seven and fifteen level inverter output has been examined (i) with equal modulated voltage level and (ii) with inequal voltage as input. It is noticed that when the input voltages are of equivalent values for reduced produces less levels compared to unequal voltage inputs. The combination of output boost converter with reduced switch multilevel inverter has been introduced for standalone photovoltaic operation. Also, the P&O MPPT algorithm is tested in this paper with validated output from PV system. The proposed system is tested only in standard test condition in this paper. From the results and discussion, it is concluded that the proposed system provides better quality output waveforms with lesser component count and can be suitable for photovoltaic grid connected operation.

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