- Open Access
- Total Downloads : 6
- Authors : Tanmay J.Bharambe, S.S.Dhamse
- Paper ID : IJERTCONV3IS16139
- Volume & Issue : TITCON – 2015 (Volume 3 – Issue 16)
- Published (First Online): 30-07-2018
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License: This work is licensed under a Creative Commons Attribution 4.0 International License
Matlab Simulation of Three Phase Shunt Active Filter by Current Decomposition Method
PG Scholar, ME (Electrical Power Systems) Govt. College of Engg
Dept. of Electrical Engineering Govt. College of Engineering Aurangabad, India
Abstract This paper presents the use of shunt active power filter for harmonic mitigation, reactive power compensation and mitigating unbalance in the system. The proposed control scheme based on decomposition of load current into four parts, viz. fundamental frequency positive sequence active and reactive current, current at harmonic frequency and fundamental frequency negative sequence current by using Synchronous Reference Frame (SRF) theory. The compensating current is obtained from the above decomposed components by using SRF theory. The results obtained from a MATLAB simulation prove the importance of the scheme.
KeywordsActive power filters (APF); Synchronous reference frame (SRF) theory; voltage source inverter (VSI); reactive power; harmonic; unbalance; selective compensation.
Nowadays, the consumers are more aware of the power quality problems and their causes. The extensive use of power electronics devices such as converters and inverters in both industrial and at consumer level has emerged with the challenge to improve the power quality issues by mitigating the problems such as harmonics, reactive power compensation due to the non-linear loads. Suitable criteria are set by IEEE 519 standard to overcome the harmonics problems within limits. According to these standards, an engineer must ensure that the system should less than 5%THD .
The increased use of nonlinear loads, such as rectifier devices in TV, ovens and telecommunication power supplies and commercial lighting systems cause excessive neutral currents, harmonic injection and reactive power burden in the power system. They result in poor power factor, and lower efficiency of power system . In the last years, residential, commercial and industrial customers have been responsible for the increasing of non-linear loads connected to the utility, which contribute significantly to the pollution of the power supply system. Several power conditioners, such as single- phase and three-phase Active Power Filters (APF), Uninterruptible Power Supply (UPS) systems, etc., have been used to improve the power quality both in three-phase three- wire systems and three-phase four-wire systems . The reliability of the VSI components such as semi-conductor switches is critical for the shunt active power filters. A failure in one of the switches decreases system performances and usually leads to disconnect the filter . The performance of APF is dependent on how the reference compensating signals are estimated. Various theories such as instantaneous reactive power theory, p-q theory, modified p-q theory , FBD theory and estimation based on neural networks. This schemes has
complex calculations and fails to perform during real-time implementation  and some scheme use adaptive technique for current decomposition .
In this paper, a Shunt Active Power Filter (SAPF) is employed for which a simple Synchronous Reference Frame (SRF) based scheme is used to decompose the load current into four parts:
Positive sequence fundamental frequency active current (iLR +)
Positive sequence fundamental frequency reactive current (iLX +)
Current at harmonics frequency (iLh)
Negative sequence fundamental frequency current (iL -)
By applying the selective compensation technique, the decomposed current components are compensated priority wise
i.e. those current components with higher harmonics will be compensated first. This technique is applied according to the priority i.e.in the order followed by harmonics, phase unbalance, reactive power compensation and the vice-versa combinations of them. The effectiveness of the proposed scheme is shown by Simulation in MATLAB with proper results and statistical data.
The load currents are decomposed into four parts i.e. positive sequence active (iL1R), reactive (iL1X) current and
negative sequence current (iL1-) at fundamental frequencies and
current at harmonic frequencies (iLh) by using the SRF theory. If is the time varying angle that represents the angular position of the reference frame which is rotating at constant speed in synchronism with the three phase ac voltages. The SRF theory is shown in the Fig. 1.
Fig. 1. Basic proposed scheme using SRF theory
In this, load currents iLa, iLb, iLc are converted into frame and then into dq reference frame as shown below by equation
(1) and (2).
cos() cos( 2 ) cos( 4 ) i
3 sin(t) cos(t) i
3 sin() sin( )
cos(t) sin(t) LdcD
i sin(t) cos(t) i
1 / 2
1 / 2
i 3 0
3 / 2
3 / 2
The net negative sequence components are obtained by
converting the extracted dc components into and then into
cos(t) sin(t) iL
a-b-c co-ordinates as shown by:
i sin(t) cos(t) i
i 1 0
3 1 / 2 3 / 2 i
The extraction of dc components is done from low pass filter by an extractor as shown in Fig. 1. Now for obtaining the
1 / 2 3 / 2 L
positive sequence fundamental frequency components, these extracted dc components are transformed back into – frame and then into a-b-c terms, which is given by
From the above decomposed components, selective compensation of individual and combinations of them is done, and the harmonics, phase unbalance & reactive power
iL cos(t) sin(t) iLdcD
compensation is done priority wise.
i sin(t) cos(t) i
The real (iLR+) and reactive (iLX+) currents can be obtained by decomposing the dc components in the d-q frame.
The Fig. 2 shows the control technique based on SRF theory. In this, load current signal is fed to the SRF extractor; it extracts or decomposes the load current into required four
The reference currents (i*sa , i*sb , i*sc) for required
sin(t) cos(t) i
cos(t) sin(t) iLdcD
compensation is obtained by taking the difference of the load current and the decomposed current components which are need t be compensated. Out of the four decomposed current
i sin(t) cos(t) 0
components, those components having higher number of r r e i
harmonics a e compensated prio ity wis in the descend ng
From equation (5) and (6), the real and reactive components in terms of a-b-c co-ordinates are given by:
i 1 0
order i.e. those components having higher number of harmonics will be compensated first, after that the other components in the level of their importance in the application. This is achieved by the priority and gain scheduler block; the components are selected priority wise in the level of their importance. Thus, selective compensation is achieved. Here,
1 / 2 3 / 2
the first priority is given to harmonics, then unbalance and after that reactive power compensation.
3 1 / 2 3 / 2 iLR
i 1 0
1 / 2 3 / 2
3 1 / 2 3 / 2 iLR
The negative sequence current components are obtained by transformation of frame into dq frame, and then extraction of dc quantities are done by LPF similarly as done previously in case of positive sequence components.
Fig. 2. Proposed Control Technique
The current component which required to be fully compensated will be assigned a gain 0, and components which are not need to compensated would be assigned a value 1. Furthermore, to prevent the overloading of the SAPF, the adjustment of gains Kx , Kh, Kn are in reverse order. Here, the gains are assigned a value less than 1. A PI controller is used for regulating the dc bus voltage to its reference value and also for minimizing the inverter losses. The required current is added to the positive sequence fundamental frequency active component for maintaining the dc voltage constant and to minimize the inverter losses. The Hysteresis current controller generates the PWM gating signals for the VSI of SAPF by using the reference supply current (i*sa , i*sb , i*sc) and given supply currents (isa , isb , isc). Finally, the overall compensation current is injected so that supply current follows the reference current.
The basic model of proposed scheme consists of SAPF connected between the three phase source and the load as shown in Fig. 3.The load 1 is resistive load used for creating unbalance in the system by opening any of the phases. The load
2 is diode rectifier circuit followed by a combination of capacitor and resistive load.
Fig. 3. Model of proposed scheme for current decomposition.
The Fig. 4 shows the waveforms related to decomposition of load currents into four parts i.e. positive sequence fundamental frequency active and reactive current, current at harmonic frequencies, negative sequence fundamental frequency current. As shown in fig. 3.2. we can see that load 1
i.e. resistive load is switched on at 0.05s and unbalance is created at 0.14s by opening phase a, the negative sequence current observed changes as soon as unbalance occurs; whereas it is observed that there is no effect or change on the positive sequence active and reactive current.
Model With SAPF And Diode Rectifier Load
The Fig. 5 shows the model with SAPF and diode rectifier load. The model consists of a controller and a measurement block. The timer block provided at the breaker of APF takes care of the time at which APF should be switched on, here at
0.08s. The unbalance is created with the help of breaker by opening phase a of three phase diode rectifier load.
Fig. 4. Decomposition of Load Current
Fig. 5. Model with SAPF and diode rectifier load
The Fig. 6 shows the controller used for the proposed scheme, in these the PI controller is used to regulate the dc bus voltage to its reference value and to compensate for inverter losses. The signals from PI controller are given to the dq0 to abc transformation block and finally connecting it to summimg point. The three phase voltage source is fed to the Discrete 3phase PLL block, from which the sin and cos quantities are extracted and further fed to the dq0 to abc transformation block. The three phase load current is fed to the SRF controller block from which the isref is obtained and further feeded to the summing point. The isref signals obtained from the summing point and are signals are fed to the
hysteresis current controller for generating the gate pulses for VSI.
Fig. 6. Controller of the Proposed Scheme
The Fig. 7 shows the SRF controller. The three phase load current (Iabc) and three phase source voltages (Vabcs) are converted into two components Id and Iq by Clarkes Transformation. These decomposed current components are converted into their dc components by Parks Transformation. This extracted dc components of current Iddc and Iqdc are further combined and reference current signals Isref are obtained.
Fig. 7. Block Diagram of SRF controller
Hysteresis current controller
The Fig. 8 shows the hysteresis current controller. The difference between Isref and Is is taken and given to PI controller and further the difference between the output of the PI controller and the repeating sequence block is taken, given to the convert block and finally the gating pulses are obtained for the switching of the IGBTs of the VSI.
Fig. 8. Hysteresis current controller
The following parameters are used designing of the SAPF as shown in Table I.
TABLE-I. DESIGN SPECIFICATION AND PARAMETERS
Source Voltage (Vs)
230V per phase
Source Resistance (Rs)
Source Inductance (Ls)
DC bus Voltage (Vdc)
DC Link Capacitance(Cdc)
1 per phase
Load2(Rectifier fed R Load)
Without Applying Filter
The Fig. 9 shows the results obtained without applying filter to the proposed scheme. The unbalance is created by opening phase a for duration 0.18sec to 0.35sec, due to this, it is observed that load current phase a (iLa) is zero for this duration. After 0.35sec, the phase a is restored. It is observed that there is no change in source voltage, but there is presence of harmonics components in the source current (Is) and three phase load current.
Fig. 9. Results obtained without applying SAPF
The Fig. 10 shows the Fast Fourier Transform (FFT) analysis of Source Current (Is) without applying filter. In this, it is observed that due to presence of harmonics and unbalance, the %THD is 22.81%, 22.70% and 21.44% for source current phase a, b, c respectively. There is major presence of 3rd, 5th, 7th order harmonics.
The SAPF is operated at 0.08s and phase a of three phase diode rectifier load is opened from 0.18s to 0.35s, the filter is eliminating harmonic alone from 0.08s to 0.22s; as well as it
compensate for all problems i.e. harmonics, unbalance and reactive power compensation all together from 0.35s to 0.44s as shown in Fig. 11.It is clearly observed that due to the SAPF, there is restoration of opened phase and harmonics are eliminated.
The FFT anlysis for the source current by applying the filter is shown in Fig. 12.(a)-(c). In this, it is observed that there is reduction in %THD to 4.62%, 4.26%, 4.17% for source current Is of phase a,b,c respectively. It is observed that it is well below 5% as per IEEE standards.
(b) (c) Fig.10. (a)-(c) FFT analysis of Source current Is by without applying filter
Fig.11. Results obtained by applying SAPF
(b) (c) Fig.12. (a)-(c) FFT analysis of Source current Is by applying filter
Comparison of %THD and RMS current With And Without Applying Filter
Load current and %THD of source current is obtained without and with applying filter is tabulated in Table II. It is observed that there is reduction in %THD and it is below 5%.
TABLE II. %THDAND LOAD CURRENT WITH AND WITHOUT FILTER
The proposed scheme shows that the SAPF can be used effectively for compensating harmonics, negative sequence current and reactive power compensation by level of priority to
the foreseen above problems. The simulation results of proposed model shows the effectiveness of the scheme with reduction in %THD according to IEEE519 standards.
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