Matlab Code for LTE Convolutional Code and Viterbi Decoder

DOI : 10.17577/IJERTV6IS030465

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Matlab Code for LTE Convolutional Code and Viterbi Decoder

Aly A.E. Elwazan Electrical Engineering Department Benha Faculty of Engineering, Egypt

Hossam L. A.Zayed Electrical Engineering Department Benha Faculty of Engineering, Egypt

Abdelhalim A. A. Zekry

Electronics and Communications Engineering Department Faculty of Engineering Ain Shams, Egypt

AbstractLTE system needs a powerful method for error control on the transmission channel. The error control method is based on adding parity bits to the signal data stream. These parity bits are used to detect the error in bits and also to correct them. Meanwhile, Convolution Encoding with Viterbi Decoding is a powerful method for Forward Error correction and Detection. In this paper, Matlab simulation Model as well as hardware architecture of LTE Viterbi decoder was designed with specifications according to 3GPP standard, where the code rate 1/3.

Keywords LTE; Convolution Encoder; Viterbi Decoding; 3GPP.


    The goal of designer is to create a communications system that transport a message signal from a source across channel has noise to a user at the other end of the channel with the following objective: The data is delivered to the user both efficiently and reliably, submit to certain design restrictions: Permissible transmit power, available bandwidth channel, and low cost of building the system. Convolution coding is a popular error-correcting coding technique used in digital communications. A data is convoluted, and then transmitted into a noisy channel. This convolution process encodes some redundant bits into the transmitted signal, thereby improving the data capacity of the system channel. The popular method used to decode convolutional coded messages is Viterbi algorithm. The algorithm tracks down the most likely sequences the encoder went through in encoding the data, and uses this information to discover the original message.


    An exhaustive literature survey has been carried out related to the titled work to find out the current research. In [11], K.Cholan, introduced new method of Viterbi decoder to improve in terms of area and speed. The design is based on reconfigurable FPGA technology, by adopting parallel pipeline features of the hardware resources. The overall system performance improved in terms of area and speed. In [9], Soreng B., a Convolution Encoder and Viterbi decoder of code rate1/2, and constraint length 7 was presented. It shows a large improvement in terms of area overhead. In [10],Gohe l implemented a Viterbi decoder based on FPGA using a constraint length of 7 and a code rate of 1/2.Itshowed an improvement in the design by using trace back implementation of survivor sequence memory management for low power decoder design. In this paper an enhancement

    in the implementation of a soft decision Viterbi decoder on Virtex-6 FPGA XC6VLX240T is introduced to overcome problems of complex implementation and area.

  3. CONVOLUTIONAL CODES Convolutional codes technique differ from block codes

    technique in that the encoder contains memory and the n encoder outputs at any time unit depend on the k inputs and m previous input blocks. An (n, k, m) convolutional code can be implemented with a k input, n-output with input memory m. typically, n and k are small integers with k<n, but the memory order m must be large to achieve low error probabilities. In the important special case when k=1, the data sequence is not divided into blocks and can be processed continuously.

    A convolutional code is generated by passing the information to be transmitted through a linear limited-state shift register. In general, the shift register contains K (k-bit) stages and n linear algebraic function generators.

    • k: number of bits shifted into the encoder at one time

      k=1 is usually used!!

    • n : number of encoder output bits corresponding to the k information bits

    • Rc = k/n : code rate

    • K : constraint length

    • m : encoder memory

    • K = m+1

    Each encoded bit is a function of the present input bits and their past ones. [1]


    Both the algorithm and operation behind the proposed 64 state Viterbi decoder, depicted in Fig. 1, are presented [2]. When a new symbol is received, the branch metric unit calculates the Euclidean distances (ED) for all possible trellis state transitions. The encoder is flushed with zeros at the end of each frame. The decoder performs frame by frame decoding. The computation of branch metrics is based on a comparison of the current input symbol with the expected value. The path metrics are identified as letters at different nodes of the trellis [3].

    The Viterbi algorithm is a maximum likelihood method to find the most probable sequence of hidden states based on a given sequence of detected outputs in Hidden Markov model. However it reduces the computational load by taking the advantage of special form in code trellis. The algorithm involves calculating a measure of distance between the

    received signal at the time t1 and the come in trellis path entering each state at time t1. The most likely path through the trellis will maximize this metric. The early refusal of the unlikely paths reduces the decoding complexity. Advantage of Viterbi algorithm is that it has self- rectification of the code, minimization of transmitting Energy, minimization of BW and very good capability to correct wrong transmitted bits, [4]


    The two decoding algorithms used for decoding the convolution codes are Viterbi algorithm and Sequential algorithm. The sequential decoding has an advantage that it can perform very well with long constraint length. The Viterbi decoding is the best technique for decoding the convolution codes but it is limited to smaller Constraint lengths [5].In order to realize a certain coding scheme a suitable measure of similarity or distance metric between two code words is vital. The two important metrics used to measure the distance between two code words are the Hamming distance and Euclidian distance adopted by the decoder depending on the code scheme, required accuracy, channel characteristics and demodulator type [6].

    1. Hard Decision Viterbi Decoding:

      In hard-decision decoding, the path through the trellis is determined using the Hamming distance measure. Thus, the most favorable path through the trellis is the path with the minimum distance. The Hamming distance can be defined as a number of bits that are different between the detected symbol at the decoder and the sent symbol from the encoder. Also, the hard decision decoding applies one bit quantization on the received bits [6].

    2. Soft-Decision Decoding:

      Soft- decision decoding is used for the maximum likelihood decoding, when the data is transmitted over the Gaussian channel. On the contrary to the hard decision the demodulator input is now an analog waveform and is usually quantized in to different levels in order to help the decoder decide more easily. Using soft- decision decoding interest is to provide decoder with more information, which decoder then use for regains the message sequences. It provides better error performance than hard-decision type. Viterbi decoding also has a performance improvement of approximately 2 dB in the

      required S/N ratio compared to the two level quantization

      1. Physical Broadcast Channel (PBCH)

        In perfect cellular systems the basic system information which allows the other hannels in the cell to be configured and operated is carried by a Broadcast Channel (BCH). So the achievable coverage for reception of the BCH is crucial to the successful process of such cellular communication systems; LTE is no exception. [7]

      2. Physical Downlink Control Channel (PDCCH)

        A PDCCH carries a data known as Downlink Control Information (DCI), which contains resource assignments and other control information for a user equipment or group of user equipment. In general, several PDCCHs can be transmitted in a subframe. [7]

        1. Tail biting convolutional coding

          1. convolutional encoder

            A convolutional encoder (k, n, m) is composed of a shift register with m stages. At each time instant, k information bits enter the shift register and k bits in the last position of the shift register are dropped. The set of n output bits is a linear combination of the content of the shift register. The rate of the code is defined as Rc = k/n. The following Figure shows the convolutional encoder used in LTE with m = 6, n = 3, k = 1 and rate Rc = 1/3. The linear combinations are defined via n generator sequences G = [g0, gn1] where

            g = [gl,0, gl,1 , gl,m].

            The generator sequences used in the following Figure are

            g0 = [1 0 1 1 0 1 1], g1 = [1 1 1 1 0 0 1], g2 = [1 1 1 0 1 0 1]

            or using octal notation

            g0 = [133] (Oct), g1 = [171] (Oct), g2 = [165] (Oct). [7]

            Figure.1: Rate 1/3 tail biting convolutional encoder

            The convolutional coded transport channels and control information rate matching consists of interleaving the three

            bit streams (0), (1), (2)Followed by the collection of bits

            processes, for a given Gaussian Channel. Disadvantage of using soft decision decoding is the increase in required memory size at the decoder and the reduced speed [4].


    A. Downlink Physical Data and Control Channels

    Unlike the data, control information (such as is sent on the Physical Downlink Control CHannel (PDCCH) and Physical Broadcast CHannel (PBCH)) is used a convolutional code to coded, as the code blocks are significantly smaller and the additional complexity of the turbo coding operation is therefore not worthwhile.[7]

    and the generation of a circular buffer as shown in the following Figure the output bits are transmitted as described in sub clause.[8]

    Figure.2: Rate matching for convolutionally coded transport channels and control information.

      1. Sub-block interleaver

    The bit stream (0) is interleaved in accordance with the sub- block interleaver with an output sequence sort out as

    (0) ,(0), (0) , ,(0)

    0 1 2


    The bit stream (1) is interleaved in accordance with the sub- block interleaver with an output sequence sort out as

    (1) ,(1), (1) , ,(1)

    0 1 2


    The bit stream (2) is interleaved in accordance with the sub- block interleaver with an output sequence sort out as

    (2) ,(2), (2) , ,(2) .[8]

    0 1 2


        1. Viterbi decoder


          Number of columns

          Inter-column permutation pattern

          < P(0),P(1)..,P( ) >


          < 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23,

          15, 31,0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6,

          22, 14, 30 >

          1. Bit collection and selection

            The circular buffer of length =3 are generated as follows:

            =(0) for k = 0,, 1

            +=(1) for k = 0,, 1

            2 +=(2) for k = 0,, 1

            Denoting by E the output sequence length rate matching, the rate matching output bit sequence is , k = 0,1,…, E 1.[3]

          2. Modulation

    Physical Broadcast CHannel (PBCH) and Physical Downlink Control CHannel (PDCCH) that coded with a convolutional code are used QPSK modulation. [7]

    Figure 4: BER versus SNR for coding rates 1/3


    Figure.3: Flow chart of Matlab code


      The performance of the Viterbi decoder can be evaluated through comparing the recovered message with the original message and calculating the bit error rate (BER) at a specific energy per bit to signal to noise ratio(SNR) according to the Formula: BER = Number of errors / total message length.


  1. G. Eason, B. Noble, and I.N. Sneddon, On certain integrals of Lipschitz-Hankel type involving products of Bessel functions, Phil. Trans. Roy. Soc. London, vol. A247, pp. 529-551, April 1955. (references)

  2. Soreng B. And Kumar .S, Efficient Implementation Of Convolution Encoder Andviterbi Decoder, International Conference On Circuits, Power And Computing Technologies [Iccpct-2013], 2013.

  3. Abdul-Shakoor.A.S And Szwarc.V, A High Performance Soft Decision Viterbi Decoder For Wlan And Broadband Applications, Communications Research Centre Canada 3701 Carling Avenue, Box 11490, Station H Ottawa,

    Ontario, K2H 8S2, 2006

  4. Hiral Pujara, and Pankaj Prajapati RTL Implementation Of Viterbi Decoder Using VHDL IOSR Journal Of VLSI And Signal Processing (IOSR-JVSP) Volume 2, Issue 1,

    PP 65-71, 2013

  5. Ajaysharma, Design and implementation of viterbi decoder using fpgas,Electronics and communication engineering department,Thapar University,Patiala(Punjab)-147004(India), March,2008.

  6. Suneha Guptajuly,Design And Implementation Of An Optimized Viterbi Decoder, Department Of Electronics and Communicationengineering THAPAR UNIVERSITY,


  7. LTE The UMTS Long Term Evolution: From Theory to Practice Stefania Sesia, Issam Toufik and Matthew Baker © 2009 John Wiley & Sons, Ltd. ISBN: 978-0-470-69716-0

  8. 3GPP TS 36.212 V8.1.0 (2007-11) 3rd Generation Partnership Project;

    Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (Release 8)

  9. Soreng B. And Kumar .S, Efficient Implementation Of Convolution Encoder Andviterbi Decoder, International Conference On Circuits, Power And Computing Technologies [Iccpct-2013], 2013.

  10. Gohel. Pand Dave K.C, Implementation Of Viterbi Decoder OnFpga ToImprove Design, Proceedings Of SARC-IRAJ International Conference, 14th, Delhi, India, ISBN: 978-93- 82702-21-4, July 2013.

  11. K.Cholan, a, Design and Implementation of Low Power High SpeedViterbi Decoder, 1877-7058 © 2011 Publishedby Elsevier Ltd.,doi:10.1016/j.proeng.2012.01.834,2011.

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