 Open Access
 Authors : K.A.Muthulakshmi, R.Yogeshwari, V.Nithyapoorani
 Paper ID : IJERTCONV12IS01009
 Volume & Issue : NCAAIET – 2024 (VOLUME 12 – ISSUE 01)
 Published (First Online): 09032024
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Mathematical Modeling Of Digitally Controlled RF SelfInterference Canceller for FullDuplex Transceiver
1K.A.Muthulakshmi,2R.Yogeshwari,3V.Nithyapoorani 1,2,3Assistant Professor
Department of Electronics and Communication Engineering, Sri Bharathi Engineering College for Women,Pudukkottai Dist.
AbstractThe mobile communications systems revolution the way in which the people communicate with each other. Nowadays Wide range of telecommunication services including advanced mobile services supported by mobile and fixed networks, which are increasingly packet based, along with a support for low to high mobility applications and wide range of data rates for multiuser environment are provided by 4G wireless standard LTE (Long Term Evolution). For the next generations of wireless technology will be required to achieve as much as a thousandfold throughput increase over the current 4G systems. This can be achieved through different physical layer techniques such as a use of massive number of antennas and the use of centimeter and millimeter wave spectrum among others. In addition to this, more sophisticated transceiver architecture is required to increase the throughput with the physical layer techniques. In band full duplex technology will double the spectral efficiency. This transceiver architecture will help to reduce the demand from applications such as machine to machine communications called Internet of Things (IoT). To simulate the full duplex transceiver architecture using XILINX ISE 14.7. The simulated results produces increased throughput with reduced delay.
Keywords5G, FDD, LTE, Inband full duplex transceiver, IoT, Peak service rate, digital self interference cancellation, spectrum efficiency, throughput, VLSI signal processing

INTRODUCTION
The wireless cellular networks of 4G LTE technologies are having great communicational technologies globally. Most of the devices communicate each other via broadband wireless networks because of the advantages of wireless connectivity. This will helps to motivate the major manufacturers and mobile network operators for the development of LTE and LTEAdvanced standards. The road map from LTE to LTEAdvanced is illustrated in Fig.1.
Fig.1. Road map from LTE to LTE Advanced
Signal processing is the most important role in the wireless technology. There are more number of signal processing techniques will be used in next wireless technology of 5G in order to increase the peak service rates, and also greatly increasing capacity, coverage, compatibility, reliability, convergence and efficiency in terms of both power and spectrum. In order to design the more sophisticated transceiver to increase the throughput, Inband fullduplex technology can be used to double the spectrum efficiency (bit/second/Hz) and it helps to reach the 5G standard with full potential [1].
The LTEAdvanced networks use cellular bands from 600 MHz to 3.5 GHz. The new frequency bands above 6 GHz (upto 100GHz) including the so called millimeter (mm) wave bands are expected in 5G. The standardization process for 5G is also expected to play a crucial role for the commercial success in the upcoming year [2].
Fig.2. LTE FDD Spectrum Allocation
Full duplex means that Bidirectional Communication, the device can transmit and receive at the same time over the same frequency. This will be used in 5G to reuse radio resources simultaneously for access and backhaul. The implementation of full duplex is the selfinterference (SI) signal (i.e.).the part of the transmitted signal that leaks into the receiver chain.
Fig.3. Inband full duplex

SELFINTERFERENCE
The Transmitter Leakage that the signal leaks from the device transmitter to its own receiver. It will become an serious issues in decoding the desired signal, which could be noisy with a dramatically affected Signaltonoiseratio (SNR). In order to achieve the best performance of a full
duplex system, the Self Interference (SI) signal has to be suppressed to reach the receivers noise floor. There are several SI cancellation methods are described in the current scenario.
The unavoidable SI in the full duplex transceiver limits the throughput, when the transmitted signal couples back to the receiver. Even though the transmitted signal is known in the digital baseband, it cannot be eliminated completely in the receiver because of Radio Frequency (RF) impairments [3] and large power difference between the transmitted and received signals. Cochannel Interference is also a dominant issue than SI. So it is the most challenging task to realize the higher levels of SI cancellation as the required isolation bandwidth is greater and also cause multipath scattering. It is possible for SI cancellation with multi antenna in full band radio transceivers by the use of non linear adaptive SI cancellation algorithms.
While it simultaneously receives signal vector in Equation (5)
(5)
The output creates an unavoidable SI feedback loop
from the transceiver output to the transceiver input through
channel shown in Equation (6)
(6) Spatial interference suppression is provided by the
precoding matrix and beamforming matrix and
is used to subtract the contribution of the transmitted
signal form the received signal for the purpose of
cancellation. The corresponding received signals in the transceiver and in the destination node can be expressed in Equations (7) and (8).
= ( + ) + (7)
= + (8)
Equations (9) and (10) are additive noise vectors in the
transceiver and in the destination ( )
.
(9)
(10)
Fig.4. A multiantenna radio transceiver

DIGITAL SELF INTERFERENCE CANCELLATION ALGORITHMS

Signal Model
The baseband model of a communication link of a communication link with full duplex transceivers is shown in the Fig.1. It shows that the system includes bidirectional communication (source and destination are the same node). Here the full duplex transceiver acts as a relay link and it is simultaneously serving an uplink user and a downlink user in the same frequency band.
Where, As Source transmit antennas and AD destination receive antennas. Atx transmit antennas and Arx receive antennas. These two antenna arrays are spatially separated and the model is applied to the single array design [4][5].
Equation (1) for the MIMO channels from the source to the transceiver.
(1)
Equation (2) for the MIMO channels from the transceiver
to the destination.
(2) At the time n, the source transmits signal vectors in
Equation (3)
(3)
At the time n, the transceiver transmits signal vectors in
Equation (4)
(4)
Here the signal is capable of modeling multipath MIMO
channels in the time domain with arbitrary modulation.

Basic Principles
Digital cancellation techniques includes the SI signal is generated and then subtracted from the received signal. But here we can apply spatial suppression if transmitter and receiver antennas are spatially separated. This requires multiple antennas in both ends, at the transmitter side precoder is used and the receiver side beam former is used to simultaneously attenuate the SI signal and receive the payload signal. In order to attenuate the effect of RF imperfections RF eam former is used, because they pass through the same channel together with the known part of the SI signal.
This may cause interference in the system, to make a nearly interferencefree system, the proper cancellation method is used for each application. When both transmit and receive sides of the fullduplex device behave primarily like a linear filter, cancellation can be reduced to designing a filter that identifies the SI channel, since the transmitted signal is known at every time instant. Any linear cancellation architecture cannot mitigate nonlinear behavior and noise sources, such as nonlinear distortion of the PA, I/Q imbalance during modulation/demodulation, phase noise, or quantization noise at the receiver [6][7][8][9]. So we use the nonlinear architecture for full duplex transceiver architecture. Here digital mitigation is performed in both the time domain and the frequency domain.
The mitigation in the frequency domain involves the processing of each subcarrier signal individually, which may cause the computational demand if the number of subcarriers
is large. On the other hand, mitigation in the time domain involves processing the signal samples independently of the number of subcarriers, but, due to the different interference paths between antennas, requires gauging the delay spread of the SI channel [10]. Mitigation takes place after baseband demodulation and digital conversion of the received signal, usually being the first operation within the digital pipeline. As a result, the employed signal must be sampled above the Nyquist rate, which demands the use of special techniques to deal with arbitrary signal spectra [10].

Spatial suppression
Spatialdomain suppression [11] employs receive and/or transmitside feed forward filters, namely Grx[n] and Gtx[n], which are matched to the SI channel alone without relying upon accurately knowing actual signals. This is in contrast to the feedback filters used in subtractive cancellation for generating an estimated copy of the SI signal from the imperfectly known transmitted signal. Nevertheless, spatial suppression can similarly mitigate SI; the pros and cons are weighed up next, when we compare the approach to time domain cancellation.
In principle, suppression works by employing beam forming filters that direct reception and/or transmission of the signal of interest to the null space of the SI channel such that signal propagation is ideally blocked completely or, if the spatial degreesoffreedom are scarce, to the weakest Eigen modes thereof such that the effective gain of the residual feedback channel is minimized. Mathematically this means solving in terms of some suitable matrix as in Equation (11)
(11)
min  [] [] [] = 0
processing without any need for modeling or implementing complex transceiver electronics, in contrast to analog or non linear digital cancellation. Transmitside beam forming will conversely suppress SI ontheair before it even reaches the receiver front end such that problems related to limited ADC dynamic range and quantization noise are alleviated. In Equation (13)
min  [] [] = 0 (13)
Thus it is also beneficial to employ spatialdomain
suppression together with linear timedomain cancellation such that the latter efficiently eliminates the linear signal components and then takes care of the residual nonlinear distortion components in an economic way.


NONLINEAR CANCELLATION
The different RF impairments distort the observed SI signal such that it is no longer a linear transformation of the original TX signal. This means that nonlinear modeling is required to fully grasp the effects of the effective SI propagation channel, which includes various sources of nonlinear distortion. Nonlinear effects, such as amplifier distortion or mixer nonlinearities, can be accurately modeled using polynomialbased systems [12, 13, 14], whereas I/Q imbalance can be modeled using widely linear filters [24], which have been extensively studied in the literature.
As a starting point, the baseband signal of TX j (j = 1, 2,.
. . , Ntx) is denoted by xj (n). The first component distorting the TX signal is the I/Q modulator, [14] which will inherently introduce some I/Q imbalance. The output signal of the I/Q modulator model (using a frequencyindependent model for simplicity) is in Equation (14)
Such a mitigation approach is therefore applicable only
=
+
(14)
with multiantenna transceivers, and having low rank in the
1,
2,
SI channel can boost suppression performance significantly. Likewise, beamforming always consumes the degreesof freedom, restricting the tradeoff between spatial diversity and multiplexing in the signals of interest, which can be seen as reducing the effective number of antennas used for data transmission if suppression is implemented transparently around actual en/decoding blocks. Suppression is also obviously sensitive to estimation error in feedback channel state information, not so unlike cancellation. However, the residual interference signal is not linearly proportional to the error term or its gain level because estimation error manifests itself as distorted beam patterns.
The main benefit of suppression over cancellation is the fact that it mitigates blindly all signal, distortion and noise components that pass through the loopback SI channel. Such a receive filter satisfies the Equation (12)
min  [] [] = 0 (12)
1, = 1/2(1 + exp( )) (15)
2, = 1/2(1 exp( )) (16) where , are the gain and phase imbalance parameters of TX j. Notice that for any practical TX front end 1, 
2, . The strength of the induced I/Q image component,
represented by the conjugated signal term in Equation (14), is
typically characterized with the image rejection ratio as
10 10 (1, 2 /2, 2 ).
The output signal of I/Q modulator is then fed to the TX
PA, which will further distort it. A common approach is to use polynomials to model the nonlinear distortion produced by the PA. In brief, polynomialbased systems model nonlinearities by processing higherorder terms of the input signal. Typically, a parallel Hammerstein (PH) model with polynomial branch nonlinearities and FIR branch filters is assumed for the PA. Using the PH model, the output signal of the PA can be written as in Equation (17).
This means that all the adverse transmitside
= =1
, (
components caused by nonlinear RF imperfections are suppressed at the receiver side together with the linear signal
=0
) (17)
components, no matter how large the transmitters EVM is Yet suppression is achieved with simple linear digital signal
where M and P denote the memory depth and
nonlinearity order of the PH model, , denote the FIR
filter impulse responses of the PH branches for TX j, and the basis functions are defined as in Equation (18).
p is the antenna port index, the process is according to Equation 1 and 2.
+1
1
0 ) + Im(0) j for i = 0 , , 1 (1)
= 1 = () 2 () 2 (18)
d2i =Re(
1 1
2
In general, the number of parameters of a Hammerstein model grows linearly with order P, while in the MIMO case, the increase is also relative to the number of TX and RX
d2i + 1 =Re( ) + Im( ) j for i = 0 , , 2 1 (2)
where N is the length of input complexvalued symbols
and () and ()re generated according to Equation 3,
antennas [14]. The PH nonlinearity is a widely used
nonlinear model for direct as well as inverse modeling of
4,5and 6.
(0)
(1) = 0 , 1 (3)
PAs and has been observed, through RF measurements, to
0 =2
+ 2+1 2
characterize the operation of various PAs in an accurate
(1)
(0)
2+1
manner [15].
1 = 2
= 0, ,
2
1 (4)
0=(0) (1) = 0, , 1 (5)
Using Equation [14] and [17], the overall output signal
2
2+1 2
1 =(1) + (0) = 0, , 1 (6)
of the TX can be expressed as
2
2+1 2
=
(
) (17)
=0 ,
=1

Layer Mapping
The Layer mapping process maps the complex valued modulation symbols onto each layer used for transmission. Two layers are used to carry modulated transmit code words with transmit diversity. Transmit diversity is used to separate one source signal into two or more independent signals. The use of transmit diversity is implied when using DCI format 1A [6].

Pre Coding
The vectors x(i)= [ 0 1 () ],i= 0,1,.., 1 is the input block of the precoder from the Layer mapping and
generates a block of vectors y(i) = [ () ] , i = 0,1,.., 1 to be mapped onto resources on each of the antenna ports, where () repersents the signal for antenna
port p.

Mapping to Resource Elements
The RE mapping process maps complexvalued modulation symbols for each antenna port to corresponding REs on resource grids. All REs are mapped in terms of Resource Element Groups (REGs)[8]. Every four REs available for mapping L1/L2 control signals forms a REG. Each REG is mapped with a symbol quadruplet which consists of 4 complexvalued symbols. This mapping method is used to support transmit diversity.

PCFICH Receiver
The receiver part of the PCFICH from the channel including the reverse process of transmitter part block and get the original CFI value are discussed below.

Layer Demapping and Deprecoding
The layer demapping and deprecoding returns the block
()

Demodulation
The BPSK demodulation generates a block of bits
= 0,1, , 1 where N is the length of input block of symbols di. The BPSK demodulation process is according
to Table III
TABLE III BPSK demodulation lookup table
di
1 + 1
0
1 1
1
0
0
The QPSK demodulation generates a block of bits
= 0,1, ,2 1, where N is the length of input block of symbols di[11].The process has hard decision type
and soft decision type. The hard decision process returns the bit sequence with value 0 or 1 and is used for PCIFCH demodulation. The hard decision process is done according to Table IV.
Re(di)
Im(di)
bi , bi+1
0
0
00
0
< 0
01
< 0
0
10
< 0
< 0
11
Table IV Hard decision QPSK demodulation
of symbols di. After layer mapping and precoding
, where

Descrambling

The descrambling process is the reverse of scrambling process which returns the unscrambledbit sequence bi from scrambled bit sequence Bi. The process is as defined by the Equation 7.
Bi = (Bi + ci )mod2 for i=0,, L1 (7)
WhereL is the length of Bi and ciis the scrambling sequence, generated as described in the Section 1.2.
IV PCFICH ARCHITECTURE
The Architecture flow of the PCFICH is drawn based on the blocks present in the block diagram. The flow of this diagram is fully based on the DSP. This can be made efficient using the various VLSI concepts like unfolding and retiming. Here both of the conceptsare used to achieve the efficient architecture.
Fig.4 PCFICH Transmitter architecture

PCFICH Transmitter Architecture
The transmitter architecture of PCFICH downlink physical control channel is presented in Fig.4. The block diagram of the PCFICH transmitter is discussed in the chapter III.The first block of this architecture is block coding.
The input of this block code is the 2 bit CFI value R1 and R0. The 2 bit value is converted into 32 bit value by block coding.The first two bits are same as the original bits and the third bit is the XOR value of the first two bits. The 3 bit pattern is repeated until the required 32 bits are obtained[10]. It is represented in Fig.5. These 32 bits form the CFI codeword.
The second block is the scrambling process. This process requires gold sequence generation. The gold sequence is
produced by using the two sequences 1 and 2. Here the x1
sequence is the predefined sequence
i.e,10000000000000000000000000000000. The 2
sequence also have 31 bits that is assumed according to the
applications. The 32ndbit of both sequences are calculated using Equation (8),(9) and (10). Then these 2 sequences are XORed to get the gold sequence. The result is also a 32 bit value.
1 + 31 = 1 + 3 + 1 2 (8)
2 + 31 = 2 + 3 + 2 + 2 + 2 + 1 + 2() 2 (9)
= (1 2() )2 (10)
Then scrambling is done by XOR of the block coded
sequence and the gold sequence. It is shown in Fig.6
SCRAMBLING
BLOCK CODE
GOLD SEQUENCE
Fig.6 Scrambling process
The resultant scrambled sequence isstored in a shift register. The shift register is set to shift 2 bitsper clock cycle for QPSK modulation. The shifted 2 bits aregiven as control lines for the multiplexer. The inputs to themultiplexer are stored in RAM table. There are 4 possible complexmodulated QPSK symbols. Based on thecontrol, the output appears, which is represented as 16 bitvalue.
The 16 complex modulated symbols are then layer mappedto one, two or four layers based on the information fromhigher layer.Z1 is the output if one antenna is selected.Z2,Z3are outputs if 2 antennas are selected and Z4,Z5,Z6,Z7 if 4antennas are selected.
The modulated symbol is multipliedwith the complex channel frequency response vector hk, whichis also represented as a 16 bit value. The resultant is a 32 bitvalue. Then noise which is represented using 16 bits is added.Thus the resultant signal yk is a 32 bit value.

PCFICH Receiver Architecture
The received signal is demapped from the 16 positions of first OFDM symbol, where CFI value is available. The receiver architecture is presented in Fig.7. It is known that, there are only three possibilities of signal transmitted, namely01,10 or 11(CFI1,2 or 3)[12].So, the demodulated signal will be one among the three. The received signal is yk and is multiplied with the conjugate of the complex channel
frequency response vector , element by element. Then
thisresultant term undergoes inner product with the three
possible values of d(m). The inner product is done using.
32
Block code
2
R0
R1
CFI
codeword
The d(m)* is multiplied with (0 ) product .For allthe
2
Fig.5 Block code
elements the multiplication is done and the results
areaccumulated, and the result is a 64 bit value[13]. The real part of accumulated value alone is taken, which is a 32 bit value.
This process is done for the three values viz. d(0),d(1),d(2).Then among the three results, the codeword which has the maximum argument value is detected as the CFI.
= argma =1,2,3 ( ) (13)
Where the soft outputs are given by
( )
In the receiver side, after removal of cyclic prefix from the received signal, then FFT is performed and then resource element demapping is done. The complex valued output at
( ) = =1
Which is simplified as
for m = 1,2,3 (14)
the kth receive antenna is modeled in Equation(11)
CFI =argmax
0 ( )
= 0
()
+ , = 1,2, , (11)
=1,2,3
=1
(15)
4.2 Received Signal
k
The received signal y kis element by element multiplied with the conjugate of the complex channel frequency response vector h *.Then this term and three possible values of d (m) undergoes inner product. The inner product is given in Equation (16)
, = =1
(16)
Fig.7 PCFICH Receiver architecture
ykis 16×1 received subcarrier vector, d(n) is the 16x1complex QPSK symbol vector corresponding to the 32 bit CFI code words, where n varies from 1 to 3, hkis 16x1complex channel frequency response and uk represents the contribution of thermal noise and interference.
The received signal yk is represented in the figure 2,for single antenna case. The noise term ukis modeled as zero mean circularly symmetric complex Gaussian with
The real part of the resultant value is taken. This is done
for number of times as the number of antennas used to receive. Then argument max among the three values is selected as the CFI value. If CFI is maximum value when m=1, then the codeword detected is 01, when m=2, it is 10 and when m=3, it is 11.

UNFOLDING AND RETIMING
5.1 Unfolding
Unfolding = = Parallel Processing
In a Junfolded system each delay is Jslow. if input to a delay element is the signal x(kJ + m), the output is in Equation (16)
2
covariance = ,since the interferers are
uncorrelated due to independent large scale propagation,
short term fading and uncorrelated scrambling sequences.
4.1CFI Estimation
The ML decision rule, by maximizing the loglikelihood function of yk and hkis given in Equation (12)
x((k1)J + m) = x(kJ + m J) (16)
Algorithm for unfolding
For each node U in the original DFG, draw J node U0, U1,U2, , UJ1
For each edge U V with w delays in the original DFG, draw the J edges UiV(i + w)%J with [(i+w)/J] delays for i= 0, 1, , J1.
0 2
CFI = min
=1,2,3
=1
(12)
Unfolding of an edge with w delays in the original DFG
Which simplifies to
produces Jw edges with no delays and w edges with 1delay
in J unfolded DFG for w < J and unfolding preserves precedence constraints of a DSP program[14].
Properties of unfolding :
Unfolding preserves the number of delays in a DFG. Thiscan be stated as follows(17),
–
(17)
5.2 Retiming
This section considers some techniques used for retiming.
First, two special cases of retiming, namely, cutset retiming and pipelining, are considered. Two algorithms are then considered for retiming to minimize the clock period and retiming to minimize the number of registers that are required to implement the circuit.Cutset Retiming is a useful technique that is a special case of retiming. A cutest is a set of edges that can be removed from the graph to create 2 disconnected subgraphs. Cutset retiming only affects the weights of the edges in the cutset. If the 2 disconnected subgraphs are labeled G1 and G2, then cutset retiming consists of adding k delays to each edge from G1 to G2 and removing k delays from each edge from G2 to G1. For example, a cutset is shown with a dashed line in Fig. 4.4(a). The 3 edges in the cutset are 2 1, 3 2, and 1 4. The 2 subgraphs G1 and G2 found by removing the 3 edges in the cutset are shown in Fig.8. For k = 1, the result of cutset retiming. The edges from G1 to G2 are 3 2 and 1 4, and one delay is added to each of these edges[15]. The edge from G2 to G1 is 2 1, and one delay is subtracted from this edge[7].

RESULTS AND DISCUSSION
6.1 Simulation result for PCFICH
The each and every block of the PCFICH downlink physical control channel is simulated using the Xilinx ISE
14.7 software.Verilog Hardware description language (VHDL) is used to simulate the codes for each and every block for PCFICH transceiver with unfolding and retiming approach for efficient architecture. The CFI is detected as the output of the after 15 time units.

Block coding
The input of the block code is 2 bit and the output of this block code is 32 bit. It is analyzed based on the CFI present in the system and also depicted according to the application. The simulation waveform for the block code is depicted in the Fig.9.
Fig.9 Simulation result for Block coding

Scrambling and Descrambling
The input of the scrambler block is 32 bit and the output of this scrambler block is also 32 bit. Here 31 gold sequence also generated using the cell specific sequence generator. It was analyzed based on the CFI present in the system and also depicted according to the application. The original CFI value is get back in receiver. The simulation waveform for the block code scrambling and descrambling is depicted in the Fig.10.
Fig.10 Simulation result for scrambling block

QPSK Modulation and Demodulation
The output of the 32bit scrambling sequence is given to the input of the QPSK modulation and the reverse process is the QPSK demodulation and the simulation result for QPSK modulation and demodulation is shown in Fig.11.
Fig.11 Simulation results of QPSK modulation and demodulation

PCFICH Transceiver Output
The entire block of the transceiver architecture coded and combined as the consequence of output to get the simulation result as in Fig.12.
Fig.12 Simulation results of PCFICH Transceiver

Unfolding and Retiming
The Output of the PCFICH transceiver is fed into the unfolding and retiming process to get the efficient output of minimum delay and maximize the efficiency. It is shown in Fig.13.
Fig.13.Simulation results of Unfolding and Retiming VII CONCLUSION
This paper describes about simulated results of each
and every block of the transceiver architecture. The output of the entire block is combined and the total output of the system in the receiver side is getting the CFI value. This output will have larger delay due to the channel noise and architecture flow. The unfolding concept is used at the CFI of the receiver architecture to reduce the delay and power consumption. The retiming is also used to reduce the number of registers present in the architecture. The output of the normal architecture will give the best result of time delay of 5 time units. The increased efficiency of architecture is 1.44. The overall architecture result produced in our paper creates the better performance than the previous one. In future work the proposed work will be extended to minimize the number of delays by the use of any other VLSI DSP concept techniques.
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