# Low Power Matrix Multiplier based on Shift Logic and Adder Tree

DOI : 10.17577/IJERTV11IS050289

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#### Low Power Matrix Multiplier based on Shift Logic and Adder Tree

Jeslin Rose V

Electronics and Communication Engineering Department IES College of Engineering

Thrissur-Kerala, India

Suvitha P.S

Assistant Professor

Electronics and Communication Engineering Department IES College of Engineering

Thrissur-Kerala, India

Abstract Approximate computing is a modern method for energy efficient design of electronic circuits and systems. In older days, the device uses a conventional method, that is, approximate computing of inputs that helps to speed up the device. But in this modern world, the use of electronic devices increases day by day and there is a need of increase the speed of the device than before by controlling the power consumption and also minimization of the size of the device as much as possible. Here we propose a low power rounding based approximate multiplier (RoBA Multiplier) that is high speed yet energy efficient. In this approach the input values are rounded to the nearest exponent of two. This way the computational intensive part of the multiplication, that is, the bit by bit multiplication of input, is eliminated and improving speed and energy consumption with a small percentage of error. The efficiency of the proposed multiplier is evaluated by comparing its performance with those of the conventional approximate multipliers using different design parameters. Both signed and unsigned inputs are accepted by this system. Here the multiplier is designed based on a shift logic and adder tree. In conventional method the fixed width adder tree is formed from the full width adder tree design. But in this case, a novel scheme is presented to obtain fixed-width AT design using truncated input. A probabilistic approach based on an estimation formula is presented to compensate the error. The simulations are done by the tool modelsim se 6.3f.

KeywordsShifters and adders; rounding ; shifting of rounded inputs; approximate multiplier

1. INTRODUCTION

Nowadays every action of human being requires much better speed and accuracy than previous conventional methods. This is also affects the image processing industry and it leads to invention of novel methods for image processing applications[1]. Generally, the matrix multipliers are used to image processing applications such as image smoothening or image sharpening. The objective of this project is to construct an efficient matrix multiplier to improve speed and efficiency thereby reduce the area consumption. Here we go for approximate matrix multiplier which reduce area and power of adders and multipliers. In conventional method the original image is multiply with a sharpening or smoothening matrix in order to get proper sharpened or smoothened image[2]. Approximate computing is a new method for energy efficient design of circuits and systems. It enables highly efficient hardware and software implementations by exploiting the challenges that faces. In this, hardware implementation of Matrix Multiplier is done by VERILOG Hardware Description Language (HDL). Also

using adders and multipliers together for approximation provides better control of error percentage.

Approximate computing is an efficient method for low power and high speed electronic devices. This type of matrix multiplier consists of two operations: lower part OR adder operation and matrix multiplication operation. The multiplier reaches its final result by two procedural steps. The first step is that Partial Product Generation by employing bit by bit multiplication. The second step is that Summation of the partial products and generating the final result. It presents how to approximate computing can bring a significant improvement in the process of matrix multiplication by introducing a negligible amount of error [3]. But in this method the bit by bit multiplication process takes more time and area hence there will be an amount of power loss also. To avoid this problem here introduces a new multiplier which is RoBA multiplier (rounding based approximate multiplier) [4]. All the inputs are rounded to the nearest exponent of 2 and then shifters are used to take multiplication operation. Instead of bit by bit multiplication shifters and adders are used and thereby reduces the total area and power consumption and also speed up the overall performance of the device.

2. APPROXIMATE MATIX MULTIPLIER

Every image processing application includes the operation matrix multiplication for the accurate and speedy processing of images and the modern technology suggests a novel method for image processing that is approximate computing.

1. Approximate Computing

In this method of matrix multiplication, the multiplier consists of two blocks. The first block is an approximate multiplier block and the another one is an approximate adder block. The approximate multiplier block performs the bit by bit multiplication, that is, partial product generation and the approximate adder performs the summation of the partial products. In approximate computing, the approximation will be done only at the LSB part because, approximation in LSB does not effects the output and the application of the device.

2. Approximate Multiplier and Approximate Adder

The approximate multiplier can be divided into two different category of blocks. This two blocks can be described with the famous Wallace tree multiplier Fig. 1, which consists of accurate and inaccurate block.

Fig. 1 Wallace Tree Multiplier

Here the inaccurate block employs the approximation technique because the approximation in the LSB does not affect the overall output of the device. The accurate block employs as Wallace tree technique. Mainly the approximate multiplier process two steps of operation ie,

• Generate partial products through bit by bit multiplication.

• Add up the partial products to get final result.

In the case of approximate adder, as similar to the approximate multiplier, it also can be categorized to accurate and inaccurate blocks.

Fig. 2 shows the approximate adder, right-side block referred to as inaccurate block which is used to obtain LSB and left side block is accurate block which is used to obtain MSB. The inaccurate block works as simple bit by bit OR addition and the carry will be neglected. The accurate block employs as a

ripple carry addition for the accuracy of the output. Fig. 3 shows RTL schematic of a 3×3 approximate matrix multiplier. The drawback of this method is, for the generation of partial products, we use a huge amount of multipliers and

adders and thereby a drastic change in area of the device hence the device undergoes for a power loss.

Fig. 3 RTL Schematic of Approximate Multiplier

3. PROPOSED MATRIX MULTIPLIER

According to above mentioned drawbacks of the approximate multiplier, here proposes a new matrix multiplier which is more efficient than the approximate matrix multiplier. A rounding based approximate multiplier (RoBA), in which all the inputs are rounded to the nearest exponent of 2 and then go for some shifting operation that is similar to the multiplication operation.

A. Block Diagram

To elaborate on the operation of the approximate multiplier, first, let us denote the rounded numbers of the input of A and B by Ar and Br, respectively. The key observation is that the multiplications of Ar Ã— Br, Ar Ã—B, and Br Ã—A may be implemented just by the shift operation. The proposed multiplier, which had high accuracy, was based on rounding of the inputs in the form of2n.

Fig. 4 Block Diagram of RoBA Multiplier

A sign detector and a sign set are given at two ends of the operation respectively. Fig. 4 shows the block diagram of a RoBA multiplier and fig. 5 shows the complete architecture

of the RoBA multiplier. This method reduces the overall power loss and area consumption hence increases the speed of the system. Comparatively the error in the approximate computing will be reduce in RoBA multiplier. The key observation is that the multiplications of Ar Ã— Br, Ar Ã—B, and Br Ã—A may be implemented just by the shift operation. The final expression for the RoBA multiplier will be given below:

Fig. 7 Simulation Result of RoBA Multiplier

Fig. 5 Complete Architecture of RoBA Multiplier

4. EXPERIMENTAL RESULTS

In this section, experimental results of the approximate matrix multiplier and the suggested RoBA multiplier both are simulated and synthesized using Xilinx and modelsim SE 6.3F. The complete simulation result of both multipliers are given in Fig. 6 and Fig. 7 respectively.

Fig. 5 Simulation Result of Approximate Multiplier

Both signed and unsigned numbers are processed in this multiplier. A small percentage of error occurs at the output. As compared with the RoBA multiplier approximate multiplier has greater error value. Also the use of components is less in RoBA multiplier hence reduce the area. As a result, the overall power loss will be reduced in RoBA multiplier.

Fig. 8 Image sharpening using the proposed approximate architecture (a) Original image. Image sharpening utilizing (b) exact multiplier (c) Approximate multiplier (d) RoBA multiplier

5. CONCLUSION

we all know the importance of matrix multiplication in the image processing field. The requirement of smooth and fast image processing with less power loss can be satisfied by the proposed matrix multiplier. Also the RoBA multiplier uses less number of components than the existed one hence we can reduce the overall size of the system. The main advantage of the proposed system is; it reduces the computational complexity of the system by using shifters instead of bit by bit multiplication. This type of approximate multiplier exhibits high accuracy and efficiency.

REFERENCES

[1] A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing By Reza Zendegani, Mehdi Kamal, Milad Bahadori, Ali Afzali-Kusha, and Massoud Pedram IEEE transactions on very large scale integration (vlsi) systems

[2] Efficient Design for Fixed-Width Adder-Tree Basant Kumar Mohanty, Senior Member, ieee eee transactions on circuits and systems-ii, express brief

[3] Approximate Computing: An Emerging Paradigm For Energy- Efficient Design Jie Han and Michael Orshansky 2013 18th IEEE European Test Symposium (ETS)

[4] Study of Approximate Multiplier with Different Adders Proceedings of the International Conference on Smart Electronics and Communication (ICOSEC 2020) IEEE Xplore Part Number: CFP20V90-ART; ISBN: 978-1-7281-5461-9 by Neema Zacharias and Prof. Lalu V.

[5] Improved High Speed Approximate Multiplier by T.Roshini, R.Sai Krishna, P.Kaushik Reddy, M.Vinodhini Department of Electronics and Communication Engineering

[6] Low Power, High Speed Error Tolerant Multiplier Using Approximate Adders by Manikantta Reddy K , Nithin Kumar Y.B., Dheeraj Sharma

, Vasantha M.H.

[7] Performance Analysis of Wallace Tree Multiplier with Kogge Stone Adder using 15-4 Compressor by A.Sundhar, S.Deva tharshini, G.Priyanka, S.Ragul and C.Saranya International Conference on Communication and Signal Processing, April 4-6, 2019, India

[8] Low-power and Area Efficient Approximate Multiplier with Reduced Partial Productsby Mukesh Kumar Sukla, Kabiraj Sethi and A K Panda 2020 IEEE VLSI Device, Circuit and System Conference (VLSI-DCS), 18-19 July, 2020, ED MSIT SBC, Kolkata, India