Low Power and Area Efficient Reconfigurable FIR Filter

DOI : 10.17577/IJERTV6IS110149

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Low Power and Area Efficient Reconfigurable FIR Filter

1 M. Dasharatha

Electronics and Communication Engineering Department,

UCE, Osmania University, Hyderabad, Telangana State, India.

2 B. Rajendran Naik

Electronics and Communication Engineering Department,

UCE, Osmania University, Hyderabad, Telangana State, India.

3 N. S. S. Reddy

Electronics and Communication Engineering Department, VCE, Osmania University,

Hyderabad, Telangana State, India.

Abstract: Multiplication of input sample and impulse response. Direct form and interchangeable form implementations are two forms of FIR filter implementations. Instead of direct form, transposed form is most effective. The Multiplication process takes place in multiplier block. Thus transposed form multiplier blocks in FIR filter will replace by MCM architecture also known as shift and add architecture.

Keywords:-Verilog,Multiple-Constant Multiplication(MCM), Finite Impulse Response, Low Complexity, Distributive Arithmetic(DA)


In digital signal processing (DSP) systems finite impulse response (FIR) filters have very much importance since their characteristics in linear-phase and feed-forward implementations make them very useful for building stable high performance filter architectures. The direct and transposed form FIR filter logic diagrams are illustrated in Fig.1(a) and 1(b). As shown in figure both architectures have similar complexity in hardware, and the performance and power efficiency.



Fig.1. Design of FIR filter. (a) Direct form (b) Transposed form with generic multipliers.

The architecture of a multiplier of the digital FIR filter in its rearrangeable form is shown in [Fig. 1(b)], where the multiplication of filter inputs with the filter coefficients is accomplished, due to the significant impact on the

complexity and performance of the design because a huge number of constant multiplications are essential. This is generally known as the multiple constant multiplications (MCM) operation and is also a central operation and performance bottleneck in many other DSP systems such as fast Fourier transforms, discrete cosine transforms (DCTs) and ECC codes.


    Filters are usually frequency selective networks, which is capable of modifying an input signal in order to facilitate further processing. Thus digital filters are more preferred than analog due to its high signal integrity [2]. An FIR filters are mainly applied for different DSP areas because providing virtues of linear phase and system stability. The basic convolution equations of filter representation are shown as follows:

    Y(n) = b0x(n) +b1x(n-1)++bNx(n-N) (1)

    = (2)

    Distributed Arithmetic is termed so because the multiplications that appear in signal processing are reordered and combined such that the arithmetic becomes distributed completely through the structure rather than being lumped. Multipliers are replaced by combinational Look Up Tables (LUT) [3]. Since LUTs are considerably larger in size, the property of materialize the FIR filter primarily relies upon the performance of logic synthesis algorithm mapping to FPGA.

    DA provides bit serial operations that implement a series of fixed point MAC operations in a known number of steps, regardless of number of terms to be calculated. The main operations required for DA based computation of inner product are sequence of lookup table access followed by shift accumulation operations of LUT output [9].

    According to DA, we can make look up tables (LUT) to store MAC values and call out values accordingly to the input data if necessary. Therefore, LUTs are utilized

    to facilitate the operations of MAC units so as to save hardware resources. This technique also promotes DA computation suitable for FPGA recognition, because the LUT along with shift and add activities can be directly summerized to LUT base FPGA logic structure.

    The convenience of DA is its efficiency of mechanization. Itbring out well when the number of ingredients in a vector is nearly same as word size then DA is really fast.


Distributed arithmetic is a famous method of implementing FIR filters without the use of multipliers. In DA the task of summing product terms is replaced by table lookup procedures that are easily implemented on FPGA.

In FIR filtering, one to one diagrams of the scrolling sequences are from two sources, one obtained from input samples while the other sequences are accomplished from fixed impulse response coefficients of filter [6]. This behavior of FIR filter makes it suitable for DA based technique for memory realization. It yields faster output, it stores pre-computed partial results in memory components that can be read out and accumulated to obtain desired result [8].

(a) (b) (c)

Fig.3:Shift-adds implementation of 29x and 43x (a) Without partial product sharing and with partial product sharing


The design have been implemented using Verilog Hardware description language and simulated and synthesized using Xilinx ISE simulator. The synthesis results obtained are targeted for SPARTAN 3E XC3S250E FPGA.

Fig. 4: RTL Schematic for Reconfigurable FIR Filter

(LUT), Shifters and accumulator with adder tree. In this technique all the partial product outputs are pre- of FIR filter consists of Look-Up Table computed and placed in a Look Up The Distributed Arithmetic technique Table (LUT). These table entries are addressed by the addresses generated by input multiplier bit data. All inputs are fed simultaneously. From the input data, address will originated and allowed to connect the LUT; its outcome is merged to the accumulated partial products.

Fig 2:Block diagram of FIR filter using DA

The Basic block diagram for FIR filter implementation using DA [8] is shown in Figure 2. The complete dot product calculations takes L clocks where L is the size of input data, and it is not depended on input data size. During the initial cycle of operation, the Least- Significant Bits of input i.e., X0(n), X0(n-1), of the K input samples are arranged to form K-bit addresses. These addresses are allowed to access Look-Up Table and that table outcome becomes the initial value of the accumulator. During the very next cycle of operation, the next-to-least significant bits X1(n), X1(n-1), …, X1(n-K+1) of the K input samples are arranged to form K-bit address which will be allowed access lookup, and the adder sums the Look up Table output is shifted by one bit and summed to the contents of the accumulator.

Fig. 5: Simulation results of a Reconfigurable FIR Filter

Table 1: Comparison of Area of existing and proposed











Area in terms of Slices

Proposed system Existing system



Fig 6: Area in terms of SLICEs for a proposed and existing system

Power Dissipation

Proposed system Existing system

57 mw

55 mw

Fig 7: Power dissipation of proposed and existing system


The proposed architecture shows the area conducive implementation of Digital filter using DA based on FPGA. This architecture replaces the complicated multiplication- accumulation operation with simple shifing and adding operations based DA algorithm which is directly applied to realize FIR filter. The simulation results have been observed by Modelsim simulator. Also synthesized by XILINX XST tool and targeted for SPARTAN 3E FPGA device XC3S250E. Device utilization values of both algorithms are compared. We have examined up to 50% diminishing in the number of pieces and up to 75%shrinkagen the number of LUTs for fully parallel applications.


  1. Kenny Johansson, Oscar Gustafsson, Andrew G. D., and Lars Wanhammar, Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic IEEE MELECON, pp. 197-200, 2004.

  2. LeventAksoy, Cristiano Lazzari, Eduardo Costa,Paulo Flores, José Monteiro., Efficient shift-adds design of digit-serial multiple constant multiplications GLSVLSI11,2011.

  3. Sang Yoon Park Member, IEEE Efficient FPGA and ASIC Realizations of DA-Based Reconfigurable FIR Digital Filter IEEE transactions 2014 on circuits and systems-ii: express briefs.

  4. P. Karthikeyan, Dr. Saravanan.R FPGA Design of Parallel Linear- Phase FIR Digital Filter Using Distributed Arithmetic Algorithm IJCSMC, Vol. 2, Issue. 4, April 2013

  5. Ramesh .R , Nathiya .R Realization of fir filter using Modified distributed arithmetic architecture An International Journal (SIPIJ)

    Vol.3, No.1, February 2012

  6. M. Kumm, K. Moller, and P. Zipf, Dynamically reconfigurable FIR filter architectures with fast reconfiguration, in Proc. 2013 8th Int. Workshop on Reconfigurable and Communication-Centric Systems- on- Chips (ReCoSoC), Jul. 2013.

  7. P. K. Meher and S. Y. Park, High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic, in Proc. 2011 IEEE/IFIP 19th Int. Conf. VLSI, System-on-Chip, (VLSI-SOC11), Oct. 2011, pp. 428433.

  8. S. M. Badave and A .S. Bhalchandra, International Journal of Information and Electronics Engineering Multiplierless FIR Filter Implementation on FPGA Vol. 2, No. 3, May 2012

  9. Md.Zameeruddin, Sangeetha Singh Efficient Method for Look-Up- Table Design in Memory Based Fir Filters International Journal of Computer Applications (0975 8887) Volume 78 No.16, September 2013

  10. M. Yazhiniand R. Ramesh FIR Filter Implementation using Modified Distributed Arithmetic ArchitectureIndian Journal of Science and TechnologyISSN: 0974-6846, May 2013

  11. Shrikant Patel Design and implementation of 31- order FIR low- pass filter using modified distributed arithmetic based on FPGA International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (An ISO 3297: 2007 Certified Organization) Vol. 2, Issue 10, October2013

  12. RakhiTharkur, KavitaKhare High Speed FPGA Implementation of FIR Filter forDSPApplicationsInternational Journal of Modeling and Optimization, Vol. 3, No. 1, February 2013

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