Low – Error Fixed-Width Modified Booth Multipliers for DSP applications

DOI : 10.17577/IJERTV2IS100001

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Low – Error Fixed-Width Modified Booth Multipliers for DSP applications

    1. ech, ECE Dept, PBR VITS, Kavali, AP-INDIA.

      Abstract: In this paper, a single compensation formula of adaptive conditional-probability estimator (ACPE) applied to fixed-width Booth multiplier is proposed. Based on the conditional probability theory, the ACPE can be easily applied to large length Booth multipliers (such as 32-bit or larger) for achieving a higher accuracy performance. To achieve great results between accuracy and area cost, the ACPE provides varying column information to adjust the accuracy with respect to system requirements. Furthermore, the ACPE Booth multipliers are applied to two-dimensional (2-D) discrete cosine transform (DCT) to evaluate the system performance.

      Keywords— Booth Encoder, Partial product generator, Fixed-width multiplier, Modified Booth multiplier, Compression tree, Carry Look ahead Adder.


The main Objective of this paper is to reduce the number of partial products and truncation error by using the modified booth multiplier. Where multipliers are always the fundamental arithmetic unit and significantly influence the systems performance and power dissipation, the modified Booth encoding which reduces the number of partial products by factor of two through performing the multiplier recoding has been widely adopted in parallel multipliers. In DSP Applications

Assoc Prof, ECE Dept, PBR VITS, Kavali, AP-INDIA.

Modified Booth Multipliers plays an Vital role for getting good performance and little truncation error. To perform n-bit multiplication in previous days we have to do n-partial product terms and also we need large number of adder cells. For the sake of this concept the system having large propagation delay and more power consumption. This multiplication process getting different innovations according to the different trends. In those some of them are mentioned below.

The Existing Method named as Direct Truncated Fixed width Multiplier (DTFM)- As the name indicates Truncation operation will done in this method but the resultant product having large truncation error. Here we have to large number of logic gates, buffer gates and adder cells then automatically it requires large power source.

Significant hardware complexity reduction and power saving can be achieved by directly removing the adder cells of standard multiplier for the computation of the N least significant bits of 2N-bit output product. However, a huge truncation error will be introduced to direct-truncated fixed-width multiplier (DTFM).

To effectively reduce the truncation error, various error compensation methods, which add estimated compensation value to the carry inputs of the reserved adder cells, have been proposed. The error compensation value can be produced by the constant scheme or the adaptive scheme.

Fig: Required Components for DTFM

Drawbacks of DTFM is High hardware complexity due to number of slices usage, More partial product array,More power consumption


The proposed high-accuracy fixed width multiplier comprises of (i) Booth Encoder (ii) Partial Product generator and

  1. Compression Tree comprising of Carry Look Ahead Adder. The proposed module outperform the existing module by hardware complexity, power consumption and performance speed. The number of hardware is reduced in each of the existing module by the proposed system. The existing system uses large number of hardware that is full adder and half adder for the final product generation whereas the proposed system uses four fixed width Carry Look Ahead Adder

    This modified booth multiplier is to produce at most n/2+1 partial products, In Fixed Width Modified Booth Multiplier (FWMBM) we have to observe some Special parameters below, The booth encoder circuit takes the input multiplicand X and produces mul, shift and two com signal which is used by the partial product generation circuit to produce the partial product bits of one dimensional array.

    Fig: Booth Encoder Table

    By using this encoding table we have to follow some steps in multiplication process as follows


    1. Pad the LSB with one zero.

    2. Pad the MSB with 2 zeros if n is even and 1 zero if n is odd.

    3. Divide the multiplier into overlapping groups of 3-bits.

    4. Determine partial product scale factor from modified booth 2 encoding table.

    5. Compute the Multiplicand Multiples

    6. Sum Partial Products

Let us consider the multiplication operation of two n-bit signed numbers are X = xn-1, xn-2 .x0 (multiplicand) and

Y = yn-1, yn-2 .y0 (multiplier). The twos complement representations of X and Y can be expressed as follows:

X = – xn-12n-1 + xi2i,

Y = – yn-12n-1 + yi2i.

The functional model design of the booth multiplier consists of first, booth encoder for encoding the multiplicand/multiplier. Second, if the multiplicand and multiplier are of n-bits, partial product generator generates (0.n/2-1) n/2 number of partial product bits which are a one dimensional array. Third, compression tree consists of 9-bit, 12-bit and 16-bit carry Look Ahead generator to produce final output product.

Fig: Partial Product Generator:

The above figure illustrates the final partial product matrix of proposed fixed width modified booth multiplier for n=8. In it, all the partial product bits in LPminor are removed and replaced by the SC generator.In addition, the carries generated by LPminor are also replaced by the outputs of SC generator

The Compression tree Compared to previous technique, the proposed error compensation circuit can achieve a tiny mean error and a significant reduction in mean square error. The smaller mean error and mean square error represent that the error distribution is more symmetric to and centralized in the error equal to zero (denoted as zero error).

Fig: Block diagram of Booth Multiplier The above is Block Diagram of

Booth Multiplier, Where Multiplier is Y and Multiplicand is X. Both X and Y is connected to the Booth Encoder. The purpose of Booth Encoder is used to generate the partial products. The compensation circuit used to reducing the errors. The Carry Save Adder (CSA) used to adding the partial products and saving the carry value. The parallel prefix adder is used to adjusting stage and also adding the partial products. The final product is getting through the pq.

The term SC-Generator is nothing but signal conditioning generator, the purpose of SC-generator is to check whether it is more number of 0s or 1s are present in the network.

Circuit Explanation:

The inputs of SC-Generator are zeroi for 0in/2-1and it will generate m-output bits 1, 2, – – – – m as shown in above fig. Where m= (n/2-1)/2 and s() will be equal

to 1+2+. . . . m . Due to the subtraction operation in [(R-1)/2], it is difficult to generate 1, 2, – – – – m by adder cells directly. Instead of adder cells, the proposed SC-generator is composed of a sorting network based on the following observation. We assume that zeroi for 0in/2-1 can be sorted and the sorted outputs are j for 0jn/2-1. Moreover, if the largest bits are gathered to the less significant positions, then k=2k for 1km. That is the problem of designing a SC generator can be translated into the design of a sorting network that sorts Zeron/2-1 . . . . . zero1zero0 into n/2-1 . . . . 10 and k=2k

. Fig: Error compensationcircuit There are 2 kinds of well known

comparison based sorting networks, the bitonic and the odd-even merge sorting networks suited to hardware implementation. Since the odd-even merge sorter has the same number of compare levels as the bitonic sorter but requires fewer comparators, thus we adopt and simplify the odd-even merge sorting network to realize the SC-generator. These

sorting networks are composed of appropriately connected comparators. Each comparator takes in 2 input bits and either passes them directly or switches them. With inputs a and b, the outputs max (a, b) and min (a, b) of comparator correspond to (avb) and (ab) respectively. After sorting for n=8,1 are equal to the sorted outputs 0, 1,2,3.The logic gates only for producing these outputs can be removed to simplify the SC-generator. Besides the sorting networks can be further simplified by using NAND, NOR, AND-OR INVERTER (AOI), and OR-

AND INVERTER (OAI) gate for n=8 respectively. The SC generator for different n can be constructed in a similar fashion.

Fig. Compression Tree using Carry Look Ahead Adder

The compression tree is the one which adds the individual partial product bits generated by partial product generator using Carry Look ahead Adder and produce the final output product bits.

Fig. 7. (a) The odd-even merge sorting network for N=16. (b) The proposed SC-generator for N=16.

Here Low power consumption Architecture reduces the area of registers used in conventional multiplier are the main factors.


  1. Real-time signal processing

  2. Audio signal processing

  3. Video/image processing

  4. Digital Signal Processing

By using XILINX software for synthesis of DTFM and FWMBM to compare the area and power using VerilogHDL Behavioral structure

The area depends on number of components used in the circuit.

Fig : Required Components for FWMBM

Power requirement also depends on the value of electrical components.

Fig : Power Analysis for FWMBM

In power comparison to execute an instruction in FWMBM it requires only 25mW power but for the same operation

DTFM requires 218nW power it is one of the drawback of DTFM.

DTFM.218 mW FWMBM 25 mW

Direct truncated fixed width multiplier:

By using Model Sim we can perform simulation operation here we can observe the time delay . error compensation, and truncation error,mean & mean square errors

Fixed Width Modified Booth Multiplier:

The above Simulation waves shows the Output Product term By using DTFM and FWMBM

In this paper, a high accuracy fixed width modified booth multiplier has been proposed. In the proposed multiplier , the partial product matrix of booth multiplication was slightly modified and an effective error compensation function was derived accordingly. This compensation function makes the error distribution be more symmetric to and centralized in the error equals to Zero, leading the fixed width modified booth multiplier to very small mean and mean square errors. In this paper reduce number of partial products by using the booth encoding and also we can apply this concept for different n values.

Presently technology used towards the reduced power consumption and area occupation which is very important in certain applications. Hopefully the present multiplier architecture may lead to the advanced technology in minimizing the area and reducing the power consumption.

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