- Open Access
- Total Downloads : 275
- Authors : Aparna. P
- Paper ID : IJERTV2IS70684
- Volume & Issue : Volume 02, Issue 07 (July 2013)
- Published (First Online): 31-07-2013
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License: This work is licensed under a Creative Commons Attribution 4.0 International License
Leakage Reduction In Advanced WDR Image Sensors With Halftone Pixels
ME VLSI Design (PG Scholar) Anna University
Leakage reduction plays an important role in power consumption in many of the systems like image sensors. Adaptive bulk biasing control scheme is used to reduce the leakage during the standby mode of operation in the systems. Advanced WDR image sensors used to take images especially in situations where the light enters a premise from different angles, i.e. where both the dark and bright areas are there in the camera field of view that provides continuous tone images. Every pixel is to be converted in to halftone pixels in any of the conventional press, in order to print the image. Here a halftone pixel is generated using Floyd-Steinberg algorithm. The adaptive bulk biasing control scheme provides 21% power reduction as compared to any other standard systems.
Index Terms- Continuous Tone Image, Halftoning, WDR image sensors, Adaptive Bulk Biasing Control, Leakage Reduction, Halftone Pixels
In late 1990s, performance of CMOS image sensors improved signicant, in terms of the CCD applications such as pinned photodiode, charge transfer gate and micro lens. The XY address scanning architecture, which was employed for active pixel sensor and pixel scanning, was investigated during the 1960s prior to the invention of the CCD image sensor. The main advantage of the active pixel sensors is the suppression of the noise injected in the signal readout path or generated. A pixel without signal amplification is termed as the passive pixel. An image sensor can be of analog output, digital output or SOC type. Wide dynamic range image sensors are finding growing applications in surveillance, tactical, automotive, medical and diagnostic instrumentation (fluorescence, detection and spectroscopy) and industrial arenas. In addition to ability to capture scenes in undesirable scene disturbances such as sun reflection or laser jamming, it is able to capture the scenes with large variations in irradiance due to temperature.
CMOS image sensors have benefits such as on chip functionality and power reduction as compared to other image sensors. i.e. they have less power consumption and are intelligent, user friendly image sensors.
Dynamic range is the ratio between the largest and the smallest possible values of a changeable quantity such as signals and lights. The human senses of hearing and sight have high dynamic range, capable of hearing from a quite murmur to the sound of a heavy metal concert. It may exceed a level of 100dB .Whereas the dynamic range of sight is 90dB. A number of techniques were proposed for the leakage reduction in CMOS image sensors. They include stacking cutoff transistors , utilization of high threshold voltage (HVT) devices, aggressive supply voltage reduction , adaptive voltage scaling  and application of negative voltages to the wells or substrate. AB2C was intended for the integration with image sensors operating in the rolling shutter model. It provides a body bias to the system under consideration. The forward body bias enhance the performance by means of the active current, whereas the reverse body bias reduces the leakage. The technique, originally proposed by Fish et al , the reverse body bias is applied dynamically using a network of resistors to the row of pixels, when the rows are not accessed. Since it have a bulk capacitance, dynamic discharging and charging has side effects such as bulk charging delay, noise or interference and additional power consumption. These problems can be reduced by means of gradual voltage application in the AB2C scheme.
We use a modified Adaptive bulk biasing control scheme that is integrated with a WDR image sensors with halftone pixels. They have improved flexibility, robustness, performance and functionality as compared to the original one. Floyd- Steinberg algorithm is the halftoning algorithm used and based on the error dispersion. It converts the normal pixels in to halftone pixels Thus with the aid of the adaptive bulk biasing control scheme WDR image sensors provide a halftone pixel with less power as compared to any other standard systems. WDR image sensors considered only the normal pixels those
provide pictures with a large number of colors. The proposed system provides halftone pixels that simulates tone imagery by means of dots, varies in spacing and shapes i.e. halftone process reduce reproduction of visuals to an image. This reproduction relies on optical illusion, i.e. the tiny dotes in halftone are blended to tone that are smooth by human eyes. It may become easy to print the image and takes a less ink for the same with a high resolution
Effects of Body Biasing
Connecting to a bias rather than to power or ground in the layout circuit is termed as the body bias. It is supplied from an on chip or from an off chip source. The forward body bias reduces the threshold voltage by applying a positive body source voltage to n channel transistor and thereby provides faster and leakier transistor. Reverse body bias on the other hand raises threshold voltage and provides both slower and less leaky transistors. The total power consumed in an image sensor can be denoted as
P = Pdynamic + Pstatic (1)
where is the power consumed during transient switching activities and is the constant power consumed due to biasing and/or leakage currents. The threshold voltage of a transistor can be represented as
= 0 + [ 2 – 2 (2)
Where VT0 is the zero biasing voltage, that is set during fabrication; is the body-effect coefficient; is the Fermi potential and VBS is the body-to-source voltage. Body effect; is the change in the threshold by creating a potential between the source and body terminals of the transistor .The speed enhancement is done by means of the body biasing in many of the digital circuits only up to 60 nm . The effectiveness of the technique degrades, as technology scales due to several factors, such as the higher influence of drain induced barrier lowering (DIBL) and other parameters on sub threshold leakage  and the increase of band-to band Tunneling current (BTBT)
as a result of applying RBB. Body biasing techniques are quiet interested for both improving variation sensitivity as well as performance enhancement in advanced processes.
Lowering the threshold voltage that increases
a devices ON current leads to the performance enhancement. A forward body bias is applied, and has the positive side-effect of reducing the standard deviation of the threshold voltage distribution. Fig. 1 shows the effect of forward body biasing on the saturation current (with VGS = VDS = VDD ) of a minimum sized nMOS transistor at various (low
power) process nodes. The figure shows the drain current increases, as compared to a zero-biased equivalent transistor.
Gradual Bulk Biasing
Consider the circuit shown Fig. 3(a) with 2N capacitors (each representing the bulk. capacitance of a single row) connected in parallel with approximately equal resistances between them. Apply a
potential,Vbias , to one of the middle capacitors, a constant voltage drop will be symmetrically applied to the remaining capacitors, as they progress towards the opposite voltage supply and can be further extended by connecting the two end nodes and grounding them. A
ring of RC circuits symmetrically biased around the virtual line connecting the biased node with the grounded one . The biasing poit can easily be moved to a different bulk without upsetting the symmetry, by changing the connection node of both the bias voltage and the ground supply. This is analogous to changing the bias point of the active row.
This scheme results in a gradual voltage drop between the two biasing points. This transition to an adjacent row causes a slight voltage change of V at each node. This small change has a very small disturbance effect as compared to the full step charge, especially since the change is gradual at then on- directly biased nodes. Therefore, a forward biased node can be set at one end of the circuit and a reverse bias can be set at the opposite end, without the need for
large drivers or the danger of applying a large abrupt voltage step.
dynamic control and the system performance enhancement this technique can be used for adapting circuits for performance under process variations. For the body biasing separate well are required for each transistor for different body potential. So it requires the implementation of techniques such as DTCMOS  though the size requirement for each transistors are very large.ie A specific circuit with limited number of devices or an entire block of devices with a common well potentials can only make use of the body biasing. Only the later can be considered in the case of a pixel or bitcell arrays with thousands or millions of devices.
A row wise addressing is commonly used for cell access .Accordingly FBB provides an efficient method for performance enhancement. The n-well and p -well in each cell in a certain row should be common
.These well are modelled as a lumped RC network. In the improved version the resistor network is connected in a ring structure, provides performance improvement especially at the end of the arrays. nMOS transistors are used instead of the resistors in the circuit and they make use of SRAM bitcells.
Ends of the arrays, where the original circuit lost correct biasing structure. Second, the resistors are replaced with constant biased nMOS transistors . This creates adaptable, high.
6T SRAM bit cell with minimum sized pMOS and access transistors (M1, M3, M5, and M6) and slightly larger pull-down nMOS (M2 and M4) is used as the standard memory cell.1-bt in pixel resistance, small area resistors, and enables further flexibility, as will be shown herein. Third, theAB2C improved concept is suitable for utilization in SRAM arrays. In this paper we show an example of its application to a serially accessed SRAM array that is operated in , as part of a wide dynamic range advanced image sensor.
Body Biasing With A Scheme
The simplest body bias is to apply a fixed bias identically to all the chips with a value set during design. A more advanced body bias methodology is to apply adaptive body bias where a different bias value is calibrated. Adaptive body biasing corrects the systematic manufacturing variations thus reducing threshold voltage variations and sort yield improvement
AB2C scheme is efficiently integrated with large components that consist of many leaking devices and can only be applied to components ,that operates in the serial access scheme. Thus a MOS image senor is a perfect candidate for the scheme. In addition to the
Within the 3 nmos transistor one is connected as pass gate transistor to forward body bias and the other one to the reverse body bias. Shift registers are connected to the gate of the transistors, which control the digital input. The third one, resistive device is connected in between the bulk voltages of the sub circuits.
Floyd-Steinberg algorithm is an image halftoning algorithm, used for the halftone image production in our case. It is a image halftoning algorithm based on the error dispersion. Even though the algorithm is the slowest, provides the best result s compared to any other classical methods. It is commonly used in situations such as,to convert an image in to GIF format ,that is restricted only with 256 colors. halftone image production in our case. It is a image halftoning algorithm based on the error
dispersion. Even though the algorithm is the slowest, provides the best result s compared to any other classical methods. It is commonly used in situations such as, to convert an image in to GIF format ,that is restricted only with 256 colors.
The algorithm scans the image either from top to bottom or from left to right .At each point the color of the image is considered it with the actual color in the system hardware. This difference is termed as the quantization error. The error is diffused over the neighboring pixels where they are added up with the current value. Thus the halftone pixel value is obtained.
Quantizatio n Error
The pixel uses standard 6T SRAM which
consist of access transistors and the minimum sized PMOS transistors. The photodiode voltage is reset only when the in-pixel memory has been set. to 1. Adaptive bulk biasing scheme is given as the input through
. Transistors M2, M4, M5, N1, N2, N3, and N4 of the
pixel, all receive the RBB voltage, during integration period. Selected rows are forward biased that reduces the threshold voltage of transistors N1-N4 increasing the swing of the signals and shutter efficiency.
Halftone value is compared with the input value with threshold by means of feedback loop. Quantization error is calculated by subtracting the halftone value from the input value. Error filter transfer this quantization errors to the neighboring pixels without affecting the pixels that re scanned. Hence, if a number of pixels have been rounded downwards, the next pixel is rounded upwards.
In this paper a WDR image sensor with halftone pixels is taken as the test case. This image sensor uses both on-chip SRAM and an in-pixel memory bit array to store the number of resets applied to each pixel during a single frame.
4.1 Halftone Images
Halftone images mainly consist of dots that vary in size, shapes and spacing. Larger dots are for denser and darker areas while smaller are for lighter areas. The continuous tone images consist of infinite number of colors, whereas halftone process reduces visual reproduction. Optical illusion is the basis of this reproduction i.e. the tiny halftone dots are blended in to smooth tone by human eyes. Thus it is a more efficient way to print the images.
Observations and Measurements
The normal pixel generation and a halftone pixel generation in a WDR image sensor is compared
.Here we have taken the display of 300 ASCII characters to consider the normal pixel generation. The simulation results of the pixel generation is shown below.
The halftone pixels are generated by means of the Floyd-Steinberg algorithm. The generation of halftone pixels is represented by means of simulation results using Modelsim shown in fig.7
AB2C is used to reduce the leakage within the systems such as image sensors. The scheme can be represented in terms of simulation results of the schematic circuit. It is shown below in fig.8
The power consumed in the above three cases can be calculated by means of Xilinx ISE13.2 Design tool and compared in the below table.
Utilization (in %)
The power consumed for both the normal pixels and for the halftone pixels are very small compared to standard
systems, with the help of adaptive bulk biasing control cheme.
Adaptive bulk biasing scheme is used to reduce the leakage within image sensors. As a test case a wide dynamic range image sensor with halftone pixels is used. These halftone pixel images have wide applications in remote sensing, iphone, ipad and ipod touch. The scheme reduces the power consumption of the WDR image sensors with halftone pixels up to 21%. A halftone image is made up of a series of dots rather than a continuous tone. These dots can be of different sizes, different colors, and sometimes even different shapes. Larger dots are used to represent darker, denser areas of the image, while smaller dots are used for lighter areas.
Halftone images are using in newspapers and magazines because it is a much more efficient way to print images. Since a halftone image is made up of discrete dots, it requires significantly less ink to print than a continuous tone image. As long as the resolution of the image (measured in LPI) is high enough, the dots appear as a continuous image to the human eye. However, if you closely examine the images printed in a newspaper, you should be able to see the dots that make up the halftone image.
Even more advanced pixels such as chrome book pixels, other than halftone pixels may be used in WDR image sensors in the future work. The implementation of the scheme integrated with WDR image sensors in Xilinx ISE 13.2 software
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Aparna.P ,was born in Kerala ,India on April 21,1990. She received B.TECH degree in Electronics and Communication from Vedavyasa Institute of Technology, Calicut University, India in 2009 and 2011and completed ME degree in VLSI design from Srinivasan Engineering college, Anna University in 2011 and 2013.
Her current research interest include Very Large Scale Integration and Image Processing