Inverter Based Transimpedance Amplifier with Capacitive Feedback Topology

Download Full-Text PDF Cite this Publication

Text Only Version

Inverter Based Transimpedance Amplifier with Capacitive Feedback Topology

Nirali Hemant Patel

Student, Masters of Electrical and Computer Engineering Concordia University, Montreal, Quebec,

Canada.

Abstract Trans-impedance amplifier (TIA) is widely used in optical sensing applications (precision instrumentation) and optical communication such as fiber optics, IR communication, and VLC. TIA converts current (I) into voltage (V). Application of TIA design depends on objectives requirement systems, for high speed as well as high-band, low noise, low power, etc. Many different topologies have appeared in different optoelectronics fields, which makes the choice of the best TIA topology for a certain application a challenging task. The proposed TIA is based on shunt-shunt feedback topology as Inverter-based TIA with Capacitive feedback. This methodology is anchored by a design in a 50nm CMOS technology. The photodiode has a capacitance of 100fF, which permits the TIA to achieve a wide bandwidth of 7GHz with a data rate of 10Gbps. It is seen that the proposed TIA provides a Transimpedance gain of 32.7dB-Hz and input cross- referred noise-current spectral density of 13.0pA/Hz1/2 and total RMS noise with 135.23µA.

Index TermsCurrent Spectral Density, Photodiode, TIA, VLC.

  1. INTRODUCTION

    In the past few years, the continuous trend toward efficient means information dissemination has revived Optical communications, paving way for detailed study in the field of fast and reliable components and the integrated circuit. Communication technology such as cell phones, portable computers with high-speed data processing and high-speed access to store data becomes an interesting issue [1].

    CMOS technologies have drastically developed in recent years. Todays world need long battery life for the devices whether it is used in communication application or medical devices or any other field. Thus low power dissipation is the basic need of todays VLSI Circuits. The first structure block in the optical communication receiver is the Transimpedance amplifier, (TIA). The main task of TIA is to changes the small signal current to the output voltage signal. In order to have a better TIA, the two main parameters that must be reckoned with are the bandwidth and the input sensitivity deviation [2, 3]. TIA being the basic circuit for many applications to convert current signal to voltage signal, improvement in its power dissipation is also necessary. Trans-impedance Amplifier (TIA) or another name called as photodiode amplifier, has a function for converting the photodiode photocurrent output (Isc) to a voltage signal (VO). TIA has implemented in various optic application, not only for optical sensing (measurement purpose) but also for optical communication (i.e. IR, VLC, fiber-optic). They are can be built by discrete circuit mechanism, such as: [4], [5], or by MOS transistor circuitry. Its circuit design divided into several aspects, such as precision instrumentation TIA, high speed TIA, low noise TIA [6], gain

    stability TIA [7], manual programmable TIA [8] and other related objectives.

    Fig.1 Block Diagram of Optical Communication Receiver [9]

    To achieve the above specifications, namely, low input resistance, low output resistance and low noise and high Transimpedance gain, various topologies have proposed. Shunt resistance [12], common gate (CG) circuits [13]; regulated cascode circuits (RGC) [14], common source circuit with shunt feedback [15, 16] and cross-coupled current conveyor [17] are some of them. Each topology provides a part of the specifications required; moreover, it even allows the designer to make some tradeoffs. A designer uses a topology according to the specifications and need, which are required, and reaches those specifications by completing those tradeoffs. In other words, tradeoffs give some degrees of freedom to the designer to meet the specifications required. [18].

    Primary parameters for consideration in selecting a Transimpedance amplifier are bandwidth, noise, signal bandwidth, and gain. Avoid a sensor with high capacitance value and even try to avoid creating a capacitance between your sensor and TIA. Avoid a TIA with high voltage noise (nV/Hz) or high current noise (pA/Hz). Consider the impedance of your sensor at the very best operating frequency of that sensor specified the product of voltage noise (of the TIA op amp), current noise (of the TIA op amp). Therefore, the aforementioned impedance of your sensor at the highest frequency are as low as you will be able to get them.

    The steadily growing bandwidth requirement of data centers, high-performance computers in terms of power consumption, low noise and speed is the major aspects, the mainframe switches the demand for high-speed serial interconnects in optical lines. Electrical interconnect is unable to address this space in a power- and cost-efficient way due to the high- frequency dependent losses of copper wiring [22].

    The commercial optical modules used in high volumes in data centers are pluggable optical modules located at the board edge, distant from the host chip. Integrating optoelectronics on to the first-level package requires a low-cost packaging solution with an optical escape path. High-speed automated packaging tools are preferred, as they are lower cost per part than packaging tools using active optical alignment, where the optical engine is been actively used to optimize the optical coupling [21]. However, high-speed automated packaging tools have worse alignment tolerances, resulting in higher optical coupling losses that stress the optical link budget [21].

    In section 2, the proposed topology is been introduced. A circuit based on the proposed topology is been shown in section

    3. In section 4, the simulation results of the circuit together with a comparison of our result with other previously reported circuits are been presented. Finally, the conclusion is there in section 5.And at last, Appendix A kept for more information and details.

  2. INTRODUCTION TO PROPOSED TOPOLOGY

    A voltage amplifier composes Shunt-Shunt Feedback topology with capacitive feedback, with a transfer function given by A(s) and a feedback resistor RF connected between its input and the output. This configuration is been known by "voltage-current" feedback, where a negative feedback network (the feedback resistor) senses the voltage at the output and returns a proportional current to the input.

    This type of feedback is chosen for a TIA circuit because it lowers both the input and output resistances, thus increasing the input pole magnitude and allowing the amplifier to absorb the photodetector current, and also yielding a better drive capability. Rest of the equations and information is mention in Appendix A.

    Fig. 2 Shunt-shunt feedback TIA [10]

    The A(s) is replaced with inverter based TIA with capacitive feedback as shown in the Fig. 3 below.

    Fig. 3. Inverter based TIA with capacitive feedback [11]

    Specifically, a bigger PD usually features a higher responsivity, but it also introduces larger parasitic capacitance at the TIA input, which limits the TIA trans-impedance gain for the specified BW and thus deteriorates the noise performance of the TIA and therefore the whole receiver. Therefore, it is significantly important to scale back the TIA input capacitance for better sensitivity. By employing a little capacitor because the capacitive feedback in the TIA core amplifier, an outsized negative equivalent capacitance is been generated at the TIA input to scale back its input capacitance.

    As a result, a higher tans-impedance gain and lower input- referred noise (IRN) current are often achieved within the proposed TIA in comparison to a reference TIA with [11] and without [20,21] capacitive feedback for the BW and Normalized INR. The employment of CF also introduces a zero in the TIA trans-impedance gain, which is Gm/ (2CF), and Gm is the equivalent transconductance of the non-inverted amplifier between node X and node Y. Since the zero is located far beyond the TIA BW (due to the CF), it has a minimum effect on the TIA frequency response. See Appendix A for more information on capacitive feedback principle and calculations.

  3. CIRCUIT BASED OF PROPOSED TOPOLOGY

    The proposed TIA is been designed with a 50 nm CMOS process, and the design parameters are presented in Fig. 4 and Table 1.

    Fig. 4 Schematic of Inverter based TIA with Capacitive feedback.

    TABLE I: DESIGN PARAMETERS

    Parameters

    Values

    Vdd

    1.2V

    W(nmos) (M2,M3)

    2µm

    W(pmos) (M5,M6)

    4µm

    W(pmos_cs) (M4)

    4µm

    W(nmos_cs) (M1)

    8µm

    The reason of choosing the W (nmos) and W (pmos) as the values mentioned above is the Bandwidth-gain AC analysis. If another width were chosen it will give the Output of AC analysis shown in the figure 5 where, W (nmos) = 4µm and W (pmos) = 8µm.

    Fig. 5 AC analysis for greater width than proposed topology

    Moreover, even if the width are chosen below the parameters shown in Table I, the output of AC analysis is like the figure shown below as Figure 6. As it is not matching the requirement of Bandwidth of 7GHz.

    Fig. 6 AC analysis for lesser width than proposed topology

    Therefore, the problem with this two approach is the zeta (damping factor) which is affecting the circuit as it produce that notch thing on the upper side.

    Moreover, PRBS source is been added. PRBS is add as a source for random binary bits. Binary pulses are generate from pseudo random binary sequence generator as an output it is in a sequence of 1's (High) and 0's (Low) of a known and reproducible pattern. The frequency of an external clock determines the number of bits per second (bit rate) which is use to drive the generator.

    From the generator a single bit is transmitted for each clock period, either it is "1" or "0" level, and the width is equal to the clock period and due to this, the external clock is referred to as a bit clock. Random (pseudo) manner is been generated for the

    As PRBS source gives the output in terms of voltage so, it is needed to convert that into current, So, B1 is used as a source as shown in the Figure 8. Rest of all the parameters should remain constant.

    Fig. 8 Circuit with PRBS source.

    So, in total the schematic with PRBS source as an alternative of the source is represent in Figure 9.

    Fig. 9 Inverter based TIA with Capacitive feedback topology with PRBS source.

    distribution of 1's and 0's for a long sequence.

    At 75

    temperature the circuit is also been implemented with

    Eye diagram is check-using PRBS, as it required a random number of bits for verifying the output. Figure 7. shows the schematic level diagram of 5 level PRBS source using D- flipflop and gates where the sine wave is given according to the clock frequency = (1/10GHz).

    the command of .temp 75. The results is been shown and described in Section 4.

  4. SIMULATION RESULTS

  1. Bandwidth:

    The equation to calculate the Bandwidth is BW= Fh-l. Fh is the upper cut off frequency. Fl is the lower cut off frequency. To find the cut off frequency first find the 3 dB points.

    Considering the finite BW of its core amplifier, the proposed TIA can be model as a second-order system, and its BW is express as below:

    3

    2

    2()

    (2)

    Fig. 7 PRBS source.

    Where, Av is the voltage gain of the TIA core amplifier.

    As shown in the Figure 11. The bandwidth gain (dB-Hz) at 0 C with -3dB graph fulfilling the condition of achieving 7GHz as a data rate.

    Fig. 11 Bandwidth-Gain Graph at 0 C

    Since there is no built-in gain (Vout/Vin) plotting function available in the software, we can just plot the output voltage by setting the input voltage amplitude equal to 1 for the AC analysis. To get the transfer function, you can just subtract the

  2. Noise Analysis:

    The noise performance is a very significant issue of high-level characteristics of an RF transceiver. The small current of the photodiode is directly affects the signal to noise ratio (SNR) and the overall bit error rate (BER). The equivalent input noise level should be very small to ascertain that the receiver works at a reasonable sensitivity rate with a low bit-error- rate [19].

    As the flicker noise does not have effect in MOS transistor, it can be neglected and the terminal noise becomes the main source of the noise.

    At discrete frequencies, using a linearized version of the circuit small signal analysis can be carried out, as it is a noise analysis. The mechanics of small signal analysis are very similar to those of an AC analysis.

    Assuming the TIA noise is been dominated by MP4 and MN1 and R3, then its IRN current power spectral density can be expressed as below (3):

    output voltage dB value by 0dBV, which indicates the dB value

    4

    1+( )2

    of the output voltage equals to the gain.

    For temperature at 75 C, the graph is improper or we can say it is unstable shown in the Figure 12. As the data rate decreases

    2() =

    + 4

    2

    , If CF << CT (3)

    to 5.04GHz frequency which is not according to the requirement.

    Fig. 12 Bandwidth-Gain Graph at 75 C

    Even if I increased my input 10 x to the sensitivity limit, my system should works the same and it is as expected as shown in the figure 13.

    The input referred noise (IRN) is shown in the Figure 14 below at 0 C with 13.00pA/Hz1/2 and the total RMS noise is 135.23µA.

    Fig. 14 INR at 0 C

    The output noise V(onoise) is shown in the Figure 15 below at

    0 with 3.462nV/Hz1/2 and the total RMS noise is 424.46µV.

    Voltage noise spectral density is a measurement of RMS noise voltage per square root hertz (or commonly nV/Hz1/2)

    Fig. 13 Bandwidth-Gain Graph with 10x input

    As Figure. 11 is simulated at 5µA and Figure. 13 is simulated at 50µA current input. See Appendix A for more information and details.

    At 75

    Fig. 15 Output noise in terms of voltage at 0 C

    , definitely, the system reacts due to increment in

    temperature over here the input referred noise (IRN) increases

    compared to 0 C due to the capacitance, as due to the temperature increment the internal structure of capacitor get affected.

    In addition, for resistor, as temperature goes up the resistance goes up as it shows linear characteristics. So, their presence affects the system, output is shown in the Figure 16, below with 14.86pA/Hz1/2 whereas, the total RMS noise is 122.31µA.

    Fig. 16 IRN at 75 C

    Even if I increased my input 10x to the sensitivity limit, my system works same as shown in the figure 17 with same INR value. The normal system works as 5µA, which is increased, to 50µA to check the reliability of the system.

    The vertical eye opening on the Figure 18 is 420mV. The simulated data rate is 10 GB/s (BW/0.7) with a voltage swing of 760mVp-p as indicated in Figure 16.

    For temperature at 75 C, the system is getting worse, the vertical eye opening became smaller compared to the normal system with 390mV with an voltage swing of 730mVp-p as shown in the Figure 19 below.

    Fig. 19 Eye diagram of the schematic at 75 C

    Again, it is been simulated at the dat rate of 10 Gbps (BW/0.7).

    Even if increasing the input 10x to the sensitivity limit, the system should works the same and it is as shown in the figure 20 with same eye diagram value. The normal system works as 5µA, which is increased, to 50µA to check the reliability and stability of the system.

    Fig. 17 IRN at 0 with 10x input

    For more information and detail, see Appendix A.

  3. Eye diagram

To be quick in visualization and determined the eye diagram that allows the key parameters of the electrical quality of the signal, as the eye diagram is a methodology to represent and analyze a high-speed digital signal data.

Just as a human eye appearance, the eye diagram takes its name. From superimposing the passive waveform to form the image, it is been created with very simplicity. For the purpose of recognizing the effects of distortion and finding its source, eye diagram is been used to look at digital signal in a primary manner.

The eye diagram is been shown below in Figure 18. At 0 C,

Fig. 20 Eye diagram of the schematic at 0 with 10x input

For more information and details, see Appendix A.

The PRBS source is added as a source instead of normal source for having random number of binary bits to check the reliability of the circuit. Usually 3, 5, 11 level PRBS source are available which will generate random number of bits using flip-flops and gates.

5-level PRBS source is been used as shown in the circuit, Figure 7 and Figure 8. The output of using PRBS is shown below in Figure 21.

Fig. 18 Eye diagram of the circuit at 0

Fig. 21 Eye diagram of the circuit at 0

with PRBS source

IRN(Arms)b

0.4µ

0.83µ

0.43µ

135.23µ

Normalized IRN

4.6m

4.4m

3.7m

1.93m

INR current power spectral density (pA/Hz1/2)

N/A

N/A

0.75

13

VEO(V)

61m

5m

70m

420m

IRN(Arms)b

0.4µ

0.83µ

0.43µ

135.23µ

Normalized IRN

4.6m

4.4m

3.7m

1.93m

INR current power spectral density (pA/Hz1/2)

N/A

N/A

0.75

13

VEO(V)

61m

5m

70m

420m

The VEO (Vertical Eye Opening) of the system output shown

above is 430mV with the voltage swing of 780mV desired data rate of 10Gbps.

p-p

at the

For 75 C temperature, the system output is been shown in Figure 22 below, the VEO is being smaller compared to the normal PRBS source system with 340mV having the voltage swing of 700mVp-p.

aNormalized IRN = INR (A

bSimulated result.

rms)/( × (()) ), based on (1) in [21].

Fig. 22 Eye diagram of the circuit at 75 with PRBS source

Even if increasing the input 10x to the sensitivity limit, the system should works identical and it is as shown in the Figure 23 with same eye diagram value. The conventional system works as 5µA, which is increased, to 50µA to examine the reliability and stability of the system.

The proposed TIA has the lowest input referred noise current when compared to other state of design. The outstanding performance was been achieved by applying the design flow methodology, optimizing the design and the noise modeling proposed in this work.

3

3

Circuit Optimization works in a great manner for having low Normalized INR. As the width of the nmos and pmos gets half compared to [11]. The value of feedback resistance is also decreased which plays an important role in that, whereas the value of feedback capacitance increases to achieve the proper result. The principle of capacitive feedback is been discussed in Appendix A.

In order to verify the effective nature of proposed capacitive feedback, a reference TIA is been taken to compare [11]. The difference is that the reference TIA is having different value of feedback capacitance CF, and even a reference TIA is been taken where no capacitive feedback is there [20] to compare the performance.

Fig. 23 Eye diagram of the circuit with PRBS source having 10x input.

An eye pattern provides the following information about a particular system. To estimate the bit error rate and the signal- to-noise ratio is the actual usage of eye-pattern. The Width of VEO defines the interval with respect to time over which the received signal can be sample without any error from ISI.

Table two, summaries the performance of different TIAs. Compared to the reference TIA, the proposed TIA is having low IRN, and achieving good VEO as shown:

[20] [21] [11]

Proposed Design

Technology(nm)

65

14

40

50

Vdd(V)

1.2

1.2

1.2

1.2

Data Rate (Gbps)

10/12

32

4.3

10

Input Capacitance Cpd(fF)

100

69

500

100

Feedback Capacitance(fF)

N/A

N/A

12.3

25

Feedback Resistance (R3) ()

20k

700

29.9k

380

-3dB bandwidth (GHz)

3.5

8

3

7

[20] [21] [11]

Proposed Design

Technology(nm)

65

14

40

50

Vdd(V)

1.2

1.2

1.2

1.2

Data Rate (Gbps)

10/12

32

4.3

10

Input Capacitance Cpd(fF)

100

69

500

100

Feedback Capacitance(fF)

N/A

N/A

12.3

25

Feedback Resistance (R3) ()

20k

700

29.9k

380

-3dB bandwidth (GHz)

3.5

8

3

7

TABLE II: COMPARISON OF PARAMETERS WITH DIFFERENT DESIGNS

CONCLUSION

A complete design flow and implementation of low-noise CMOS Transimpedance inverter based capacitive feedback system were proposed in this work. TIA have wide range of applications such as communication, medical devices and so on. All application demand the long life for proper functioning and portability of devices. The proposed circuit is based on shunt-shunt feedback topology. The experimental results show that the proposed schematic has the lowest normalized input referred noise (INR) compared to other state of art design. The proposed circuit has 50nm CMOS technology and the obtained transimpedance bandwidth ensure a 10Gbps data rate with 7GHz Bandwidth. It uses 380 feedback resistor and generally improves the noise performance with 13.00pA/Hz1/2 and Arms of 135µA. By employing capacitive feedback of 25fF in the proposed TIA, a higher trans-impedance gain and better noise performance are been achieved.

APPENDIX A

To calculate different parameters different analysis at differet stages are been done. Transient analysis is performed for Eyediagram whereas, AC analysis is been done to perform Bandwidth-Gain graph. Moreover, operating points are the first thing, which is been carried out for checking the regions of nmos and pmos. Noise analysis is perform to check input refereed noise current and output refereed noise voltage. Certain aspect like changing the temperature and increasing the input to 10x with sensitivity limit is been done using command like, for temperature .temp 75 is used.

The first and the foremost thing after selecting the circuit is to create the transfer for it and to select the parameters like resistor

and capacitor. The value of resistors (R1 and R2), which are used as feedback between the MOS transistors, are carried out by taking, performing and verifying different values of it. Over here, R1 and R2 are been taken as 50k and 50k both as if any another value is taken it is affecting the AC analysis i.e., Bandwidth graph by giving the damping factor () more than 0.707, and having a zeta more than that will affect the output of the graph by giving the notch shown in Figure 5.

The value of load capacitor is even been chosen like that only by varying it with different values and verifying it while doing AC analysis to get the Bandwidth-gain graph (dB-Hz).

A. Transfer Function of the circuit:

The Transfer Function of a circuit is been defined as the ratio of the output signal to the input signal in the frequency domain, and it applies only to linear time-invariant systems.

H(s) = =

It is clearly shown in (2) and (3) that the employment of CF reduces the TIA input capacitance from (CT to (CTCF*ACF)), and therefore a higher RF can be applied to achieve a higher trans-impedance gain and a lower IRN while maintaining the same BW and the same AV.

  1. Bandwidth:

    Even at 10x input when, that 75-C aspect is been checked it shows the following result:

    = 3

    1+

    1+

    Fig. A.2 Bandwidth-Gain graph at 75C when 10x input is provided

    +1 1+( )(1+)

    +1

    The output of the bandwidth-gain graph comes at 5.01GHz

    3

    1+

    rather than 7GHz, which is the aimed Bandwidth.

    = +1 1+(++ )2((+))

    = 3

    +1

    +1

    +

    1+

    +1

    2 (+)

    (A.1)

  2. Noise Analysis:

1+(

+1 +) (

+1 )

For Noise analysis, there are certain equations, which we have

to follow:

Where, = Time constant, K = voltage gain

2 2 + 2 + 2 + 2 (A.4)

B. Principle of Capacitive Feedback:

,,

,1

2

,2

,

,,2

2 = ,,

(A.5)

,,

2

,

,

,

Where, 2 is the voltage gain.

,,

,,

2 Is the input referred noise voltage and

,,

,,

2 Is the output noise signal

For, input referred noise current,

1

2 2 (

2

) (

, )2

,,

,,

Where, 2 ( 1

2

) = 2

,,

,,

2 (

)2

43[0] + 1

}

,,

{

(,,

)^2

Fig. A.1 Capacitive Feedback Principle Explanation figure between point x and y[.11]

After simplifying according the circuit diagram,

With reference to figure 3. The calculation of CF using this principle between the point X and Y.

If ACF >> 1, then

is been done

2() =

4

+ 4

1+()2 (A.6)

2

CX = CF(1-ACF) -CFACF < 0 (A.2)

CX = CF(1-1/ACF) CF. (A.3)

Output Voltage noise at 0C is been added in the paper, whereas at 75C it is shown below with 3.53nV/Hz1/2 and the total RMS noise is 448.38µV.

The VEO of the figure above is 340mV with 720mVp-p.While adding PRBS source as an input.

In the circuit, I1 is been replaced with IB, where IB should be a current source; therefore, the V (OUTPUT) is converted as,

IB = {(input-current of the system)*V (OUTPUT)} (A.7)

e.g., IB = {5u*(V (OUTPUT))}

Fig. A.3 Noise analysis in terms of Voltage graph at 75

While, increasing the output at 75 to 10x times than the

Even if I increased my input 10x to the sensitivity limit, my system works same as shown in the figure below. The normal system works as 5µA, which is increased, to 50µA to check the reliability of the system with the value of 424.46µV as a total RMS noise value and 3.462nV/Hz1/2 as the output noise voltage.

sensitivity limit the system reaction is been indicated in the figure below:

Fig. A.7 Eyediagram at 75C when 10x input is provided with PRBS source.

The VEO of the above figure is 390mV with 720mVp-p.

Fig. A.4 Noise analysis graph in terms of voltage at 75

provided

E. Eye-Diagram

when 10x input is

REFERENCES

  1. Alioto, M., Ultra-low power VLSI circuit design demystified and explained: A tutorial. IEEE Transactions on Circuits and Systems I: Regular Papers, 2012. 59(1): p. 3-29.

  2. Sackinger, E., The Transimpedance Limit. Circuits and Systems I: Regular Papers, IEEE Transactions on, 2010. 57(8): p. 1848-1856.

    Eye diagram at input with 0C is been shown in the figure below which is having the Vertical Eye opening of 200mV.

    Fig. A.8 Eyediagram at input side with 0C

    Eye diagram at 10x input than sensitivity at 75C is shown below in the figure:

    Fig. A.6 Eyediagram at 75C when 10x input is provided

  3. Awny, A., et al., A Linear Differential Transimpedance Amplifier for 100-Gb/s Integrated Coherent Optical fiber Receivers. IEEE Transactions on Microwave Theory and Techniques, 2017.

  4. D. Wen, W. Cai, Y. Pan, Design of Underwater Optical Communication System, OCEANS Shanghai, April 2016.

  5. P. T. Patil, G.K. Mukherjee, A.K. Sharma, R.R. Mudholkar, High-Gain Transimpedance Amplifier (TIA) for Night Airglow Photometer, Int. J. of Electronic Engineering Research RIP, Vol. 1(2), pp. 109116, 2009.

  6. T-Y. Lin, R.J. Green, P.B. Oconnor, A low noise single-transistor transimpedance preamplifier for Fourier-transform mass spectrometry using a T feedback network, Review of Scientific Instruments, Vol. 83, 2012. DOI: 10.1063/1.4751851.

  7. B. Moeneclaey, et al., A 40-Gb/s Transimpedance Amplifier for Optical Links, IEEE Photonics Technology Letters, Vol. 27(13), pp.1375-1378, July 2015.

  8. L. Orozco, Programmable-Gain Transimpedance Amplifiers Maximize Dynamic Range in Spectroscopy Systems, Analog Dialoue, Vol. 47, May 2013. [Online] Available at: http://www.analog.com/library/analogdialogue/archives/47- 05/pgtia.html.

  9. Proesel, J., Schow, C., Rylyakov, A. , "25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, pp.418-420, 19-23 Feb. 2012

  10. A. F. Ponchet, E. M. Bastida, C. A. Finardi, R. R. Panepucci, S. Tenenbaum and S. Finco DCSH Design House, A Design Methodology for Low-Noise CMOS Transimpedance Amplifiers Based on Shunt- Shunt Feedback Topology, IEEE, 2016.

  11. Xianbo Li and C. Patrick Yue, 3 GHz, 1 mW inverter-based TIA with capacitive feedback for enhanced gain and sensitivity in VLC applications, ELECTRONICS LETTERS 18th April 2019 Vol. 55 No. 8 pp. 469471.

  12. M. Rakideh, Seifouri, P. Amiri, A folded cascode-based broadband transimpedance amplifier for optical communication, Microelectron. J. 54 (2016) 18.

  13. S.M.R. Hasan, Design of a low power 3.5-GHz broad-band CMOS, IEEE Trans. Circuits Syst. I 52 (2005) 10611072.

  14. <>M. Seifouri, P. Amiri, M. Rakide, Design of broadband transimpedance amplifier for optical communication systems, Microelectron. J. 45 (2015) 679684.

  15. J. Kim, J.F. Buckwalter, Bandwidth enhancement with low group-delay variation for a 40-Gb/s transimpedance amplifier, IEEE Trans. Circuits Syst. I 57 (2010) 19641972.

  16. P. Amiri, M. Seifouri, B. Afarin, A. Hedayati Pour, Design of RGC preamplifier with bandwidth 20GHz and transimpedance 60 dB for telecommunication systems, Tabriz, J. Electr. Eng. 46 (2016) 1523.

  17. D. Chen, S. Yeh, X. Shi, M.A. Do, C.C. Boon, W.M. Lim, Cross- coupled current conveyor based CMOS transimpedance amplifier for broadband data transmission, IEEE Trans. Very Large Scale Integer. (VLSI) Syst. 21 (2013) 15161525.

  18. Seifouri, M., Amiri, P., & Dadras, I., A transimpedance amplifier for optical communication network based on active voltage-current feedback, Microelectronics Journal, 67, 2531.

    doi:10.1016/j.mejo.2017.07.003.

  19. Chen, D., et al., Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2013. 21(8): p. 1516-1525.

  20. Ahmed, M.G., Talegaonkar, M., Elkholy, A., et al.: A 12 Gb/s 16.8 dBm OMA sensitivity 23 mW optical receiver in 65 nm CMOS, J. Solid- State Circuits, 2018, 53, (2), pp. 445457, doi:10.1109/JSSC.2017.2757008

  21. J. E. Proesel et al., "A 32 Gb/s, 4.7 pJ/bit Optical Link With 11.7 dBm Sensitivity in 14-nm FinFET CMOS," in IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 1214-1226, April 2018, doi: 10.1109/JSSC.2017.2778280.

  22. D. Mahgerefteh et al., Techno-economic comparison of silicon photonics and multimode VCSELs, J. Lightw. Technol., vol. 34, no. 2, pp. 233242, Jan. 15, 2016.

Leave a Reply

Your email address will not be published.