Improved 10-Bit 30-Ms/s SAR ADC using Switchback Switching Method

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Improved 10-Bit 30-Ms/s SAR ADC using Switchback Switching Method

Bhagya Lakshmi

M. Tech, VLSI and Embedded Systems, ECE

T. John Institute of Technology Bangalore, India

Dr. M. Puttaraju

Professor & HOD, ECE

  1. John Institute of Technology Bangalore, India

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    Abstract This brief presents an Improved 10-bit 30- MS/s Successive approximation register analog to digital converter (ADC) that uses a power efficient switchback switching method. Compared with the monotonic switching method and Vcm Based methods, the common mode voltage variation (Vcm) reduces which improves the dynamic offset and the parasitic capacitances variation of the comparator. The comparator consists of pre-amplifier and a dynamic latched comparator. The pre-amplifier is adopted to block kickback noise and enhance the comparison speed. The proposed ADC uses an asynchronous circuit to internally generate the signals. The switchback switching procedure does not consume any power at the first digital to analog converter switching conversion, which can reduce the power consumption. This method does not require fast settling reference buffer to charge MSB capacitor in the conversion phase as it provides longer settling time. The proposed switching procedure consumes only 127.5CV2 . The prototype is fabricated in a 90nm CMOS technology. At 1V supply and 30MS/s, the proposed ADC consumes 0.98mW.

    Keywords Analog to Digital Converter (ADC), energy efficient switching method, low input capacitance, successive-approximation-register (SAR) ADC

    1. INTRODUCTION

      Successive approximation register (SAR) analog-to- digital

      Converters (ADCs) require several comparison cycles to complete one conversion, and therefore have limited operational speed. SAR architectures are extensively used in low-power and low-speed (below several MS/s) applications. As the feature size of CMOS devices is scaled down, the propagation delay of logic circuit reduces. SAR ADCs have achieved several tens of sampling rates with 5 to 10-bit resolution.

      Several power efficient techniques have been proposed for the capacitive digital-to-analog in the past. If we compare the conventional switching technique, the energy saving [1], monotonic [2], and Vcm based [3] switching techniques reduce 69%, 81%, and 90% switching energy, respectively. The Vcm based reduces most of the switching energy but

      requires more switches and reference voltages which increases

      Fig. 2 Block Diagram of the proposed SAR ADC

      complexity of the digital circuits. The monotonic switching technique has less switches and reference voltage but during conversion phase common mode voltage varies from Vcm to Vref which induces dynamic offset and the parasitic capacitance variation.

      This brief proposes a SAR ADC which uses less switches and reference voltages and reduces 50% of common mode voltage variation. It does not consume energy at first switching hence reduces power consumption.

    2. ARCHITECTURE AND DESIGN OF PROPOSED SAR ADC

      1. SAR ADC Architecture

        Fig 2 shows the block diagram of the proposed SAR ADC.

        n – 2

        Eavg, switch = (2n 3- i) CV2ref

        i = 1

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        For monotonic [2] and Vcm [3] based techniques, the average switching energy can be expressed by the following equations. For 10-bit, the monotonic technique consumes 255.5CV2 and the Vcm based consumes 170.2CV2 .

        Fig. 4 Dynamic Comparator with Pre-amplifier

        Its core consists of two sampling capacitors, two capacitive reference DACs, dynamic-latched comparator and SAR control logic. The capacitive DAC is split into two parts: a reference DAC and a sampling capacitor. The analog signal is captured by sampling capacitor and reference signal is provided by the reference DAC.

        The switches Sa and Sb are turned during sampling phase and the signal is sampled onto sampling capacitors. The bottom plate MSB are connected to Vrefp and all LSBs are connected to Vrefn and reference DAC is at reset state. Next, the switches are turned off and the ADC begins the first conversion. The comparator compares whether Vip is higher than Vin if it is then MSB is set to 1 and if it is not then MSB is set to 0.

        The switchback switching method switches only one capacitor in each bit cycle, which reduces power dissipation. The common mode voltage of the switchback switching method would be downward for the first switching and then upward for the remaining cycles. The common mode voltage is reduced to ¼ Vref and approaches to Vcm.

        In fig. 3, first three switching phases is shown. According to switchback switching method, the bottom plate of MSB is connected to Vrefp and the rest are connected to Vrefn at the sampling phase. As soon as the sampling switches are turned off, the comparator directly performs first comparison without switching any capacitor and hence energy consumption is saved. The MSB is precharged in switchback procedure in sampling phase and allows longer settling time.

      2. Equations

      For switchback switching method, the average switching energy is given by

      Fig. 5 SAR Logic (a) Schematic (b) Timing Diagram

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      For 10 bit, the switchback switching method consumes 127.5 CV2 . This technique requires almost 50% less energy than monotonic and 25% less than Vcm based techniques.

    3. DESIGN OF BUILDING BLOCKS

  1. S/H Circuit

    The proposed SAR ADC uses sampling capacitors to sample input signal Csp and Csn, via the bootstrapped

    switches, Sa and Sb [9]. During conversion phase, Sa and Sb are turned off hence parasitic capacitance in drain terminal is less than 0.01fF. The Vdac are the voltages of comparator output and reference voltages and is given by

    Fig. 6 Schematic of Preamplifier

    Fig. 8 Schematic of Comparator

    Fig. 10 Schematic of SAR Logic

  2. Dynamic Comparator

    In Fig. 4, schematic of comparator is shown which consists of a pre-amplifier and a dynamic latched comparator. The proposed architecture uses preamplifier to block kickback noise which is generated by floating sampling capacitors and latched comparator due low capacitance and this increases speed.

  3. SAR Logic

    The proposed ADC uses an asynchronous control circuit

    to internally generate the necessary clock signals [5] to avoid a high-frequency clock generator and a pulse-width modulator. asynchronous phase generator.

    Fig. 7 Simulation result of Preamplifier

    Fig. 9 Simulation result of Comparator

    Fig. 11 Simulation of SAR Logic

    Fig. 5 shows a schematic and a timing diagram of the

    .When the clock is switched to low conversion process starts. Sampling switches are turned ON by Sample which is the sample signal. After ten comparisons, Sample will be set to 1 to sample the input signal until the system clock, Clk, switches to 0. Therefore, the duty cycle of the system clock, Clk, is 50% and no PWM is needed for the integration application. The dynamic comparator generates the Valid signal after each comparison. Clkc is the control signal of the dynamic comparator. P1 to P10 sample the digital output codes of the comparator and serve as control signals for the capacitor arrays to perform the switchback switching procedure.

  4. Results

Fig 6, Fig 8 and Fig 10 shows the schematics of preamplifier, comparator and 10 bit SAR logic respectively. The above schematics have been created in PSPICE. Fig 7, Fig 9 shows simulation results of preamplifier and comparator respectively

ACKNOWLEDGMENT

We take this opportunity to express our deepest gratitude and appreciation to all those who have helped us directly or indirectly towards the successful completion of this paper.

REFERENCES

  1. W. Y. Pang, C. S. Wang, Y. K. Chang, N. K. Chou, and C. K. Wang, A 10-bit 500-KS/s low power SAR ADC eith splitting capacitor for biomedical applications,in Proc. IEEE ASSCC Tech. Papers, Nov. 2009, pp. 149-152.

  2. C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure, IEEE J. Solid-State Circuits, vol. 45, no.4, pp. 731-740, Apr. 2010.

  3. Y. Zhu, C. H. Chan, U. F. Chio, S. W. Sin, S. P. U. R. P. Martins, and

    F. Maloberti. A 10-bit 100-MS/s reference free SAR ADC in 90nm CMOS, IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June. 2010.

  4. G. Y. Huang, C. C. Liu, Y. Z. Lin, and S. J. Chang, :A 10-bit 12 MS/s SAR ADC with 1.2-pF input capacitance, in IEEE ASSCC Dig. Tech. Papers, Nov. 2009, pp. 157-160.

  5. S. W. M. Chen and R. W. Brodersen, A 6-bit 600-MS/s 5.3-mW asyncronous ADC in 0.13-µm CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 574-575.

  6. V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, and

    J. Craninckx, An 820 µW 9b 40 MS/s noise tolerant dynamic-SAR ADC in 90nm digital CMOS, in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 238-239.

  7. M. Furta, M. Nozawa, and T. Italura, A 9-bit 80 MS/S successive approximation register analog to digital converter with a capacitor reduction technique, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 7, pp. 502-506, Jul. 2010.

  8. M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, A 10b 50MS/s 820mW SAR ADC with on-chip digital calibration, in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 384-385.

  9. A. M. Abo and P. R. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter, IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.

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