 Open Access
 Total Downloads : 1099
 Authors : Yogendra Kr. Upadhyaya, Dr. R. K. Sharma
 Paper ID : IJERTV2IS80641
 Volume & Issue : Volume 02, Issue 08 (August 2013)
 Published (First Online): 24082013
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Implementation of Frequency Down Converter using CORDIC Algorithm on FPGA
Yogendra Kr. Upadhyaya #1
Electronics and Communication Engineering National Institute of Technology Kurukshetra
Haryana, INDIA
Dr. R. K. Sharma *2
Electronics and Communication Engineering National Institute of Technology Kurukshetra
Haryana, INDIA
AbstractIn a communication system, the received signals are of high data rates making it difficult to process the signals to extract information of interest. So to solve this problem DDC makes a better solution. In this efficient way of designing and implementing a Wideband Digital down converter has been discussed. Though the received signal is RF signal with high data rates, IF stage is used to frequency shift the signal to fixed IF which is input to ADC. This is sampled and given as input as input to DDC.CORDIC generator is used instead of numerically controlled oscillator (NCO).
It is shown that filter bandwidth varies by decimation factor. Decimation range in this paper is 2 to 16384. Filtering is implemented in stages to obtain efficient response. Xilinx 13.2 version is used to simulate each block of DDC at system level testing and Sparten3 FPGA with speed 4 is hardware used implementing the design.
KeywordsWideband Digital down converter, ADC, Baseband signal, Decimation CORDIC generator, FPGA, System level, Board level testing.

INTRODUCTION
Communication plays vital part in day to day life for transfer of information. Though there are different modes of communication at present Digital Communication is more popular. It is a process of transferring signals, in digital format
i.e. as bits. A transmitter, channel and receiver are the main blocks of communication system. The DDC presented in this paper is the key component of Receiver. The digital IF signal from ADC depends on the band of interest as the Nyquists theory states that signal should be sampled at rate at least double the bandwidth of interest. A DDC allows the frequency band of interest to be moved down the spectrum to baseband signal near to 0 HZ such that further processing on signals become easier. Later techniques are involved for varying the filter specifications to extract the signal of interest. The remainder of this paper is structured as follows: Section
2 provides an overview of Digital down Converter. Section 3 mentions the steps involved in converting IF signal to base band signal. Section 4 is about filtering and decimation. Section 5 gives a detailed explanation on implementing the design on FPGA. Section 6 provides Simulation results and the last section.

OVERVIEW OF DDC
Down Conversion involves the process of the shifting a high rated signal to a standard signal. Generally the receivers receive wide band of signals but end user may only require a small portion of the entire band. So fulfilling the above requirement might involve prohibitively large filters. A variable decimation DDC makes this process easier.
A DDC consist of four basic blocks

CORDIC(Coordinate Rotation by Digital Computer)

Mixer

VARCIC(Variable Cascaded Integrated Comb) filter

CIC (Cascaded integrated Comb) filter

FIR(Finite Impulse Response ) filter

CORDIC Algorithm:The CORDIC (Coordinate Rotation Digital Computer) was developed by Jack Volder in 1959

as an iterative algorithm to convert between polar and Cartesian Coordinates using shift, add and subtract operations only. It can be implemented with shift add/subtract type algorithm. It can also be used to compute trigonometric functions. Examples sine, cosine, polar to rectangular coordinates etc.

Y
Vn(Xn,Yn)
V0(X0,Y0)
X
Fig.1 Vector V rotating with phase
In circular rotation made a CORDIC function could compute the Cartesian Coordinates of the target vector Vn by rotating the input vector V0 by an arbitrary angle =z0. so how do we calculate Xn and Yn based on input vector and angle
Xn = X0 cos Y0 sin
Yn = Y0cos + X0 sin Xn = cos(X0 Y0 tan) Yn = cos(Y0 + X0 tan)
So far, nothing is simplified however if rotation angles are restricted so that tan =,the multiplication by tangent term is
reduced to simple shift operation.tan =Â±20 ,21, 22,23
Table:1 for 8bit CORDIC Hardware
as part of a system processing gain. The product approaches 0.6073 as the number of iterations goes to infinity. Therefore, the rotation algorithm has An, of approximately 1.647. The exact gain depends on the number of iterations and obeys the relation
An=1 + 22
It also needs to be noted that the previous equations are valid for rotation angles between
/2 /2
In order to increase the convergence range for all rotation angles Z0< volder proposed an intial iteration which rotates the input vector by Â±/2
0
0
X =d.Y0
i
di=2i= tani
i=arcta n(2i)
iin radains
0
1
450
0.7854
1
0.5
26.5650
0.4634
2
0.25
14.0360
0.245
3
0.125
7.1250
0.1244
4
0.0625
3.5760
0.0624
5
0.3125
1.78760
0.0312
6
0.015625
0.89380
0.0156
7
0.0078125
0.44690
0.0078
i
di=2i= tani
i=arcta n(2i)
iin radains
0
1
450
0.7854
1
0.5
26.5650
0.4634
2
0.25
14.0360
0.245
3
0.125
7.1250
0.1244
4
0.0625
3.5760
0.0624
5
0.3125
1.78760
0.0312
6
0.015625
0.89380
0.0156
7
0.0078125
0.44690
0.0078
Y =d.X
0 0
Z =Z d.
0 0 2
But what if my desired angle of rotation is not exactly one of these values. The desired angle of rotation is obtainable by performing a series of successively smaller elementary
rotations where i=0——–n1 for tan = Â±2i
Let say our desired rotation is 30 degrees.
Where d= +1 if Z0<0
1 otherwise
The elementary angles can be expressed in any convenient angular unit. Those angular values are supplied by small lookup table (one entry per iteration) or they are hardwired depending on implementation. The angle accumulator adds a third difference equation to CORDIC
Table:2 choosing the signs of the rotation angles to force z to zero
algorithm.
Zi+1=Ziditan
1(2i)
i
zii
zi+1
0
30.045.0
15
1
15+26.6
11.6
2
11.614.0
2.4
3
2.4+7.1
4.7
4
4.73.6
1.1
5
1.11.8
0.7
6
0.7+0.9
0.2
7
0.20.4
0.2
8
0.2+0.2
0
9
0.00.1
0.1
We start at iteration 0 with an angle of Z0=300.If the angle Zi>0 then we subtract the tan() angle, otherwise we add the tan() angle and make our approximate Xi and Yi calculations.
Xn = cos(X0 Y0 tan) Yn = cos(Y0 + X0 tan)
If the decision at each iteration i, is which direction to rotate rather than whether or not to rotate then the cos(i) term becomes a constant because cos(i)=cos(i). In other words the cos (i) is not dependent on direction of rotation. The iterative rotation can now be expressed as:
Xi+1=Ki [Xi diYi2i] Yi+1=Ki [Yi +diXi2i] Ki=cos (tan1(2i)
K = 1
Thus we now have a set of accumulation
equations to use for each iteration[2]
Xi+1=Ki [Xi diYi2i] Yi+1=Ki [Yi +diXi2i] Zi+1=Ziditan1(2i)
Where d= +1 if Z0<0
1 otherwise
Where di determines the direction for each elementary rotation. Therefore after n iterations the CORDIC equations
Xn =An [X0 cos (z0) Y0 sin(z0)] Yn =An [ Y0 cos(z0) + X0 sin(z0)] Zn =0
Where An is originally expected gain.
Therefore a CORDIC function could be used to rotate vectors.We define a vector where X0=0
Xn An Y0 sin(z0)
Yn An + X0 sin(z0)
By selecting Y0 equal to 1/An, the rotation produces the unscaled sine and cosine of angle argument z0, very often the sine and cosine module a magnitude value. Using other techniques such a sin0/cos0 lookup table requires a pair of multipliers to obtain the modulation. The CORDIC technique performs the multiply as part of the rotation operation and therefore eliminates the need for a pair of explicit multipliers.



MIXER
i (1+22)
di=Â±1
Removing the scale constant from iterative equations yields a shiftadd algorithm for vector rotation. The product of Kis can be applied elsewhere in system or treated
Signal modulation involves changes made to sine waves in order to encode information. The mathematical equation representing a sine wave is as follows
SBP(t) = A cos(2ft+)
Where A is amplitude, f is frequency and is phase.
SBP(t) = A cos(2ft+)
SBP(t)=A cos(2ft) cos – A sin(2ft) sin N N
If I= A cos
Q=A sin
Acos(2ft+) = I cos(2ft) Q sin(2ft)
Where I is the amplitude of in phase carrier
Z Z Z Z
– –
. . . .
Q is the amplitude of quadraturephase carrier.
Remember that difference between a sine
wave and cosine wave of the same frequency of is 90degree phase offset between them. The implication of this are very
fs .
fs fs/
D
Fig. 2 CIC Filter
. fs/
R
important what this essentially means is that we can control the amplitude, frequency and phase of modulating RF carrier sine wave. We can achieve the same effect by manipulating the amplitudes of input I and Q Signals. Of course the second half of equation is a sine wave and first half is a cosine wave so we must include a device in the Hardware circuit to induce
a 90 degree phase between the carriers but this is a much
Each integrator contributes to the CIC transfer function
with a pole. Each comb section contributes with a zero of order D, where D is the frequency decimation ratio. The CIC transfer function in the Zplane becomes:
Frequency Characteristics:
The transfer function for a CIC filter at fs is
simpler design issue than direct phase manipulation.
If:
simpler design issue than direct phase manipulation.
If:
H (z) H N (z) H N (z)
H (z) H N (z) H N (z)
1 z D
N
1 z D
N
D 1
D 1
zk
zk
N
N
I = A cos
I = A cos
1 z
1 z
1
1
k 0
k 0
I C N
Q = A sin

CIC Filter
The cascaded integratorcomb (CIC) filter is a class of hardwareefficient linear phase finite impulse response (FIR) digital filters [6]. The CIC filter is suitable for this highspeed application because of its ability to achieve high decimation factors and other reason is it is implemented using additions and subtractions rather than using multipliers. It decimates by R which is programmable. The two basic building blocks of a CIC filter are

An integrator (decimator): An integrator is simply a single pole IIR filter with a unity feedback coefficient [9],[10]
y [n] = y [n1] + x[n]
This system is also known as an accumulator [9],[10]. The transfer function for an integrator on the zplane is
HI ( z ) = 1/(1 z1)
We must be careful here because we have two sampling frequencies in the system, related by D. If we evaluate the z transference at the output sampling frequency z=exp(j2fs/D),The magnitude response at the output of the filter is as shown below[3] .We can obtain an expression for the CIC filter's frequency response by evaluating Hcic(z) transfer function on the zplane's unit circle, by setting z =
ej2, yielding a sinc like function.
As already mentioned the frequency response of CIC filters is affected by the parameters N, M, R. Differential delay, M, affects the location of nulls at any given rate change value and increases attenuation levels generally at all lobes in the response. Varying the rate change value, R, adjusts the null positions up or down accordingly without having much affect on the attenuation of each lobe and increasing the number of stages increases attenuation of the lobes without shifting null
positions.
slow sampling rate fs/R is described by
H ( f ) D. for D 1
sinf / D
f
sinf / D
f

Comb Filter (Interpolator): A comb filter running at the
y[n] = x[n] – x[n D].
A comb filter is a differentiator with a transfer function
HC (z) = (1 zD)
In this equation, M is the differential delay, and is usually limited to 1 or 2. To summarize, a CIC filter would have N cascaded integrator stages clocked at fs, followed by a rate change by a factor R, followed by N cascaded comb stages running at fs/R [10]
sinf N sinf N
f
f
Compensation FIR filter:
The output of the CIC filter has a sinc shape, which is not suitable for most applications. A cleanup filter can be applied at the CIC output to correct for the pass band droop, as well as to achieve the desired cutoff frequency and filter shape.This filter typically decimates by a factor of 2 or 4 to minimizethe output sample [3],[10].
Fig. 4 Magnitude Response of CFIR Filter


Simulation Results:
CORDIC Based Generator
Fig.5 RTL Schematic view of CORDIC
Fig.6 RTL Schematic view of CIC Filter
Fig.7 RTL Schematic view of FIR Filter
Fig.8 RTL Schematic view of CORDICDDC
Fig.9 Output for input Xin=1 & Yin=1 in quadrant I
Fig.10 Output for input Xin=0 & Yin=0 in quadrant I
Fig.11 Output for input Xin=1 & Yin=0 in quadrant I
Fig.12 Output for input Xin=1 & Yin=0 in quadrant II
Fig.13 Output for input Xin=1 & Yin=1 in quadrant III
Fig.14 Output for input Xin=0 & Yin=1 in qadrant III
Fig.15 Output for input Xin=1 & Yin=1 in quadrant III
Fig.16 Output for input Xin=0 & Yin=1 in quadrant IV
Fig.17 Output for input Xin=1 & Yin=0 in quadrant IV
Fig.18 Output for input Xin=1 & Yin=1 in quadrant IV
Fig.19 Output of CIC filter for different inputs
Fig.20 Output of Low Pass Filer
used in the context of digit down conversion of frequency synchronization, the additional hardware effort is partly compensated because there is no need for explicit multiplier. This is where our previously shown CORDIC sin0/cos0 functions come in
Xn =An Y0 sin(z0) Yn =An + X0 sin(z0)
Where X0 set to 0.This will allow to create a CORDICDDC.
At each clock interval,Y0 is loaded with current samples SBP(k) of an IF input signal and Z0 with the current sample (k).The latter is supplied by an overflowing phase accumulator which generates the oscillator frequency f0.X0 is set to zero. After n+1 iterations the CORDIC provides the samples I(k) and Q(k) of down converted in phase and quadraturephase signal with a resolution of approximately n bits. In order to achieve this, only a very small lookup table is needed. It contain the n+2 basic rotation angles. Still the main problem of the CORDIC is that (n+1) iterations have to be performed for each signal sample requiring an internal clock rate being (n+1) times higher than sample rate of the signal. However the CORDIC can be implemented by pipelined arithecture which eliminates the n+1 factor. Thus the CORDICDDC becomes suitable for the high speed applications.
An additional advantage of such an implementation is that there is no need for lookup table anymore, since the invariant
elementary rotation angles can be hardwired to each pipeline stage. In other words a specific tan1() will always be used for each pipeline stage.
Fig.21 Output of CORICDDC
Fig.22 Sine wave on CRO through FPGA Sparatn3E
CORDICDDC: An approach to overcome this drawback is the calculation of the corresponding sin0/cos0 values by means of CORDIC with the main advantage of using only a small look up table(~nÃ—n bit).The major drawback of CORDIC approach is increased circuit complexity. However it

CONCLUSION:
The CORDIC algorithm is powerful and widely used tool for digital signal processing applications and can be implemented using PDPs (Programmable Digital Processor) But large amount of data processing is required because of complex computations. This affects the cost, speed and flexibility of DSP system. So the implementation of DDC (Digital Down Converter) using CORDIC algorithm on FPGA is need of day as the FPGA can give enhanced speed at low cost with lot of flexibility. This is due to the fact that hardware implementation of a lot of multipliers can be done on FPGA with are limited in case of PDPs. It can be concluded that the desiged.RTL model for CORDIC and DDC is accurate and can work for real time applications.
The number resolution of frequency increases the size of the ROM/LUT for CORDIC increases exponentially. This reduces the speed of DDC and increases the size of hardware. This issue of increase in the size of ROM/LUT can be solved by using memory reduction techniques like phase truncation and quadrature symmetry of sine wave. In our design we have implemented a 12 bit DAC on SPARTAN 3E board and analyze the effect of frequency using CORDIC algorithm.
vii. FUTURE SCOPE
CORDIC algorithm is implemented in large FFT instead of Booth Multipliers, OFDM system, in DCT and in DWT using PipelinedParallel algorithm. CORDICDDC is implemented in SDR (Software Defined Radio) and beam loss accounting system.

Advanced Digital Design with Verilog HDL PHI Learing Private Limited 3rd edition, 2005.

Field programmable gate array, S. Brown, R.J.Francis, J.Rose ,Z.G.Vranesic, 2007, BSP.
REFERENCES

J.E.Volder: The CORDIC trigonometric comp. technique.IRE Trans. Elec. Comp.(1959), vol. EC 83, pp. 330334.

Ray Andraka: A survey of CORDIC algorithms for FPGAs .Proceedings of the 1998 ACM/SIGDA 6th international symposium on FPGAs, Monterey, CA (1998), pp191200.

GC4016 Multistandard Quad DDC Chip Data Sheet, Rev. 1.0. August 2001, Texas Instruments. (Formerly Graychip Inc.). Document: slws133a.pdf.

Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J.M. Smit
An Optimal Architecture for a DDC 2006 IEEE.

Stephen Creaney and Igor Kostarnov Designing Efficient Digital Up and Down Converters for Wide band Systems. XAPP1113 (v1.0) November 21, 2008.

T.Hollis / R.Weir, Theory of Digital Down Conversion, Hunt Engineering, 2003.Rev 1.2.

Xilinx DDS Compiler v2.1, Product specification DS5558 March 21,2008.

E. B.Hogenauer. An economical class of digital filters for decimation and interpolation. IEEE Transactions on Acoustics, Speech and Signal Processing, ASSP29(2):155{162, 1981.

Alan Y. Kwentus, Zhongnong Jiang, and Alan N. Willson. Application of Filter Sharpening to Cascaded IntegratorComb Decimation Filters. IEEE Transactions on Signal Processing, Vol. 45, No. 2, February 1997 457.

Alteras application note 455 April 2007,
Understanding CIC compensation filter ver. 1.0.

Alan V. Oppenheim and Ronald W. Schafer. DiscreteTime Signal Processing. PrenticeHall Signal Processing Series. PrenticeHall, Englewood Cliffs, 1989.

IEEE Transactions on Acoustics, Speech and Signal Processing,Vol. ASSP23, no. 5 , October 1975 Optimum FIR Digital Filter Implementations for Decimation, Interpolation, and NarrowBand Filtering.

R. R. Shively, On multistage FIR filters with decimation, IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP23, pp. 353357, Aug. 1975.
