 Open Access
 Total Downloads : 570
 Authors : Khushboo, Jubli
 Paper ID : IJERTV2IS120988
 Volume & Issue : Volume 02, Issue 12 (December 2013)
 Published (First Online): 25122013
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Implementation of Cascade Amplifier in 180nm CMOS Technology
Khushboo, Jubli
Electronics & Communication Engineering Northern India Engineering College
FC26, Shastri Park, Delhi110053, India
Abstract
This paper described about the complete analysis and design of common source amplifier designed for application in a capacitivemicro machinedultrasonictransducer (CMUT) based intravenous imaging system. These CMUTs have recently gained much interest due to their numerous advantages as ultrasound transducers that can be integrated with electronics on silicon and are compact. In this paper the workability of the feedback biasing cascade amplifier circuit configurations has been analysed and tested experimentally using PSPICE and MATLAB simulation tool. It has been found that the new propositions have improved performance such as gain and bandwidth. The results have been taken on 180nm technology. It gives the derivations of all the equations described in the paper like, closed loop gain of negative feedback amplifier, transfer function, drain current equation, stability factor, FOM etc. The Simulation result of the CS amplifier with feedback biasing in 180nm CMOS technology using PSPICE and compared this with the MATLAB plot of the transfer function of the same.
KeywordsCascade amplifier, CMUT, CLOSED loop gain and bandwidth, stability factor, CS amplifier, 180nm CMOS technology.

Introduction
The Nanoscale technologies can be a viable option for the analog circuitry as well. Some of the features of Nanoscale technologies that are otherwise not desirable to an analog designer may actually be useful in some circuit techniques, as we will show in this brief for the case of feedback biasing. Even though a feedbackbiasing scheme is simple and ensures that the input MOSFET remains in saturation, irrespective of the process and temperature variations, its biggest disadvantage has been the limited voltage swing. We show that this disadvantage vanishes as one move to Nanoscale technologies [1]. Simulation and experimental results [1], presented therein for validation of the ideas, were for Feedback biased Cascade amplifier designed for application in a capacitivemicro machinedultrasonictransducer (CMUT) based intravenous imaging system. A number of works on CMUT operation and applications are available. Application of ultrasonic imaging fields such as dermatology,ophthalmology and cardiovascular
medicine require very high frequency resolution. CMUTs can be made for high frequency operation. CMUT is an appropriate technology for building very high frequency arrays. A linear array of high voltage pulsar and amplifier circuits has also been designed for use with an array of CMUTs to enable real time imaging applications [7]. Due to the requirement of having an array of several transducers with local signal conditioning on a catheter tip for performing imaging inside the human arteries, the compactness of the circuitry is of utmost importance, followed by the constraint on the power consumption of the system. It is for this reason that a cascade amplifier topology is designed for this application, as the cascade amplifier is one of the most efficient amplifier stages that can be realized in CMOS technology [6]. To realize the biasing within a very small area sub threshold MOSFETs as highvalue resistors have been employed to bias amplifiers [1]. The article rediscovers the attractiveness of feedback biasing when applied to circuits designed in Nanoscale CMOS technologies. It is shown that very compact amplifiers can be obtained by utilizing a type of biasing that imposes minimal area overhead. It presents measurement results of commonsource (CS) amplifiers using feedback biasing designed for application in a capacitive micro machined ultrasonic transducer 30MHz (CMUT). The proposed feedback biasing is also suitable for amplifying signals from high impedance sources that pose challenges on maintaining high input impedance for the voltage amplifiers while maintaining a very low input capacitance value. Here CMUTs can be integrated with electronics on silicon and are compact.
The basic idea behind the cascade amplifier is it can be designed to increase the DC gain and the gainbandwidth. We have presented feedback biased cascade amplifier, to increase the overall gain and bandwidth simultaneously. The paper discovers the attractiveness of feedback biasing when applied to circuits designed in NanoscaleCMOS technologies. Utilizing a type of biasing very compact amplifiers can be obtained that cover minimum area in the NanoscaleCMOS technologies where the biasing point has found to be more stable
The proposed feedback biasing is also suitable for amplifying signals from high impedance sources that pose challenges on maintaining high input impedance for the voltage amplifiers while maintaining a very low input capacitance
value. The amplifiers were fabricated in 180nm CMOS technology and measured to be just 20Âµm x 10Âµm.

FEEDBACK BIASING IN NANOSCALE CMOS TECHNOLOGIES
The four basic feedback topologies

Voltage amplifiers: – It amplifies an input voltage signal and provides an output voltage signal. A suitable feedback topology for the voltage amplifier is the voltagemixing

Current amplifiers: – It amplifies an input current signal and provides an output current signal. A suitable feedback topology for the current amplifier is the currentmixing current sampling.

Trans conductance amplifiers: – It amplifies an input voltage signal and provides an output current signal. A suitable feedback topology for the Trans conductance amplifier is the voltagemixing current sampling. It is also called as seriesseries feedback. We have used Tran conductance amplifier for our amplifier.

Trans resistance amplifiers: – It amplifies an input current signal and provides an output voltage signal. A

DC Analysis Equations
VDD VDS=0 (1)
VDD = IDRD + VDS
VDD – IDRD VGS=0 (2) VDD = IDRD + VGS
After comparing equation (1) & (2) IDRD + VDS = IDRD + VGS
VDS = VGS (3)
i.e. Output voltage is controlled by Input voltage.
In above fig.1, the voltage drop across RG is zero & IG = 0. Output is taken across VDS,
So VDS = Vout i.e. Vout = VGS (4) We know VDS = VGS so put it in equation no. (1)
VDD = IDRD + VDS
VDD = IDRD + VGS
suitable feedback topology for the Trans resistance
V = V
+ I R
(5)
amplifier is the currentmixing voltage sampling. It is also called as shuntshunt feedback

BASIC ANALYSIS OF FEEDBACK BIASING

DC Analysis
VDD
DD GS D D
Next we have to drive the equation: VOUT_MIN VDS_MIN VT
As we know VT = Threshold voltage.
The value of VGS at which a sufficient no. of mobile
RD ID
0
RG
ID
+
Vout
electrons accumulates in the channel region to form a conducting channel is called the Threshold Voltage. Its value varied between 0.5 to 1.0 V.
When VGS = VT(induced channel), but at this point ID (drain current) is usually very small.
As VGS> VT, increased conductance, & reduce resistance.
VGS
–
Fig.1NMOS with feedback biasing
VDD
In fact the conductance of channel is proportional to the excess gate voltage (VGS VT) also known as the Effective voltage or the Overdrive voltage.
It follows that the current ID will be proportional to VGS VT and of course to the voltageVDS that causes ID to flow.
RG CD
Vin
RD
Req
Vout
Fig.2 when used as a voltage amplifier with a low impedance source.
Fig.3 Operation of enhancement NMOS Tr.
VOUT_MIN = Put ID = 0
VDDVSS 2
VT
VDD = VDS+VSS
VDDVSS
ID =
RD
Tr.
Fig.4 ID versus VDS plot for enhancement type NMOS
When VDS increased that reduces the voltage between gate and drain end to VT,
I.e. VGD = VT Or
VGS VDS = VT VDS = VGS VT
The channel depth at the drain end decreased to almost zero,
and the channel is said to be Pinched off at this point it
Fig.6 DC load line
For faithful amplification the quiescent point Q will be on the middle of the load line.
VDDVSS
enters the saturation region of operation. The voltage VDS at which saturation occurs is denoted VDSsat,
VDSsat = VGS VT
So VOUT_MIN =
2
VDDVSS
VT (9)
Or
VOUT_MIN VDS_MIN VGS_MAX VT (6)
Where
= VGS_MAX
2
Bias Point calculation
Equ.no. (9) is the minimum output voltage to give the faithful amplification.
VDD
RD
V2
Assume amplifier gain is high i.e. AV =
V1
is high.
RG
+
VGS
–
VDS
VSS
Vout
It means that the value of V1 should be kept low in order to not clip off the input voltage.
When Q shifted towards the yaxis i.e. ID side, the positive peaks of the output signal would be clipped off, because the MOSFET would turn off for part of the cycle. It is called as the circuit not having sufficient headroom.
When Q shifted towards the xaxis i.e. VDS side, the output signal is distorted. It is called as the circuit not having sufficient legroom.
Fig. 5 NMOS with feedback biasing
VDD VDS VSS = 0
VDD = IDRD+VDS +VSS (7)
Put VDS = VGS
VDD VGS VSS = 0
VDD = IDRD+VGS +VSS (8)
From equ.no.(7) plot DC load line to obtain the given equation:

HIGH FREQUENCY ANALYSIS OF FEDDBACK BIASING
At high frequency we include the internal MOSFET capacitance also.
And at high frequency the feedback biasing figure is also improved
Here, CGD=CG; CGS=CIN; CDS= CL
VDD G D
RD
CG RG
Vout
Vt ro
gmVGS
RD R'G
CL
CIN
Vout
Vf
CL
Cin
S S
Fig. 9 (a) High frequency model of the circuit
G D
Fig.7(a) Schematic showing a feedback biased amplifier, with important impedances shown
VDD
Vt
gmVGS
S
Rout R'G
CL
CIN
Vout
Vf
S
CG RG
Cin
RD
+ +
Vf Vt
– –
Vout
CL
Fig. 9(b) High frequency model of the circuit
Gm = Transconductance of the MOSFET. The control that the VGS has over the ID is measured by
ID
Fig. 7(b) Feedback loop is broken to calculate the loop gain
Gm =
VGS
constant VDS.
MOSFET CAPACITANCES
Based on their physical origins, the parasitic device capacitance can be classified into two major groups:

Oxide related capacitances: – The two overlap capacitances
Fig. 2.9(b) is used to calculate the loop gain response of the feedback, as expressed in [1].
Vf(s)
that arise as a result of this structural arrangement as shown
LG(s) =
V (s)
in figure (8) are called CGD are voltage independent.
(overlap) and CGS
(overlap). They t

Junction capacitances: – The voltage dependent source
1 1sC
substrate and drainsubstrate junction capacitance are, C
= gm Rout
IN
and C .
SB
sCL
1 1
DB RG +
CGD
D
CGB
CDB
Rout
sCG
1
sCIN
G
CGS
MOSFET B
(DC MODEL)
CSB
LG(s)= gm sRGCG (10)
1+sRoutCL 1+sRG CG+CIN
Apply KCL
S
Fig. 8 Lumped representation of the parasitic MOSFET
Vout 1 +sCL+ 1 = gmVGS
capacitances
Here, CGD=CG; CGS=CIN; CDS= CL
In order to obtain this loop gain response we have to make the
Rout
Z= R'G+
Z
1
high frequency model of this feedback biasing method. High frequency analysis (equivalent circuit)
Where
Z=
sCIN
sR'GCIN + 1 sCIN
& R`G = RGCG & Rout = roRD
Vout 1
+sCL+
sCIN
= gmVGS
Io R'G+ 1
Rout
sR'GCIN+1
& VOUT =
sCIN
1sR'GCIN+1+sCLRout 1+R'GCIN +sCINRout
Vout = gmV
1
gmVGSRout 1+sCINR'G
Rout sR'GCIN+1
GS
IoR'G+ =
sCIN
sR'GCIN+11+sCLRout +sCINRout
Vout sR'GCIN+11+sCLRout +sCINRout =gmVGSRout sR'GCIN+1
sR' C +1 gmV R 1+sC R'
gmVGSRout sR'GCIN+1
Io sC = sR' C +11+sC R +sC R
G IN GS out IN G
G IN GS out IN G
Vout =
IN G IN L out IN out
Vout = Vin
sR'GCIN+11+sCLRout +sCINRout
gmVGSRout sR'GCIN+1
sR'GCIN+11+sCLRout +sCINRout
Io= gmVGSRout 1+sCINR'G Ã—
sR'GCIN+11+sCLRout +sCINRout
Io= gmVGSRoutsCIN
sCIN
sR'GCIN+1
RG
RG=RGCG = sRGCG+1
gmRout 1 sRGCIN
sR'GCIN+11+sCLRout +sCINRout
1
&Vf = IO Ã— sCIN
Vout
sRGCG 1
Vin
1 sRGCIN 1 sCLRout sCINRout
Vf(s)=
gmVGSRoutsCIN Ã—
sR'GCIN+11+sCLRout +sCINRout
1 sCIN
sRGCG 1
gmRout sRGCIN sRGCG 1
Where V = V
Vout
sRGCG 1
GS t
Vin
sRGCIN sRGCG 1 1 sCLRout sCINRout
gmVGSRout 1+sCINR'G sC
G IN L out IN out
G IN L out IN out
sRGCG 1 IN
gmRout sRGCIN sRGCG 1
Io= sR' C +11+sC R +sC R Ã—
sR'GCIN+1
Vout
sRGCG 1
Vin
sRGCIN sRGCG 1 1 sCLRout sCINRout sRGCG 1
sRGCG 1
We know R`G = RG CG
Vout gmRout sRGCIN sRGCG 1
RG 1 sCG RG
=
Vin sRGCIN sRGCG 11 sCLRout sCINRout sRGCG 1
RG 1 sCG sRGCG+1
=
=
Vout gmRoutsgmRoutRGCINsgmRoutRGCG 2
Vf(s) gmRout
Vin s RGCINCLRout+RGCGCLRout+CINRoutRGCG +sRGCIN+RGCG+CLRout+CINRout+1
Vt(s)
sRGCIN 11+sC Rout sC Rout
sR C +1
L IN
G G
Vout = gmRoutsgmRout RGCIN+RGCG
Vin s2 RGCINCLRout+RGCGCLRout+CINRoutRGCG +sRGCIN+RGCG+CLRout+CINRout+1
(3.19)
Vf(s) gmRout
Vt(s) sRGCIN+sRGCG+11+sCLRout+sCINRout sRGCG+1
sRGCG+1
Vf(s) = Feedback voltage Vt(s) = Input voltage
Vf(s) gmRout sRGCG+1
Vf(s)
Vt(s)
= gmRout 1+sCGRG
sRG CIN+CG +11+sCLRout
Vt(s)
sRGCIN+sRGCG+11+sCLRout+sCINRout sRGCG+1
Now divide numerator and denominator by
RoutÃ— 1sC 1sC
= gm L IN
sCINRout 1+sRGCG
Rout+ 1sC
RGÃ— 1
L sCG + 1
Vf(s)
gmRout 1+sRGCG
sCINRout 1+sRGCG
Rout+1/sCG sCIN
=
Vt(s)
1+sRGCG+sCINRG 1+sRoutCL
sCINRout 1+sRGCG
RoutÃ— 1 1
sCINRout 1+sRGCG
sCINRout 1+sRGCG
= gm sCL sCIN
+
+
Rout+ 1sC
RGÃ— 1
L sCG + 1
gm
Rout+1/sCG sCIN
Vf(s) =
– sC
sCINRout 1+sRGCG
1
1
IN
R
Vt(s)
1+sRGCG+s2CINRG1+sRoutCL
= gm
out
sCIN
1+sRoutCL sRGCIN+ 1+sRGCG
Vf(s) =
Vt(s)
gmRout 1+sRGCG
1+sRG CG+CIN 1+sRoutCL
sCIN 1+sRGCG
1+sRoutCL 1+sRG CG+CIN
1+sRoutCL 1+sRG CG+CIN
= gm Rout 1+sRGCG
Vf(s)
Vt(s)
= gmRout
1+sRoutCL
Ã— 1+sRGCG
1+sRG CG+CIN
LG(s) = Vf(s) = gm Rout 1+sRGCG (13)
(11) Vt(s) 1+sRoutCL 1+sRG CG+CIN
Vf(s) = gmRoutsgmRoutRGCG
Vt(s) s2 RGRoutCGCL+RGRoutCLCIN +sRoutCL+RGCG+RGCIN +1
or
The loop gain response has a dc gain (gmRout)
When RG>> Rout & CL&CIN are of the same order the dominant pole of the loop gain response is set by the RC product at the input node i.e. RG (CG + CIN).
Vf(s)
Vt(s)
sRGCIN
gmRout
LG(s)= gm Rout 1+sRGCG = Zeros
sR C +1 11+sCLRout sCINRout
1+sRoutCL 1+sRG CG+CIN
Poles
G G
=
=
Vf(s) gmRoutsgmRoutRGCG
Ist pole:
Vt(s) s2RGRout CGCL+CLCIN+CINCG +sRoutCL+RGCG+RGCIN+RoutCIN 1
1 +sRG (CG
+ CIN
) = 0
(12)
Rechecking the above equation no. (12) from
sRG (CG + CIN) = 1
s =
s =
1
bottom to top,
RG CG+CIN
(14)
LG(s) =
Vf(s)
Vt(s)
1
IInd pole:
(1 + sCL Rout) = 0
sCL Rout = 1, s =
1
(15)
R C
= gmRout 1sC
sCIN
out L
L
RoutÃ— 1sC
RG
1
sCG
1
sC
+ 1 sCIN
Zeros:
gm Rout (1+ sRGCG) = 0
1+sRGCG = 0
sRGCG = 1
= gm L IN
Rout+ 1sC
RGÃ— 1 1
L sCG + 1
s = (16)
RGCG
Rout+1/sCG sCIN
jwaxis(imaginary axis)
So B1 =
1
RG CG+CIN
RGRoutCL CG CIN 1
RG CG CIN 0
2nd pole wt
0
1st pole
Real axis Wt=unity gain frequency
1
R
R
B1 = Ã— RG CG+CIN G CG+CIN
Fig. 10Poles & Zero
Splane
B1 = 1
So all the coefficients in the first column are of the same
Assuming that CIN>> CG, it lies at much higher frequencies than the dominant pole.So Ist pole is the dominant pole.Assuming the IInd pole is lies far beyond its unity gain frequency ft.One can estimate wt as the product of the dc gain & the frequency of the dominant pole i.e.
sign (positive), the given equation has no roots with positive real part. Hence the system is stable. Since the input signal VIN to the amplifier shown in Figure (3.13) (a) is capacitive coupled (By CD) to the gate of the MOSFET. CD forms a HPF (High pass filter) with REQ.
Wt =
gmRout RG CG+CIN
gmRout (17)
RGCIN
The loop gain is less than unity beyond the 3dB frequency hence the feedback loop is disabled beyond this frequency and the amplifier operates effectively in open loop. Therefore the feedback loop while biasing the MOSFET
Where CIN>>CG
Ft = unity gain frequency
Dominant pole = It is the pole which is near to zero (origin)
does not interfere with the signals beyond W3dB.
Resistance REQ appears due to the miller effect at the gate of the MOSFET i.e.
RG
so that it dominate the amplifier frequency response; it is called a Dominant pole.Check the stability of the system using Routh Hurwitz criterion:
Let the equation aosm + a1sm1 +. + am = 0

All the coefficients of the equation should have same sign.

There should be no missing term.
These two conditions are necessary to make the system stable.
REQ =
Vin
1AV
RD
RG CD
Req
VDD
Vout
(18)
1+sRoutCL 1+sRG CG+CIN
1+sRoutCL 1+sRG CG+CIN
Apply this criterion to our loop gain response LG(s): LG(s) = gm Rout 1+sRGCG
HPF
Fig. 11(a) When used as a voltage amplifier with a low impedance source.
(1 + sCL Rout)(1 + sRGCG + sRGCIN) = 0
S2RGRoutCL (CG + CIN) + sRG(CG +CIN) +1 =0 S2 RGRoutCL(CG + CIN) 1
REQ1=RG/(1AV) REQ2=RG(11/AV)
RG
VDD
RD
Vout
S1 RG (CG +CIN) 0
S0 1
1 a0 a2
CD
Vin
REQ1
By Miller effect
REQ2
B1 =
a1 a1 a3
Fig.11(b) When used as a voltage amplifier with a low impedance source.


FIGURE OF MERIT DEFINITION
Next to drive the equation:
RL =
RG
1AV ,
Vout =
Vin 1
sC
R+ 1
Gm
Ã—
Ã—
FOM =
Gm sC
IDS 2CGS
FOM: Figure of merit= AV BW
Vout=
Vin 1+sCR ,
WH =
1
CR ,
1
2 fH =
CR
Vout
A = Voltage gain =
1
Vout
V
BW = Bandwidth = fH
Vin
fL
fH= AV =
2CR ,
Vin ,
AV = gmRD
fH = Higher cut off frequency fL = Lower cut off frequency
FOM = gmRD
1
2CINR'G
At higher frequency analysis we take fH only
R'D Gm
CGD
=
C R' 2CGS
IN G
G D
Vin
ro RD
Vout
Gm
Ã—
Ã—
FOM =
Gm
R'L
CGS
IDS 2CGS
S gmVGS
Fig. 12Equivalent circuit to find the FOM

FEEDBACK BIASED CASCADED CS
AMPLIFIER
1
V V
(sC
) = g V
In Figure (9), we show the schematic of a voltage
out R'L
GS GD m GS
amplifier that has been implemented in a 90nm CMOS technology. To achieve sufficient gain, two stages were
IGD = small (so neglect it)
required due to the relatively low intrinsic gain in 90nm. The amplifier employs feedbackbiasing to allow for the
Vout
= gmV
GSRD
use of small transistor area and, hence large mismatch. This requires each stage to have different bias points. Therefore a decoupling capacitor is added between the two stages.
RD = rdRD
VGSVout
This techniques result in a very small input capacitance [5].
IGD =
= sCGD(VGSVout)
1/ sCGD
MX3a
VDD
MX3b
VDD
=sCGD[VGS+gmRLVGS]
MX1a
M2a
VBIAS VBIAS
M2b
MX1b
Vout
=sCGDVGS(1+gmRL) Ceq = CGD (1+gmRL)
By miller effect replace CGD
Vin
Cin
MX2a
Stagea
M1a
Ccoup
MX2b
Stageb
M1b
Cload
CIN = CGS + Ceq
CIN= CGS + CGD (1+gmRL)
RL occurs due to miller effect
Fig.13Schematic of a feedback biased Cascaded CS amplifier
Diodeconnected devices MX1 and MX3, which are connected in series across input device M1, form the feedback biasing resistance. Using two devices in series ensures that the voltage across them is not sufficient to turn
them both on during large voltage swings. Hence, a high resistance path is guaranteed at all voltage levels.
Device MX2 is optional in the design for the feedback biasing to work. It typically exhibits a much higher resistance, compared to the feedbackresistive path (series combination of MX1 and MX3), and forms a direct high resistance path to ground for the gate node of M1. It also acts as a voltage dependent resistance that forms a weak feedback loop that keeps M1 from entering deep into the linear region during higherthanrated input voltages. It was also observed that MX2 helped improve the linearity performance of the amplifier by compensating for the nonlinear behavior of the main feedback path. Under normal operation of the amplifier, the input resistance (at the gate of M1) is dominaed by the equivalent resistance decided by devices MX1 and MX3 [1].

SIMULATION RESULTS AND TRANSFER FUNCTION PLOTS USING PSPICE & MATLAB
There is a simulation result of transfer function given in equ.no. (11) and their relevant codes are given in AppendixI.
.AC Analysis (Gain vs Frequency plot)
Fig.14Simulated gain plots for the amplifier using PSPICE.
Gain = 15.417DB
Bandwidth = 132.56MHz.
9
8
7
6
Gain
Gain
5
4
3
2
1
Green Dots: PSPICE simulation result
Blue Line: MATLAB transfer function plot result
Figure (15) shows the comparison and agreement between PSPICE simulations results and MATLAB plot of the respective transfer function.

CONCLUSION
This paper described about the complete analysis and design of common source amplifier which is used in medical ultrasound imaging system. It gives the derivations of all the equations like, closed loop gain of negative feedback amplifier, transfer function, stability factor, FOM etc. The presented the simulation result of the CS amplifier with feedback biasing in 180nm CMOS technology using PSPICE and compared this with the MATLAB plot of the transfer function of the same.

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0
2 4 6
8 10
10 10
10 10 10
Frequency in Hz
Fig.15 PSpice Simulation and MATLAB transfer function plots for the amplifiers.