Implementation of A 4n-Bit Comparator based on IC Type 74L85 using Linear Threshold Gate Tunneling Technology

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Implementation of A 4n-Bit Comparator based on IC Type 74L85 using Linear Threshold Gate Tunneling Technology

Anup Kumar Biswas

Assistant Professor,

Department of Computer Science and Engineering Kalyani Govt. Engineering College, Kalyani, Nadia-741235, West Bengal, India

Abstract:- In this paper we will focus on the design of a 4n-bit comparator based on threshold logic functions using the specific behavior of a tunnel junction, i.e., the ability of controlling the transport of individual electron through a tunnel junction. We introduce an inverter based on single electron transistor, a novel design of an n-input linear threshold gate accommodating both positive and negative weights with 1 single tunnel junction and n+2 true capacitors, different gates like ANDs, OR, NOR and XOR. Every gates with their output waveforms are also introduced. All the time delays, their component values for different components are presented in tabular forms.

Key words: linear threshold gate, electron-tunneling, comparator

  1. INTRODUCTION

    It is clear for those who are involved in research in semiconductor technology that the ever decreasing feature size and the corresponding increase in density of transistors facilitated many improvements in semiconductor based designs. We are able to realize that such improvement will eventually come to an end. For ensuring further feature size reduction, possible successor technologies with greater scaling potential like single electron tunneling are currently under the investigation of researchers. Single electron tunneling based circuits are centered regarding tunnel junctions, through which individual electrons can be tunneled in a controlled manner.

    connected to the islands via small capacitors. For implementing a 4n-bit comparator circuit, LTG would be a best candidate for this case. Ultra-low noise is produced while tunneling an electron through the LTG based circuit. Multiple input logic gates, an XOR, are implemented, and based on them, a comparator of 4-bits is implemented and above all, with the help of this comparator a multiple of 4-bit i.e. 4n-bit comparator is presented in this paper.

  2. INVERTER

    Almost for every complex circuit, an inverter [3, 7, 8] is essential. An inverter is depicted in Fig. 1(a) which is made up of two single-electron transistors connected in series. The input voltage is directly coupled to the islands (indicating by small dots) of the SET1 and SET2 through two capacitors

    1 and 2 respectively. The island of each SET has a size smaller than 10 nm diameter of a superconductor metal like gold and their capacitances must be less than 10-17 F. The output terminal 0 is connected to the common channel in between them and to the ground via a capacitor to put down charging effects.

    In our present era, high operating speed, low power consumption, and high integration density-based devices are financially indispensable in all the sectors of engineering and technology. Single Electron tunneling based device is one such equipment by which all Boolean logic gates can be implemented. It is a single electron which is adequate to store information in the single electron tunneling based device in the atmosphere of 0K. Power being consumed in the single electron tunneling circuits is very low when compared with (CMOS) circuits. The processing speed of a threshold Logic gate (TLG) will be nearly close to the electronic speed. The single electron transistor (SET) and LTG draws the attention

    Fig.1 (a) an Inverter

    Fig.1 (b) Symbol of an Inverter

    For the inverter, the parameters values chosen are: 1

    =0,

    of researchers, scientists or technologists to design and

    =0.1× ,

    = 9,

    = 1 ,

    = 1 ,

    = 1 , =

    2

    4 10 3 2

    2 2 1

    implement large scale circuits for the sake of the consumption

    1 ,

    = 1 ,

    = 1 , = 17 and

    = 17 , R1

    of ultra-low power and their small size in different phases of 10

    1 2 2 2

    1 4

    2 4

    applications. Tunneling events for TLG-based circuits happen when only a single electron tunnel through the tunnel junction under the proper bias voltage and multiple input voltages

    =R2=100K. For simulation purpose, the value of C is taken

    1aF in this work.

    The normal operation of the inverter is described as: – the output 0 value will be high when the input voltage is low and 0 value will be low when the input voltage is high. To obtain this goal, we set the voltages 1 = 0 2 =16mV along with the tuning gate voltages both for SET1 and SET2 are applied. When is low, the SET1 goes in conduction mode and the SET2 in Coulomb blockade. This effectively connects the output to voltage and causes the output voltage to become high. Coulomb blockade interacts on the steady flow of current because whenever the high voltage (logic 1) is applied to the input, it causes to shift the induced charge on each of the islands of the two SETs by a fraction of an electron charge and keeps the SET1 in Coulomb blockade [4, 5, 11, 14, 16] and the other one (SET2) in conducting mode. As a consequence, the output shifts from high to low. The simulation result of an inverter is presented in Fig. 1(d).

    Fig. 1(c) Simulation set of Inverter (d) Simulation result

    where are being the n Boolean inputs and are their corresponding n integer weights. The LTG compares the weighted sum of the inputs 1( × ) with the threshold value . If the weighted sum value is more than or equal to the threshold or critical voltage value then the logic output of the LTG is 1, otherwise it is 0.

    =

    =

    Fig. 2 Multiple input threshold logic gate

    The tunnel junction capacitance and the output capacitance

    0 are considered to be the two fundamental circuit elements in a LTG. The input signal vector elements

    { , , , , } are weighted by their corresponding

    1 2 3

    vector element capacitances {, , , , } and added to

    In this work we assume the Boolean logic inputs

    the junction voltage,

    1 2

    . On e

    3

    n ary,

    e input signal

    corresponding to the voltages like: logic 0 =0 Volts and

    th co tr th

    vector elements { , , , , } which are weighted by

    1 2 3

    logic 1=0.1× . We assume, for simulation and other

    their respective vector capacitances {, , , , } are

    1 2 3

    19

    19

    purposes,

    C=1aF then Logic 1= 0.1× 1.602×10 =0.1 × 1.602 ×

    1×1018

    102=16.02 × 103 =16.02 16 mV.

  3. MULTIPLE INPUT THRESHOLD LOGIC GATE The multiple input threshold logic gate [1, 2, 5, 7, 8, 9] required to build gates consists of a tunnel junction, two multiple inputs connected to the points a and b. Each input voltage , for the upper side regarding the tunnel junction is

    connected to point b through the capacitance and each

    subtracted from the junction voltage, , across the junction.

    The critical voltage needed to enable tunneling action.

    acts as the intrinsic threshold of the tunnel circuit. The bias voltage connected to tunnel junction through the true capacitance, , is used to adjust the gate threshold to the desired value . When a tunneling phenomenon occurs though the tunnel junction, an electron passes through the junction from a to b in upward direction.

    input voltage

    for the lower side is conected

    point a

    We will use the following notations for the rest our discussion.

    ,

    to CP = C

    + g

    CP .. (3)

    below the tunnel junction through the capacitor . Bias

    voltage is connected to the point b through a true

    b k=1 k

    capacitor

    . Point a is grounded through a capacitor

    Cn = C0 + h

    Cn (4)

    0

    l=1 l

    as shown in Fig. 2. The capacitor of tunnel junction is . Using this capacitor based circuit and changing the suffix value of capacitors, we will be able to implement the linear threshold gate (LTG) which is the base element in constructing all gates and combinational circuits. The linear threshold gate is presented by the signum function of g(x)

    = CP + CPCn + Cn. (5)

    When we consider that all of the voltage sources ( in Fig. 2) are 0 (or connected to ground), the circuit can be thought of

    combination of three capacitors , namely CP, Cn and ,

    expressed by equations (1) and (2).

    f(x) = sgn{g(x)} = { 0, () < 0

    … (1)

    connected in series,. Here, is represented by the sum of all 2-term products of these three capacitances CP, Cn and .

    1, () 0

    =1

    =1

    g(x)=

    (

    × ) – ..(2)

    We are now interested in finding out the expression of critical voltage of the tunnel junction. Suppose that the capacitance of the tunnel junction is and the remainder of the circuit

    bearing the equivalent capacitance is , as observed from the tunnel junctions perspective, we can measure the critical voltage[7,8] for the tunnel junction as given below.

    (, ) = { + 1.5} (12)

    Threshold logic equation for OR gate

    = 0.5

    .. (6)

    Table-2

    A

    B

    F(A,B)

    t

    0

    0

    0

    0

    0

    1

    1

    >

    1

    0

    1

    >

    1

    1

    1

    + >

    A

    B

    F(A,B)

    t

    0

    0

    0

    0

    0

    1

    1

    >

    1

    0

    1

    >

    1

    1

    1

    + >

    +

    = 0.5 + (||) = 0.5

    ( ) ()

    +

    ( + )

    ( + )

    = 0.5

    ( + ) + ( ) ()

    (+)

    For positive logic we assume weights of A and B are 1 each. Then from the three equations

    .

    = 0.5

    .. (7)

    >

    (13)

    When we are able to calculate the voltage across the junction as , a tunnel event will happen through this tunnel junction if and only if the following condition is satisfied.

    || (8)

    If the junction voltage is less than the critical voltage i.e.

    || < there being no tunneling events through the tunnel junction. As a result, the tunneling circuit remains in a

    .

    Theoretically, threshold values are being integer numbers but for our purpose we can take it as real numbers, if necessary. And the threshold logic equations for two inputs AND, OR, NAND and NOR gates can be written in the following sections.

  4. THRESHOLD LOGIC EQUATION / FUNCTION (TLF) A threshold logic function (TLF) is a Boolean function that can be implemented by using a single TLG. The TLF can also be called linearly separable. An unate function is a Boolean function represented by a formula such that each variable appears either in the positive or in the negative form throughout the formula. As the equations (12), (16), (17), (18), (19), (20) and (21) have their variables either positive or negative for particular cases, so they are unate functions. Threshold logic equation for AND gate: F(A,B)=A.B

    Table-1

    A

    B

    F(A,B)

    t (threshold)

    0

    0

    0

    0

    0

    1

    0

    >

    1

    0

    0

    >

    1

    1

    1

    + >t

    > .. (9)

    > … (10)

    > ,,,,,..(14) and

    + > .(15)

    If we assume =1, =1 and t=0.5, then the three equations in 4th column in Table-2 are satisfied. Hence the Threshold logic equation for OR gate is

    (, ) = { + 0.5}(16)

    Threshold logic equation for NAND gate

    Table-3

    A

    B

    F(A,B)=

    (AB)

    t

    0

    0

    1

    0

    0

    1

    1

    1

    0

    1

    1

    1

    0

    + <

    As NAND is negative logic we assume that all the weights

    , and the threshold value are negative. If we take the values = 1, =1 and t=1.5 (2 < < 1) then the four equations in the 4th column of the table are satisfied. Hence the Threshold logic equation for NAND gate is

    (, ) = { (1.5)}

    = { + 1.5} ..(17)

    Threshold logic equation for NOR gate

    Table-4

    A

    B

    F(A,B)=

    (AB)

    t

    0

    0

    1

    0 + 0

    0

    1

    0

    <

    1

    0

    0

    <

    1

    1

    0

    + <

    As NOR is negative logic we assume that all the weights

    , and the threshold value are negative. If we take the values assume = 1, = 1 and t=-0.5 (1 < < 0)

    +

    > ….. (11)

    then the four equations in the 4th column are satisfied. Hence

    As AND is positive logic we assume all the weights ,

    and the threshold value are positive.

    If we assume =1, =1 and t=1.5, then all the equations from (9) to (11) are satisfied.

    So we can write

    g(x)= =1( × ) –

    g(A,B)={A. + . } and the Threshold logic equation for AND gate is

    the Threshold logic equation for NOR gate is

    (, ) = {1 1 (0.5)}

    ={ + 0.5} (18)

    Threshold logic equation for 3-input AND gate

    Table-5

  5. THRESHOLD GATE-BASED IMPLEMENTATION

    The threshold gate-based implementations of the Boolean Logic gates have the same basic circuit topology and we will draw and explain them in the subsequent sections. The threshold gate is built up of a bias capacitance , a tunnel junction capacitance , and an output capacitance 0 . The two input AND and OR gates contain two input true capacitors. Fr both the and gates, the two input

    capacitors we are taking are CP = CP = 0.5 for positively

    A

    B

    C

    F(A,B,C)

    t

    0

    0

    0

    0

    0

    0

    0

    1

    0

    >

    0

    1

    0

    0

    >

    0

    1

    1

    0

    > +

    1

    0

    0

    0

    >

    1

    0

    1

    0

    > +

    1

    1

    0

    0

    > +

    1

    1

    1

    1

    + +

    A

    B

    C

    F(A,B,C)

    t

    0

    0

    0

    0

    0

    0

    0

    1

    0

    >

    0

    1

    0

    0

    >

    0

    1

    1

    0

    > +

    1

    0

    0

    0

    >

    1

    0

    1

    0

    > +

    1

    1

    0

    0

    > +

    1

    1

    1

    1

    + +

    weighted inputs. Whereas, for

    1

    the

    2

    NAND

    and NOR gates, two

    capacitors hold the values as Cn = Cn = 0.5 for negatively

    As AND gate is a positive logic we shall assume that all the values of , , and are positive. If we take

    = 1, = 1, =1 and = 2.5 ( or any value in the range

    2 < < 3), then all the inequality equations from are

    satisfied.

    So the Threshold logic equation for 3-input AND gate is

    (, , ) = { + + 2.5}(19)

    Threshold logic equation for 4-input AND Gate

    Similarly, for 4-input AND gate threshold logic equation will be

    (, , ) = { + + + 0.5} (20)

    Threshold logic equation for 4-input OR Gate

    Table-6

    A

    B

    C

    D

    F(A,B,C,D)

    t

    0

    0

    0

    0

    0

    0

    0

    0

    0

    1

    1

    0

    0

    1

    0

    1

    0

    0

    1

    1

    1

    +

    0

    1

    0

    0

    1

    0

    1

    0

    1

    1

    +

    0

    1

    1

    0

    1

    +

    0

    1

    1

    1

    1

    + +

    1

    0

    0

    0

    1

    1

    0

    0

    1

    1

    +

    1

    0

    1

    0

    1

    +

    1

    0

    1

    1

    1

    + +

    1

    1

    0

    0

    1

    +

    1

    1

    0

    1

    1

    + +

    1

    1

    1

    0

    1

    + +

    1

    1

    1

    1

    1

    + +

    +

    As OR gate is a positive logic we shall assume that all the values of , , and are positive. If we take = 1, = 1 , =1 , =1 and = 0.5 ( or any value in the range 0 < < 1), then all the equations in column 5 of Table- 6 are satisfied.

    So the threshold logic equation for 4-input OR gate is

    (, , , )

    1 2

    weighted inputs.

    Every threshold gates is augmented with an inverter (Fig.1 (a) or 1(c)). The function of the inverter is to invert/buffer the output of a threshold gate. The logic function done by the buffered threshold gate is that the inverse of which is done by the threshold gate itself. For instance, a buffered gate implements the function. For the remaining part of our discussion, when we refer to a logic function such as AND or OR, we imply the logic function performed by the entire gate (i.e., threshold gate plus an output buffer).

    The parameters used for the implementations and simulations of different gates like AND, OR, NAND and NOR gates and other combinational or sequential circuits are given in Table- 7 [6, 7].

    Table-7

    TLG

    2-

    input AND

    2-

    input OR

    2-

    input NAND

    2-

    input NOR

    3-

    input OR

    Cb

    10.6C

    11.7C

    13.2C

    11.7C

    11.8C

    C0

    8C

    8C

    9C

    9C

    7.8C

    CP

    1

    0.5C

    0.5C

    0.4C

    Cp

    2

    0.5C

    0.5C

    Cn

    1

    0.5C

    0.5C

    0.5C

    Cn

    2

    0.5C

    0.5C

    0.1C

    0.1C

    0.1C

    0.1C

    0.1C

    Cg1

    = Cg2

    0.5C

    0.5C

    0.5C

    0.5C

    0.5C

    C2

    = C3

    0.1C

    0.1C

    0.1C

    0.1C

    0.1C

    C2

    = C3

    0.5C

    0.5C

    0.5C

    0.5C

    0.5C

    C1

    = C4

    4.25C

    4.25C

    4.25C

    4.25C

    4.25C

    CL

    9C

    9C

    9C

    9C

    9C

    0 = 0 , 1 = 16 , =105,

    =0.1aF, other capacitance values are in terms of

    , where = 1

  6. AND GATE

    For implementing the AND gate we will use the parameters

    3=10.6C , = =0.5aF, = = 4.25,

    1 2

    1 = 2 = 0.5, = 9, 0 = 8, =105

    in Fig. 4(a) and accordingly after running the

    simulator the output we get is given in Fig. 4(b).

    Fig.3 (a) AND Gate (b) Simulation result of AND gate

  7. NAND GATE

    For implementing the NAND gate, we will use the

    parameters = =0.5aF, = = 4.25,

    Fig.5(b) Simulation result of 3-input AND gate

    1 2

    1 = 2 = 0.5, = 3 = 13.2, = 9, 0 = 8, =105 in Fig. 5(a) and accordingly after running the simulator the output we get is given in Fig.4(b).

    Fig.4 (a) NAND Gate

    Fig.4 (b) Simulation result of NAND gate

  8. 3-INPUT AND GATE

    For implementing the 3-input AND gate we will use the parameters 3=10.6C , = =0.5aF, = =

  9. FIG. 4-INPUT AND GATE

    1

    1

    2

    2

    When we are implementing a 4-input AND gate we will use the parameters 3=10.6C , = =0.5aF, =

    = 4.25, 1 = 2 = 0.5, =

    9, 0 = 8, =105 in Fig. 6(a) and accordingly after running the simulator the output we get is given in Fig. 6(b).

    FIG. 6(A) 4-INPUT AND GATE

    1 2

    4.25, 1 = 2 = 0.5, = 9, 0 = 8, = 105 in Fig. 5(a) and accordingly after running the simulator the output we get is given in Fig. 5(b).

    Fig.6(b) Simulation result of 4-input AND gate

    Fig. 5(a) 3-input AND gate

  10. OR GATE

For implementing the AND gate we will use the parameters

= =0.5aF,3 = 11.7, = = =

12. 4-INPUT OR GATE

Combining the three 2-input OR gate, a 4-input OR gate is built To implementing this gate we will use the parameters

1 2

4.25,

=

= 0.5,

= 9, =

= =0.5aF,3 = 11.7, = = =

1

2

0 1 2

8, = 105 , = 16 and accordingly after running the simulator the output we get is given in Fig. 7(b).

Fig. 7(a) OR gate

Fig. 7(b) simulation result of OR gate

  1. 3-INPUT OR GATE

    For implementing the 3-input AND gate we will use the

    parameters = =0.5aF,3 = 11.7, =

    4.25, 1 = 2 = 0.5, = 9, 0 = 8, = 105 , = 16 and accordingly after running the simulator the output we get is given in Fig. 9(b).

    Fig. 9(a) 4-input OR gate

    1 2

    = = 4.25, 1 = 2 = 0.5, = 9, 0 = 8, = 105 , = 16 and accordingly after running the simulator the output we get is given in Fig. 8(b).

    Fig. 8 3-input OR gate

    Fig.9 (b) Simulation result of 4-input OR gate

    1. NOR GATE

      For implementing the NOR gate we will use the parameters

      = =0.5aF,3 = 11.7, = = =

      1 2

      Fig.8 (b) Simulation result of 3-input OR gate

      4.25, 1 = 2 = 0.5, = 9, 0 = 9, = 105 , = 16 and accordingly after running the simulator the output we get is given in Fig. 10(b).

      Fig. 10(a) NOR gate

      Fig.10 (b) Simulation result of NOR gate

    2. EXCLUSIVE OR (XOR) GATE

      For implementing the XOR gate we will use the parameters

      = =CP = CP = = 0.5aF, 3 =

      xi= AiBi + AiBi i = 0, 1, 2, 3 .(23)

      where xi=1 only if the pair of bits in position i are equal, i.e., if both are 1s or bothare0's.

      The equality of the two n umbers, A and B, is displayed in a combinational circuit by an output binary variable which we designa te by the symbol (A = B) shown in Fig. 12(a)[given in a separate page extra page due to its large size ]. This binary varia ble is equal to 1 if the input numbers, A and B, are equal, and it is equal to 0 if they are not equal. If the equality condition exist, t h e n all xi variables must be equal to 1. This indicates an AND operation [20] of all variables:

      (A=B)= x3 x2 x1 x0 (24)

      the binary variable (A = B ) is equal to 1 if and only if all pairs of digits of the two numbers are equal.

      When we want to examine whether A is greater than or less than B, we investigate the relative magnitudes of the pairs of corresponding bits commencing from the most significant bit position. If the two bits are equal, we compare the next lower significant pair of bits. This comparison continues un til a pair of unequal bits is faced. If the corresponding bit of A is 1 and that of B is 0, we conclude that A >B. If the corresponding bit of A is 0 and that of B is 1, we decide that A<B. T h e

      1 2 1 2

      11.7, = = = 4.25, 1 = 2 =

      0.5, = 9, 0 = 8, = 0.1aF, = 105 , = 16 and accordingly after running the simulator the output we get is given in Fig. 11(b).

      Fig. 11(a) XOR gate

      Fig. 11(b) simulation result of XOR gate

    3. DESIGN OF A 4-BIT COMPARATOR

      Here we consider two binary numbers A and B of bit lengths 4 which are given as follows:

      A = A3A2A1A0 }(22)

      B = B3B2B1B0

      where each suffixed letter represents one of the digits in the number. Both the two numbers are equal if all pairs of

      corresponding bits are equal i.e., if A3=B3, A2=B2 and A1=B1 and A0=B0 . As the numbers are binary, the bits are either 1 or 0 and the equality relation of each pair of bits can be expressed logically by an equivalence f unction given in equation (23):

      sequential comparison can be expressed logically by the f ollowing two Boolean f unctions (25) and (26) as follows. (A > B) = A3B3+ x3A2B2 + x3 x2A1B1 + x3 x2 x1A0B0

      ….(25)

      (A < B) = A3B3+ x3A2B2 + x3 x2A1B1 + x3 x2 x1A0B0

      (26)

      The symbols ( A > B ) and ( A < B ) are binary output variables which are equal to 1 when (A > B) a n d (A < B) respectively. The circuit drawn in the blue box in Fig. 12(b) with the assistance of the equations (24), (25) and (26).

      [Note: Fig. 12(a) A 4-bit Comparator based on LTG representing IC type 74L85 is given in the last separate page due to its large size.]

      Fig. 12 (b) circuit representing Fig. 12 (a)

      Fig. 12 (c) chip form of Fig. 13(a) (called 74L85)

    4. DESCRIPTION OF 74L85 COMPARATOR

      We have elaborately tried to implement the circuit of a 4-bit comparator of IC type 74L85 and which is depicted in Fig. 12(a). The Fig. 12(a) is pictorially represented by Fig. 12 (b). The IC type 74L85 is functionally implemented with the help of this Fig. 12 (b).

      When we are interested in making the chip executable, first work is to provide power supply. As we know, the circuits like adder, multiplier start executing from LSB, on the contrary a comparator comparing more than 2-bits data commence comparing from the MSB and goes towards LSB. We take two data A and B having the same word length. The data values of A and B may be different or the same, whatever may be, the comparator will provide the decision like a signum function. For the case of an IC 74L85, the data inputs will be of two parts with 4-bits each and the output will be of 3-bits. In the input side data can be any binary numbers of four bits whereas in the output will be of only one bit and other two bits will be of . All the three bits are expressing the output depending upon the inputs.

    5. 4-bit Comparator

      A Comparator is a combinational circuit which compares two binary numbers for comparing whether one binary number is equal to, less than or greater than the other number. We logically design a circuit which is having two input data A and B of 4 bits each, and three output terminals, one for (A > B) condition, one for( A = B) condition and one for (A < B) condition.

      When we are considering four bit comparison, the only Fig. 13(a) is sufficient to manipulate the data in the input side to provide output. In this case the three cascading input terminals indicated by input(A<B), input(A>B) and input(A=B) are kept in dont care condition, the only exception is that when the comparing data all are equal, we set input(A<B)=L, nput(A>B)=L and input(A=B)=H. The input-output relationship is shown in Table-1. The marks × in the Table- 8 indicate dont care.

      Before Cascading: When we are interested in what happens if we take the all possible inputs for cascading inputs i.e., for input(A<B), input(A>B) and input(A=B).The input-output combinations we get from Fig. 12(a) /Fig.12(c) is written in Table-9. From the Table-9, we observe that when the comparing input data A and B are equal, the outputs (in the red colour box) are not acceptable, because at the same time two or three output levels cant be HIGH or three output levels cant be LOW for a comparator. Only one output level will be HIGH and other two will be LOW for a comparator. As the comparator output condition levels are violating for the cases indicating by the red color box in Table-9, so all the cascading inputs in the red color box will not be taken in consideration. So the modified table to be accepted when two or more 4-bit comparators are in cascaded connection is given in Table-10.

      Fig. 13 8-bit comparator

    6. 8-BIT COMPARATOR

      After Cascaded connection: Two 8-bit numbers compared by cascading two 4-bit comparators U1 and U2 is shown in Fig.13. The output of the lower order comparator (U1) [ i.e, when inputs A = (A3, A2, A1, A0) and B=(B3, B2, B1, B0)]

      at terminals 5(O A=B), 6(O A>B), and 7(O A<B) are connected respectively to the corresponding cascading inputs of the higher-order comparator (U2). In the lower order comparator (U1), the A=B cascading input (terminal 4) must be connected to HIGH level input. And the other two cascading inputs A>B (terminal 3) and A< B (terminal 2) must be connected to LOW. The outputs of the higher-order comparator (U2) will be the outputs of the 8-bit comparator. If anybody is interested in making a circuit for comparing more than 8-bits then he/she can connect the circuit like Fig.14 for comparing 4×n bits, where n=3,4,5 . So he /she can use a 4n-bit comparators.

      Fig. 14 a 4n-bit Comparator

    7. DISCUSSION

      Now we are interested in determining the processing delay of any two-/three-/four-input logic gates, combinational and sequential circuits based on the LTG gates. To find out the delay of a logic gate we have to take the consideration of involving critical voltage given in equations (6) and (7), as well as the tunnel junction capacitance . However, assuming at T = 0K, the switching/processing delay of a logic gate can be calculated by using the approach [1,7, 8, 9].

      delay=(|ln ( )|) / ( || ) ..(21)

      where is the junction voltage and is the critical (threshold) voltage

      The slowest switching happens whenever the tunnel junction voltage has the value greater than the critical voltage , i.e.,

      | | > , but very close to it. This must happen, for instance, for the case of a 2-input NOR gate, when only 1 is logic 1, resulting =11.8mV, the critical voltage of the tunnel junction voltage is 11.58mV. We consider that the probability of error change =1012 and the junction resistance = 105. We obtain a gate delay equal to 0.07281|ln ( )|ns = 1.675 ns. In the same manner, we are capable of calculating the circuit delays and they are tabulated in Table-11.

      When an electron passes through the tunnel junction, the amount of total energy in the circuit changes after the tunneling. So the difference between the energies before and after the tunneling event is calculated by the equation (22) =

      = ( ||)..(22)

      and this is the amount of switching energy consumed while a tunneling event occurs in the tunneling circuit.

      Here we have drawn the curves of the switching delay as a function of the switching error probability in Fig. 15(a) and the switching delay as a function of the unit capacitance C which is drawn in Fig. 15(b).

      Fig. 15(a) Delay vs. Error Probability

      Fig. 15 (b) Delay Vs. capacitance

      We have also found out the area/element numbers for all gates, their switching delay, and switching energy consumptions for the corresponding individual linear threshold gates (using the same methodology as accepted for the Boolean gates). The switching energy vs. elements diagram regarding our present LTG based circuits is shown in Fig. 16.

      Fig. 16. Switching energy vs. elements

      From the Table-11 we observe that the time delay for the 4- bit comparator as well as IC Type 74L85 is 0.528|ln( ) | ns , for 8-bit comparator time costs for processing is 1.056|ln( ) | ns and in general for a 4n-bit comparator the processing delay will be 0.528n|ln( ) | ns. In this case time delay is directly proportional to number of 4-bit comparators or IC Type 74L85.

      Given that the value of equals to 1016, so the time delay for a 8-bit comparator to provide the first decision about the two 8-bit input data being compared is 19.45ns. Therefore

    8. SWITCHING DELAYS OF LTG AND SET

      The time delay or the processing delay for a CMOS logic gate like NAND, NOR, XOR is 12ns [20], whereas the time required for tunneling through a single electron transistor (SET) is approximately close to 4ns [4, 5, 16, 18]. The XOR gate using conventional logic circuits needs 16 transistors, whereas the same function can be implemented with the help of just one SET [3, 5, 6, 11] i.e. number of nodes can be reduced to 1 instead of 16.

      Assuming that that error probability is 1016 then the delay for the 2-input OR gate will be 2.28ns and similarly the other delays for the other gates used in implementing the IC chip 74L85 can be calculated and are all shown in Table-12. It is transparent that the LTG based circuit is faster than the SET based circuit when =1016. The comparison of delays for SET and LTG gate based circuits is drawn by a bar

      diagram in Fig.16.

      the fan-out rate is = 1

      19.45ns

      51.413881GHz.

      Fig.16 Delay comparison of SET and LTG

    9. CONCLUSION

      We discussed a novel design of threshold logic gates implemented in single electron transistor technology, where the basic operating principle is single electron transport phenomenon. A generic Linear Threshold Logic Gate implementation is elaborately discussed and from which we

      have obtained a family of logic gates like AND, NAND, OR. We have also derived the threshold logic equations for different logic gates. All the 2-input logic gates along with 3- input AND gate and 4-input AND/OR gates have been implemented and are verified by means of simulation using SIMON. The number of elements like true capacitors, junction capacitor for logic gates, their delays, power consumed by them are shown in a tabular form and their related curves or bar diagram are produced in due places. With the help of the different logic gates we have implemented a 4-bit comparator and by this single comparator unit we have been able to build 8-bit or 4n-bit comparator. In single electron tunneling technology, we observe that the threshold logic gates are at least 3 times faster than CMOS based logic gates. The operating temperature is kept very close to 0K in real operation. At last we find that the implemented comparator providing the fan-out is the order of O(109).

    10. REFERENCES

  1. Anup Kumar Biswas,State Transition Diagram for A Pipeline Unit based on Single Electron Tunneling.International Journal of Engineering Research & Technology (IJERT) Vol. 10 Issue 04,

    April-2021

  2. Anup Kumar Biswas, Design of A Pipeline for A Fixed-Point Multiplication using Single Electron Tunneling Technology, International Journal of Engineering Research & Technology (IJERT), Vol. 10 Issue 04, April-2021 pp. 86-98

  3. Souvik Sarkar1, Anup Kumar Biswas2, Ankush Ghosp, Subir Kumar Sarkar1 Single electron based binary multipliers with overflow detection, International Journal of Engineering, Science and Technology Vol. 1,No. 1, 2009, pp. 61-73

  4. A. K. Biswas and S. K. Sarkar: An arithmetic logic unit of a computer based on single electron transport system: Semiconductor Physics, Quantum Electronics & Opt-Electronics. 2003. Vol 6. No.1, pp 91-96

  5. A.K. Biswas and S. K. Sarkar: Error Detection and Debugging on Information in Communication System Using Single Electron Circuit Based Binary Decision Diagram. Semiconductor Physics Quantum electronics and opt electronics, Vol. 6, pp.1-8, 2003

  6. Alexander N. Korotkov, Single-electron logic and memory devices

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BIOGRAPHY

Anup Kumar Biswas is an Assistant Professor in the Department of Commuter Science and Engineering in Kalyani Govt. Engineering College. He is awarded his PhD[Engg.] degree in the stream of Electronics and Telecommunication Engineering from Jadavpur University in the year 2006. He has engaged in teaching and research activities since the last

16 years. His Specialization field is nanotechnology especially single electron tunneling technology. Dr. Biswas has published several papers in various national, international conferences and journals.

Fig. 12(a) A 4-bit Comparator based on LTG representing IC type 74L85

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