High K Oxides as an Alternative Gate Oxide in CMOS Technology and Its Corresponding Effects – Survey Approach

DOI : 10.17577/IJERTV2IS110167

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High K Oxides as an Alternative Gate Oxide in CMOS Technology and Its Corresponding Effects – Survey Approach

1Alekhya Duba, 2Vidhi Jaggi, 3Mr. Abhishek Verma, 4 Dr. Anup Mishra

1,2B.E Scholar, 3Assistant Professor, 4Professor

Bhilai Institute of Technology, Durg (C.G.)


Recent years have seen myriads of drastic transformations in the field of metal oxide semiconductors. Beginning from using oxy- nitride in 2001 as a gate oxide to SiO2 in 2007, gate oxides has been a topic of constant research. However the present focus is to reduce the leakage current which is amplified due to constant scaling of the device. Reduction of the leakage current can be done by replacing SiO2 with a physically thicker layer of metal oxides with a higher relative permittivity (K) such as HfO2, Al2O3 and La2O3. These oxides are inferior to SiO2 in properties such as they have a high defect density and their inability to remain in amorphous form. This review covers the choice of high-K oxides, requisites of a material to serve a better gate oxide than SiO2, mobility and leakage current of the present materials under consideration.

Keywords High K oxides, CMOS scaling, Leakage current, Mobility.

  1. Introduction

    In advancement of integrated circuit technology, scaling of gate dielectric thickness to reduce size of MOSFETs is a big challenge. MOSFET has been continually scaled down in size to increase drive current, for higher switching speed and to have more number of transistors on a single chip. The rate of scaling viz. doubling of the number of transistors integrated per unit area after every 18 months was an observation of Gordon E Moore. The minimum feature size in a transistor has decreased exponentially with year. The semiconductor Roadmap defines how each design parameter will scale in future years to continue this, as shown in Figure 1 and Table 1.

    Aggressive scaling of CMOS technology in recent years has reduced the silicon dioxide (SiO2) gate

    dielectric thickness to few nm. However the scaling cannot go forever, and there is a limit to Moores law. Major cause for further reduction of the SiO2 thickness is increased gate leakage current. The thickness of the SiO2 layer presently used as the gate dielectric is becoming so thin that the gate leakage current due to direct tunnelling of electrons through the SiO2 will be so high that the circuit power dissipation will increase to unacceptable values. Variation of leakage current with reduced thickness of SiO2 is shown in figure 2.

    Fig 1 :Scaling of feature size, gate length and oxide thickness according to 2003 Semiconductor Roadmap[1]

    Fig 2: Scaling trend of MOSFET gate dielectric thickness [2].

    Table 1. Summary of 2003 Roadmap. Node, gate length, equivalent oxide thickness of high power(CPU) and low standby power devices(mobile), gate oxide material [1].



















    ASIC 1/2 Pitch









    Physical gate length









    Tox high power









    Tox low power








    Gate oxide


    HfOx ; Si,N


    Gate metal

    poly Si

    metal gate, e.g. TaSiNx

    Tunnelling currents decreases exponentially with increasing distance.FET is a capacitance-operated device, where the source-drain current of the FET depends on the gate capacitance, given by:

    C=0 KA/t (1)

    Where, 0 is the permittivity of free space, K is the relative permittivity, A is the area and t is the SiO2 thickness. Hence, the solution to the tunnelling problem is to replace SiO2 with a physically thicker layer of a new material of higher dielectric constant K. This will keep the same capacitance, but will decrease the tunnelling current. These new gate oxides are called high K oxides. The thickness of a high-K film ,in order to achieve the same capacitance as SiO2 film of thickness tox can be written as [1]:

    teq = Tox(high K/ox) (2)

    This implies that the thickness of a film with a dielectric constant higher than that of SiO2 can be kept higher, thus achieving a reduction in gate leakage current. There are some problems identified for the use of high-K oxides. These are

    1. the ability to continue scaling to lower EOTs,

    2. the loss of carrier mobility in the Si when using high K oxides,

    3. the shifts of the gate voltage threshold, and nally

    4. the instabilities caused by the high concentration of electronic defects in the oxides.

  2. Effects of Scaling:

    Aggressive scaling of CMOS technology in recent years has reduced the silicon dioxide (SiO2) layer used as dielectric becoming too thin (<1.4nm).Major causes for concern in further reduction of the SiO2 thickness include increased poly-silicon (poly-Si) gate depletion, gate dopant penetration into the channel region, and high direct-tunnelling gate-leakage current, exceeding 1A/cm2 at 1V.

    This leakage arises from quantum effects. At 1.4 nm, the quantum nature of particles starts to play a dominant role. At such thickness, electron behaves more like a wave, defining the probability of finding the electron in a particular location. This wave extends all the way to the other side of the dielectric, increasing the probability of electron to appear on channel side having tunnelled through the energy barrier.

    The leakage current can be given by the following equation [3]:


    Where W and L are the effective transistor width and length respectively,

    A = q3/162hox,

    B = (ox)3/2/3hq,

    mox is the effective mass of the tunnelling particle, ox is the tunnelling barrier height,

    tox is the oxide thickness,

    h is 1/2 times Plancks constant and q is the electron charge.

    Fig 3: Leakage current vs. voltage for various thicknesses.[1]

    Fig 4: Schematic of direct tunnelling through a SiO2 layer and the more difficult tunnelling through a thicker layer of high K oxide. [1]

    This increased leakage current results in increased leakage power dissipation, which dominates the total chip power consumption as technology advances to nano scale. Most of the battery operated applications such as cell phones, Laptops etc requires a longer battery life, which can be made possible by controlling leakage current flowing through the CMOS gate.

    Fig 5: Variation in gate current density with thickness of oxide [2].

    Presently a processor chip contains about 100 million transistors and each gives high leakage current wich leads to heating effect. The advantage of scaling without increase in leakage current can be achieved by use of high K oxides as an alternative of SiO2. The thickness of a high K film in order to achieve the same capacitance as an SiO2 film of thickness tox can be written as

    teq = tox (high-k/ox) (4)

    From the above equation we can infer that by using high K oxide material instead of SiO2 for insulation we can increase the thickness of the film, and can effectively reduce leakage current. Some of the high K elements investigated are silicon nitride (Si3N4) or oxynitride (SiOxNy) ,zirconium oxide (ZrO2),hafnium oxide (HfO2 ) ,aluminium oxide (Al2O3),and lanthanum oxide (La2O3).Variation of gate voltage and leakage current density with different oxides are as shown in figure 6.

    Fig 6:Variation of parameters with a) Si3N4 b)HfO2 c)Al2O3 d)La2O3.[2]

    By replacement of SiO2 with high-K oxides, scaling can be done without sacrificing performance.

  3. Choice of High K Oxides

    Since it becomes necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (K), there are various oxides under consideration for this purpose such as hafnium oxide (HfO2), hafnium silicate, zirconium oxide (ZrO2),SrO,CaO,Ta2O5,TiO2,BaO,Al2O3,Y2O3,La2O3,

    and various lanthanides and it was found that in many

    respects they have inferior electronic properties than SiO2, such as a tendency to crystallize and a high concentration of electronic defects. New high quality electronic materials developed from these oxides are on the way of extensive research.

    There are also some problems associated with high K such as increased threshold voltage and decreased

    mobility. These problems can be solved by replacing poly Si gates with doped metal gates which improves mobility.

    The key reason for using Si in microelectronics technology is that SiO2 is an excellent insulator. SiO2 can be made from Si by thermal oxidation where as other semiconductor such as Ge, GaAs, GaN, SiC etc has a poor native oxide. The only problem of SiO2 is that, when very thin, it is possible to tunnel across it. Hence we must start to use a new oxide of high K which we can choose from large part of periodic table.

    The requirements of a new oxide to replace SiO2 are as follows:

    1. The metal oxide must have a permittivity higher than Si, industry targets values nearly between 15 to 20.

    2. Aiming towards less leakage of current, the material should allow less leakage current.

    3. Density of defects must be less

    4. The oxide is in constant contact with Si and hence must be thermodynamically stable with it. [1]

    5. High breakdown field and low loss factor .

        1. K Value

          The first requirement for the candidate oxide is that K should be over 10, preferably 25-30.From the table and figure it can be seen that the value of K vary inversely with the band gap. So we must accept a relatively low K value. There are oxides with very large K values such as SrTiO3 but this has low band gap i.e 3.2eV. In fact we cannot use a huge K oxide in CMOS design because they cause undesirably strong fringing fields at source and drain electrode.

        2. Thermodynamic Stability

          The second requirement for oxide material is that it must not react with Si to form either SiO2 or a silicide

          .This is because the EOT will increase due to resulting

          SiO2 layer and the effect of using the new oxide will be negative. Also if silicide is formed then it would generally be metallic and would short out the field effect.

          Table 2: Different oxides with their parameters.[4]


          Dielectric Constant (Bulk)


          Conduction offset(eV)

          Silicon dioxide (SiO2)




          Silicon nitride (Si3N4)




          Aluminium Oxide (Al2O3)



          Tantulum pentoxide (Ta2O5)




          Lanthana (La2O3)




          Yttrium oxide (Y2O3)




          Hafnia (HfO2)




          Zirconia (ZrO2)




          This condition requires that the oxide used in place of SiO2 should have high heat of formation than SiO2.This restricts the possible oxides to very few, from columns II,III,AND IV of the periodic table. Some of these are SrO, CaO, BaO, Al2O3 ,ZrO2, HfO2,Y2O3 ,La2O3, and

          lanthanides. The group II oxides SrO etc are not favourable for use because they are reactive with water but they can be accepted as a transition layer. Hence we are now available with oxides like Al2O3,ZrO2,HfO2,Y2O3,La2O3, and various lanthanides. Zr and Hf belongs to group IV .It is also a fact that thermodynamic data for many oxides was not so

          accurate .HfO2 is presently preferred high K oxide over ZrO2 because it was found that ZrO2 is slightly unstable and react with Si to form silicide,ZrSi2.HfO2 in conjunction with metal gates improves leakage current, gate capacitance and speed. By replacing SiO2 with HfO2,transistors will be able to continue to shrink without sacrificing performance.

          La2O3 has slightly higher K value than HfO2 but it is more hygroscopic. Y2O3 also has lower K than La2O3. Al2O3 also has disadvantage of lower K value.

        3. Kinetic Stability

          The third condition to choose the oxide is that it should be compatible with existing process conditions. Suppose we choose an amorphous oxide, this requires that the oxide remain amorphous when annealed to upto 1000oC for 5 seconds. In this condition, SiO2 is best as it is an excellent glass former but other high K oxides are not.Al2O3 is a reasonably good glass former and considered to be the next best in this respect.Ta2O5 is moderately good glass former but it cannot be used because it is reactive. Many other oxides crystallize well below 1000oC.

          This problem can be avoided upto great extent by alloying the desired oxides with glass former SiO2 or Al2O3 which gives either a silicate or aluminate. This then retains the stability against crystallisation to close to 1000oC.Under this condition, aluminates would be preferable to silicates as they have higher K value. Hf silicates can just pass this criterion as addition of some nitrogen is found to raise the crystallisation temperature.

          The use of nano-crystalline oxides is found to be poor choice because the grain boundaries would cause higher current leakage paths.

        4. Band Offset

      The high K oxide must act as an insulator. This requires that the energy gap must be over 1eV so that the conduction by the Schottky emission of electrons or holes into the oxide bands can take place as shown schematically in figure. SiO2 has gap of 9eV which forms large barriers for both electrons and holes. The

      bands of narrower band gap oxides like SrTiO3 which is only 3.3eV must be aligned almost symmetrically with respect to those of Si for both barriers to be 1eV.In practice, the valence band offset is usually larger than conduction band offset. Due to this the choice of oxide is limited to those with band gaps over 5eV.

      Various oxides such as Al2O3,ZrO2,HfO2,Y2O3,La2O3 and various lanthanides and their silicates and aluminates satisfy this criterion. The reason for this is that high heat of formation correlates with a wide band gap in ionic compounds. Al2O3 is a highly desirable gate dielectric not only because it has high band gap, but also it has a high breakdown field(5-0 MV/cm).[5]The plot for leakage current versus EOT for various high K oxides is shown in fig 7.

      Fig 7: Leakage Current vs EOT.[1]

      Lanthanides have the lowest leakage in figure and has the highest figure of merit because they have highest CB offset. However as La oxides are hygroscopic, Hf alloys are preferred.

  4. Effects of High K oxides on Mobility:

    The objective of using high K oxides in place of silicon dioxide is to create smaller, faster devices. The speed of the device follows source to drain current, which in turn depends on the carrier mobility. Carriers in FET behave like a two-dimensional electron gas. The carrier density is determined by the vertical gate field which induces them, by Poissons equation.

    The observations made by Takegi et al.[6] suggested that the mobility of electrons and holes depends only on the effective gate field and Si face,[100],[110] or [111].

    Fig.8. Carrier mobility vs. Vertical field in FETs in the universal mobility model, showing the mechanisms which limit the mobility, and their temperature dependences.[1]

    The individual components of mobility add according to Matthiessens rule,


    The mobility is limited by different mechanisms at different fields, as each obeys a different power law with field. At low fields, mobility is limited by Coulombic scattering(C) by trapped charges in the oxide, channels and gate electron interface; at moderate field it is limited by phonon scattering (PH), and at high fields by scattering by surface roughness (SR).

    CMOS devices with SiO2 gate oxide have a mobility close to 300 cm/V-s for the electric field and doping concentration used. The mobility is primarily limited by interface roughness over the range of interest. However the mobility offered by the high K oxides is well below this value. Figure 9 shows the mobility of various high K oxides. In NMOS devices this reduction is more pronounced as compared with that of PMOS, in which the reduction in mobility is fractionally less. This paper explores the cause of this lowered mobility and ways to overcome the same.

    The cause of this mobility degradation can be described by the following two effects. First, high K oxides have much more trapped charge than SiO2, these excessive amounts of trapped charges and interface states results in scattering[8]. Secondly, there is a possibility of remote scattering by low lying polar phonon modes as noted by Fischetti et al.[9]. The dielectric layer is made up of dipoles. These dipoles vibrate and lead to strong oscillations in the crystal lattice, called phonons. Oscillating dipoles interact with channel carriers when gate oscillations and phonons in high-K dielectric are in resonance. This resonance condition leads to significant degradation of channel carrier mobility and subsequently the operating speed of the device[5].

    Resonance occurs when gate carrier density is 1×1019/cm3.

    Fischetti [9] modelled the effect for various oxides and SiO2. ZrO2 and HfO2 showed more pronounced reduction. The effect is smaller in ZrSiO4 or HfSiO4 which are covalently bonding without soft modes. It is also small in Al2O3 which has no soft modes. These oxides have intrinsic effect on mobility as compared to the higher K oxides such as HfO2. However by using HfSiO4, or by including SiO2 as interfacial layer to separate the HfO2 away from channel the mobility degradation can be minimised. Both the methods are undesirable as they increase EOT.

    However this problem was soon overcome by substituting the polysilicon gate electrode with metal gate having free carrier density more than 1×1020/cm3, making it possible to dynamically screen the longitudinal soft optical phonon modes arising from

    high K dielectric materials. The influence of dipole vibrations on the channel electrons can be reduced significantly by increasing the density of electrons in the gate electrode.

    Fig.9. Carrier mobility of n-type Si, for various gate oxides, After Gusev et at.[7]

    Fig 10. Increase in channel mobility by replacing polysilicon gate with a metal gate[10].

    The mobility of the channel carriers can be further increased considerably by using a combination of tin and HfO2 as depicted in figure 11.

    Fig .11 Effective electron mobility for a) HfO2 with poly- Si b) HfO2 with Tin c) SiO2 with poly-Si.[11]

  5. Conclusion

    This paper has reviewed the choice of materials which could replace silicon dioxide. Leakage current as a result of scaling is explained and leakage current values for various thickness of SiO2 is illustrated. The cause of mobility degradation due to defects and phonon scattering is also covered. Presently, Lanthana (La2O3) is used as an oxide in the mosfet channel. Though it has higher thermal stability and a highK value, its moisture absorption capacity is large and hence is not stable with SiO2. Further research can be carried in finding methods to reduce the problem of higher absorption of moisture.

  6. References

  1. J. Robertson, High dielectric constant oxides, The European Physical Journal, Publisher, UK, 2 Dec 2004.

  2. Yee-Chia Yeo, Tsu-Jae King, Chenming Hu, MOSFET Gate Leakage Modelling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations, IEEE , Publisher, location , 4 April 2003.

  3. Taur Y, Ning TH. Fundamentals of Modern, VLSI Devices, Cambridge University Press,1998.

  4. H. Wong, H.Iwai/ Microelectronic Engineering 83(2006).

  5. P.D.Ye et al. GaAs metal-oxide-semiconductor field effect transistor with nanometer thin dielectric grown by atomic layer deposition

  6. S.I.Takagi et al., IEEE T. Electron Dev.41,2357 (1994)

  7. E.P. Gusev et al., in Tech. Digest. Int. Electron Devices Meeting 2001,p.455.

  8. R.W. Murto, M.I gardner, G.A. Brown, P.M. Zeitzoff,

    H.R. Huff, Solid State Technol. 46,43 (2003)

  9. M.V. Fischetti, D.A. Neumayer, E.A. Cartier, J. Appl. Phys. 90,4587 (2001)

  10. The High-k solution, by Mark T. Bohr, Robert S. Chau, Thir Ghanin, Kaizad Mistry. Posted in 1 oct 2007 in IEEE spectrum magazine.

  11. R.Chau, Advanced metal gate/high-k dielectric stacks for high performance CMOS transistors, in AVS 5th Int. Microelectronics Intrerfaces Conf. Santa Clara, CA,2004,pp3-5.

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