 Open Access
 Total Downloads : 474
 Authors : K.Veerraju, D.Nagesh
 Paper ID : IJERTV1IS7360
 Volume & Issue : Volume 01, Issue 07 (September 2012)
 Published (First Online): 25092012
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Fpga Implementation Of Bist With Self Feedback Logic To Achieve Complete Fault Coverage
K.Veerraju M.Tech student,
Pragathi Engineering College, Surampalem (A.P, IND).
Abstract
This paper presents an implementation of a deterministic BIST technique on FPGA that can efficiently achieve complete fault coverage without using any storage devices. A novel test structure containing a self feedback logic unit and a circular shift register is proposed and the self feedback logic unit to generate a set of seed patterns based on responses of some pre selected internal nets .This seed patterns are then used to generate all required test patterns through a circular shift register .It is notice that the self feedback logic unit requires large routing area, when internal nets connects to the self feedback logic. For the reduction of routing area we use arbitrary formulae at the internal connections.
1. Introduction
Logic BuiltIn SelfTest (BIST) has been shown to be an effective design for testability (DFT) technique in which some onchip test structure is used to test the digital circuit itself [1]. Pseudorandom testing based on linear feedback shift registers (LFSRs) is commonly used as the basis of BIST due to its simplicity and effectiveness. However a complex circuit often contains some hardtodetect faults that are randompattern resistant and thus a pseudo random test scheme usually requires long time to reach satisfactory fault coverage.
To address this problem, in literature several techniques have been proposed. The weighted random test method [1] is presented to enhance the detectability of hardtodetect faults. This technique may require long test time for a circuit containing many hardto detect faults. The mixedmode BIST technique [1] takes advantages of both pseudo random and deterministic patterns to achieve complete fault coverage in a short time. To carry out the test process, complicated control may be required to switch between different test modes, loading required seeds and/or reconfiguring some specific mapping logic.
D.Nagesh
Assitant Professor, Dept.of ECE Pragathi Engineering College, Surampalem (A.P, IND).
In alternative logic BIST methods are proposed that use simple control logic to generate only deterministic patterns without pseudorandom ones. In twistedring counters (TRC) along with some reseeding logic are employed to generate the required patterns. Simple finite state diagram based control is used to load seed patterns to the TRC and to perform the TRC operations to generate additional patterns. The required seed patterns can be stored in an onchip ROM or provided by an external tester. A large number of patterns are generated from a seed pattern so as to reduce the number of required seeds. Though the control is simple, this technique may require long test time to achieve 100% fault coverage if the length of the TRC is large. In [5] a hybrid BIST using partially rotational scan is proposed in which a scan chain is divided into multiple segments, each of which can independently perform rotation operations. The required patterns for complete fault coverage are generated based on a given set of seeds that can be shifted to the scan chain by an external tester and then rotated within each segment. Since only shifting and rotation operations are required, the test control is also simple. However it may still require long test time if a large number of shifting and rotation operations have to be performed.
Some techniques use circuit responses to generate the required deterministic patterns. The circular self test scheme replaces each primary IO with a special BIST cell and connects them together with the internal scan cells to form a long circular selftest path. Both pattern generation and signature analysis can be done by the selftest path, and thus only small area overhead is needed. However the fault coverage may be degraded if some states required to detect some faults cannot be reached by the selftest path. To address this issue a jumping logic that can change the contents of the scan register to any state is proposed, by which all the desired patterns can be generated efficiently. Authors propose to connect some internal nets of the circuit under test (CUT) to its inputs so as to provide the required logic values of the next pattern directly. By exploring the relation between the responses of internal nets and a precomputed test set, this method aims to generate a series of deterministic patterns that contain
compatible with the precomputed ones. However, since the test set is predefined, it is difficult to identify a set of connections that can generate all required patterns. To get high enough fault coverage, different sets of connections, each with a specific initial pattern, are required. Therefore the area overhead can be high. All of the above methods need either onchip ROM or external testers to provide the required seed patterns or some input patterns. In this work we propose a deterministic BIST scheme that requires no storage device. A novel selffeedback logic unit along with a circular shift register design is employed to generate the required patterns. Unlike the work in which selects patterns from a given test set and tries to identify a set of internal nets to provide the required logic values, we develop an efficient method to generate effective test patterns (seeds) based on the current circuit responses. These patterns are then used to regenerate more patterns through a circular shift register. Experimental results show that our method can achieve 100% stuckat fault coverage using much fewer test cycles than those in [2] and [5]. On average 92.27% and 88.05% test cycle reductions can be achieved compared with [2] and [5], respectively. The comparison also shows that we can use much lower area overhead and comparable test time to reach complete fault coverage. In the rest of this paper we first describe the proposed BIST architecture in Section 2. The method to generate all test patterns and to determine the associated hardware configurations is then detailed in Section 3. Section 4 provides the experimental results along with the comparisons with previous work. Finally, this paper is concluded in Section 5.
2 .The Proposed BIST Architecture
As shown in Figure 1 the proposed BIST architecture consists of a selffeedback logic unit (SFL), a circular shift register (CSR), a response monitor and an onchip BIST control unit. The SFL along with the CSR are used to generate all the required test patterns, and the response monitor is employed to capture the test responses. The whole test procedure is managed by the control unit.
In our BIST architecture all the primary inputs and scan cells of a CUT are serially connected to form the CSR. During test application an initial pattern stored in the CSR is circularly shifted (rotated) by one bit per test cycle. Thus up to n1 additional test patterns can be generated if the length of the CSR is n. However it should be pointed out that in our architecture full rotation is not always required for each initial pattern. In other words, each initial pattern can have its own
rotation number in order to reach 100% fault coverage in a shorter time. Due to this novel feature, much fewer test cycles are required than previous work [25] that uses a fixed number of shift or rotation cycles for each initial pattern or seed.
The required initial patterns for the CSR can be generated by simply resetting the CSR or through the SFL based on the current responses of some pre determined internal nets. In the latter case, some logic operations of the response bits are employed to change the state of the CSR directly. In this work unary logic operations including nooperation, inversion, shortto VDD and shorttoGND, and binary ones including and/or, and/nor and xor/xnor are considered. Throughout this paper we shall define each such a logic operation of response bit(s) as one feedback candidate. Some related definitions are also given: a set of feedback candidates that together can provide the required logic values of an initial pattern is defined as a configuration; a pattern generated by the SFL via a configuration is defined as a feedback pattern, the set containing all feedback patterns is called the feedback test set, and a pattern generated by a rotation operation based on a feedback pattern is defined as a rotation pattern. To generate all required feedback patterns we may require multiple configurations. In this work one configuration may be reused to generate multiple feedback patterns so as to reduce the area overhead.
Figure 1: proposed BIST architecture
A control unit is employed to control the switching between the selffeedback mode and the circular shifting mode as well as to control the selection of different configurations. Thus the complexity of the control unit depends on 1) the frequency of the switching between the two modes and 2) the number of configurations. Next we present an efficient method which aims to minimize both 1) and 2) described above.

Test generation and configuration determination
This section presents our method for test generation and configuration determination, which consists of two phases. In Phase 1, a set of feedback patterns are generated with full rotation consideration so as to drop as many easytodetect faults as possible. A predefined fault coverage value will be used as a criterion to determine when to stop Phase 1. If any faults are not detected after this phase, Phase 2 is executed in which a new set of feedback patterns are generated with variable rotation number consideration. The main objective of Phase 2 is to determine appropriate rotation numbers for each feedback pattern so as to minimize both test time and test control complexity. Note that in both phases each configuration will be utilized to generate multiple feedback patterns. Phase 1: Feedback Pattern Generation with Full Rotation Consideration
Figure 2: Procedure of Phase 1
Figure 2 provides the procedure of Phase 1. At first we use an allzero pattern as the initial pattern. We add this pattern to the feedback pattern set S and drop all faults detected by this pattern from the testable fault list
F. Based on this pattern, we build a special data structure called a feedback binary tree (FBT) to record the sets of current available feedback candidates that can provide the required logic0 and logic1 values for the next
feedback pattern. We will use an example shown in Figure 3 to illustrate how a FBT is constructed. Assume the CUT has 4 input pins {I1, I2, I3, I4} and 5 internal nets {N1, N 2, N 3, N4, N5}. For simplicity, in Figure 3 we directly use internal net responses as feedback candidates without performing any logic operations. After applying the allzero pattern, the FBT is built in which the root is linked to the allzero pattern and the two leaf nodes {Class0, Class1} are linked to the set of feedback candidates that provide logic0 and logic1 values, respectively. As indicated, since the responses on the nets of N4 and N5 are logic0, the Class0 node is linked to the set {N4, N5}. Similarly the Class1 node is linked
to the set {N1, N2, N3}.
Next a partiallyspecified test set (T1) is generated for all remaining faults in F. This set is used to help determine the feedback patterns to be generated in the following process. We execute a circular merge process on T1 to generate a set of compressed patterns (CS1). An example to generate one compressed pattern is shown in Figure 4, where P2 and P 3 can be generated by circularly shifting P1 for one and six cycles, respectively. Thus the three patterns can be merged into one. In our procedure each pattern in CS1 is associated with a weight which indicates the number of patterns that can be generated by this pattern through rotation operations.
Figure 3: Example of feedback pattern generation and configuration determination
Figure 4: Example of the circular merge process
We say that a pattern is compatible to the FBT if the required logic values of the pattern can be provided by the sets of feedback candidates linked to the FBT. Among those patterns in CS1 that are compatible to FBT, we select the one that has the maximum weight as the next feedback pattern. For the example in Figure 3,
assume now the pattern TP1=0011 is such a pattern. This pattern is compatible to FBT because the values of I1 and I2 of TP1 can be provided by any net in {N4, N5} and those of I3 and I4 can be provided by any net in {N1, N2, N3}. This pattern is then used as the first feedback pattern and will be applied at Cycle 2.
Once a proper pattern in CS1 is selected, the pattern is added to S and removed from CS1. Next all the faults detected by the selected pattern and its associated rotation patterns are dropped. If now all testable faults are detected, the procedure ends. Otherwise the FBT will be updated based on the current test responses. Also refer to Figure 3. After fully rotating TP1 we will enter Test Cycle 5 and the responses at this cycle will be used to update the current FBT. Since now the logic value of N4 is 0, N4 is linked to a new leaf node Class0,0, which means N4 can provide a logic0 value for generating TP 1 and a Logic0 value for the next feedback pattern. Similarly N5 and {N1, N2, N3} are linked to new leaf nodes Class0,1 and Class1,1, respectively, while no net is linked to the node Class1,0. After the updating of FBT, if the current fault coverage is equal to or greater than a predefined value (PDFC) then we will enter Phase 2 and the current FBT will be still used. Otherwise another iteration of Phase 1 will be started. In Figure 3, the second feedback pattern TP2 is selected which can be generated by connecting N5 to I1, N4 to I2, and any one net in {N1, N2, N3} to both I3 and I4.
Phase 2: Feedback Pattern Generation with Variable Rotation Number Consideration
Figure 5 presents the procedure of Phase 2. Similar to Phase 1, a partially specified test set, T2, for the remaining undetected faults is first generated. A circular merge process is then executed to compress T2. In this process we reorder patterns in T2 in order to determine the smallest rotation number for each pattern in CS2. Refer to Figure 4 again. If the patterns are reordered such that P3 is used as the initial pattern, then the other two patterns can be generated using only 3 rotation operations, comparing to the 6 rotations without pattern reordering.
To simplify test control, we next divide the patterns in CS2 into L groups such that patterns that have the same or similar rotation numbers will be tentatively put into the same group,and the maximum of the rotation numbers of all patterns in the same group will be used as the rotation number for all patterns in that group. Various tentative grouping results will be evaluated according to their resulting numbers of test cycles, and the one that leads to the fewest test cycles will be adopted.
To simplify test control, we next divide the patterns in CS2 into L groups such that patterns that have the same or similar rotation numbers will be tentatively put into the same group, and the maximum of the rotation numbers of all patterns in the same group will be used as the rotation number for all patterns in that group. Various tentative grouping results will be evaluated according to their resulting numbers of test cycles, and the one that leads to the fewest test cycles will be adopted.
We next examine the group that has the smallest rotation number and select a pattern from the group using the same selection criteria as that used in Phase 1: compatible to FBT and can generate the most patterns in T2 via rotation. Once one such pattern is identified, it is added to S and all the faults detected by the pattern and its associated rotation patterns are dropped. If now all testable faults can be detected, the procedure ends. Otherwise additional pattern(s) have to be selected. In this case if no any unselected pattern in the group can be generated using the current configuration, we start a new configuration for which the response of the last pattern of the current configuration is used as its initial pattern and a new FBT is built. Thus our method needs no storage space. On the other hand if all the patterns in the targeted group are already added to S, another group of patterns will be processed in the next iteration.

Experimental Results
Experiments using QUARTUS 12.0 targeting 100% fault coverage. We will compare the results with some related work that also employs only deterministic patterns but needs some space to store the required seed patterns or initial patterns. Quartus II software improves FPGA designer productivity by offering a complete design suite of industryleading tools and features. The design environment enables FPGAs designers to meet aggressive timetomarket goals with leadingedge synthesis and placeandroute algorithms, as well as advanced DSP design and system integration tools, and includes a broad portfolio of preverified IP cores. The development suite targets all aspects of the FPGA design process, from design entry, to timing closure to verificaAlteras Quartus II software improves FPGA designer productivity by offering a complete design suite of industryleading tools and features.
Here we use 92, 94, 96 and 98% and report the best results. In our method can completely test all circuits using only l or 2 configurations and also the number of required feedback patterns (S) is small.
In the last column of Table 1, we provide the test time in our method and the comparisons with previous work [2] and [5] which use a fixed shift/rotation cycles for each initial pattern or seed. The column RD % shows the reduction in test time. On average 99.27% and 88.05% test time reduction can be achieved by our method. compares our results with the work in which also generates patterns based on circuit responses. As indicated, in most cases our method can achieve better
(100%) fault coverage while using a smaller number of configurations. For some circuits the numbers of test cycles using our method are larger than those reported.

Conclusions
In this paper we have developed an efficient test perclock BIST technique to achieve complete fault coverage and implementing this on FPGA. No storage devices are required by this technique. We employ a selffeedback logic unit to generate a set of seed patterns based on responses of some preselected internal nets. The seed patterns are then used to generate all required test patterns through a circular shift register. An efficient method to concurrently determine the test patterns to be generated and the feedback connections is provided which results in much shorter test time or much smaller area overhead compared to previous work.
Although the number of configurations is small, we do notice that the connections from the internal nets to the selffeedback logic unit still require large routing area. We are currently investigating this problem.
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