 Open Access
 Total Downloads : 1885
 Authors : N. Subhramanyam, Ambavaram Poli Reddy, J. Rajpraveen
 Paper ID : IJERTV2IS1247
 Volume & Issue : Volume 02, Issue 01 (January 2013)
 Published (First Online): 30012013
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Fault Detection for ISCAS 89’S27 Benchmark Circuit Using Low Power LtRTPG
N. Subhramanyam, 
Ambavaram Poli Reddy, 
J. Rajpraveen 
M.TECH 
PG Scholar 
PG Scholar 
Abstract
In this project test patterns generated by the Low transition random pattern generator (LTRTPG) detect Easytodetect faults. This LTRTPGs are normally used in Built In Self Tests (BIST). This project also presents a novel lowtransition linear feedback shift register (LFSR) that is based on some new observations about the Output sequence of a conventional LFSR. The proposed design, called Bitswapping LFSR (BSLFSR), is composed of an LFSR and a 2 Ã— 1 Multiplexer. When used to generate test patterns for scanbased builtin self tests, it reduces the number of transitions that occur at the scanchain Input during scan shift operation by 50% when compared to those patterns produced by a conventional LFSR. The proposed LTRTPG can significantly reduce switching activity during BIST. These techniques have a substantial effect on average and peakpower reductions with negligible effect on fault coverage or test application time. Experimental results on ISCAS89 S27 benchmark circuits show up to 65% and 55% reductions in average and peak power, respectively.
Index Terms Builtin selftest (BIST), linear feedback shift register (LFSR), lowpower test, pseudorandom pattern generator

Introduction
The LTRTPG reduces switching activity during BIST by reducing transitions at scan inputs during scan shift operations. An example LTRTPG is shown in Fig. The LTRTPG is comprised of an r stage LFSR, a Kinput AND gate, and a toggle flip flop (T flipflop). Hence, it can be implemented with very little hardware. Each of K inputs of the AND gate is connected to either a normal or an inverting output of the LFSR stages. If large K is used, large sets of neighbouring state inputs will be assigned identical values in most test patterns, resulting in the decrease fault coverage or the increase in test
sequence length. In this project, LTRTPGs with only K=2 or 3 are used since a T flipflop holds previous values until the input of the T flipflop is assigned a 1,the same value v, where v E{0,1} , is repeatedly scanned into the scan chain until the value at the output of the AND gate. Hence, adjacent scan flip flops are assigned identical values in most test patterns and scan inputs have fewer transitions during scan shift operations. Since most switching activity during scan BIST occurs during scan shift operations. The LTRTPG can reduce heat dissipation during overall scan testing. This paper presents a new TPG, called the bitswapping linear feedback shift register (BSLFSR), that is based on a simple bit swapping technique applied to the output sequence of a conventional LFSR and designed using a conventional LFSR and a 2 Ã— 1 multiplexer. The proposed BSLFSR reduces the average and instantaneous weighted switching activity (WSA) during test operation by reducing the number of transitions in the scan input of the CUT.

Proposed approach to Design the LT RTPG:
Fig: PROPOSED LTRTPG
It has been observed that many faults that escape random patterns are highly correlated with each other and can be detected by continuously complementing values of a few inputs from a parent test vector. These observations are exploited and improve fault coverage for circuits that have large numbers of RPRFs. We have also observed that tests for faults that escape LTRTPG test sequences share many common input assignments. This implies that RPRFs that escape LTRTPG test sequences can be effectively detected by fixing selected inputs to binary values specified in deterministic test cubes for these RPRFs and applying random patterns to the rest of inputs. This technique is used in the 3weight WRBIST to achieve high fault coverage for random pattern resistant circuits. The proposed LTRTPG is as follows.
The LTRTPG reduces switching activity during BIST by reducing transitions at scan inputs during scan shift operations. An example LTRTPG is shown in Fig. The LTRTPG is comprised of an r stage LFSR, a Kinput AND gate, and a toggle flip flop (T flipflop). Hence, it can be implemented with very little hardware. Each of K inputs of the AND gate is connected to either a normal or an inverting output of the LFSR stages. If large K is used, large sets of neighbouring state inputs will be assigned identical values in most test patterns, resulting in the decrease fault coverage or the increase in test sequence length. In this project, LTRTPGs with only K=2 or 3 are used since a T flipflop holds previous values until the input of the T flipflop is assigned a 1,the same value v, where v E{0,1} , is repeatedly scanned into the scan chain until the value at the output of the AND

Bitswapping LFSR:
In recent years, the design for low power has become one of the greatest challenges in highperformance very large scale integration (VLSI) design. As a consequence, many techniques have been introduced to minimize the power consumption of new VLSI systems. However, most of these methods focus on the power consumption during normal mode operation, while test mode operation has not normally been a predominant concern. However, it has been found that the power consumed during test mode operation is often much higher than during normal mode operation. This is because most of the consumed power results from the switching activity in the nodes of the circuit under test (CUT), which is much higher during test mode than during normal mode operation.
Several techniques that have been developed to reduce the peak and average power dissipated during scanbased tests. A direct technique to reduce power consumption is by running the test at a slower frequency than that in normal mode. This technique of reducing power consumption, while easy to implement, significantly increases the test application time . Furthermore, it fails in reducing peakpower consumption since it is independent of clock frequency.
Another category of techniques used to reduce the power consumption in scanbased builtin selftests (BISTs) is by using scan chain ordering techniques. These techniques aim to reduce the averagepower consumption when scanning in test vectors and scanning out captured responses. Although these algorithms aim to reduce average power consumption, they can reduce the peak power that may occur in the CUT during the scanning cycles, but not the capture power that may result during the test cycle (i.e., between launch and capture).The design of lowtransition testpattern generators (TPGs) is one of the most common and efficient techniques for lowpower tests. This project presents a new TPG, called the bitswapping linear feedback shift register (BSLFSR), that is based on a simple bit swapping technique applied to the output sequence of a conventional LFSR and designed using a conventional LFSR and a 2 Ã— 1 multiplexer.
The introduced BSLFSR reduces the average and instantaneous weighted switching activity (WSA) during test operation by reducing the number of transitions in the scan input of the CUT.
Fig : Bitswapping LFSR
The introduced BSLFSR for testperscan BISTs is based upon some new observations concerning the number of transitions produced at the output of an LFSR.
Definition: Two cells in an nbit LFSR are considered to be adjacent if the output of one cell feeds the input of the second directly(i.e., without an intervening XOR gate).
Approach: Each cell in a maximallength nstage LFSR will produce a number of transitions equal to 2n1 after going through a sequence of 2n clock cycles.
Proof: The sequence of 1s and 0s that is followed by one bit position of a maximallength LFSR is commonly referred to as an msequence. Each bit within the LFSR will follow the same msequence with a onetimestep delay. The msequence generated by an LFSR of length n has a periodicity of 2n – 1. It is a wellknown standard property of an m sequence of length n that the total number of runs of consecutive occurrences of the same binary digit. The beginning of each run is marked by a transition between 0 and 1; therefore, the total number of transitions for each stage of the LFSR is 2n 1. This approach can be proved by using the toggle property of the XOR gates used in the feedback of the LFSR.
IMPORTANT PROPERTIES OF THE BSLFSR:
There are some important features of the BS LFSR that make it equivalent to a conventional LFSR. The most important properties of the BS LFSR are the following.

The BSLFSR generates the same number of 1s and 0s at the output of multiplexers after swapping of two adjacent cells; hence, the probabilities of having a 0 or 1 at a certain cell of the scan chain before applying the test vectors are equal. Hence,
the proposed design retains an important feature of any random TPG. Furthermore, the output of the multiplexer depends on three different cells of the LFSR, each of which contains a pseudorandom value. Hence, the expected value at the output can also be considered to be a pseudorandom value.

If the BSLFSR is used to generate test patterns for either test per clock BIST or for the primary inputs of a scanbased sequential circuit (assuming that they are directly accessible) as shown in Fig. 3, then consider the case that c1 will be swapped with c2 and c3 with c4, . . . , cn2 with cn1 according to the value of cn which is connected to the selection line of
the multiplexers (see Fig. A). In this case, we have the same exhaustive set of test vectors as would be generated by the conventional LFSR, but their order will be different and the overall transitions in the primary inputs of the CUT will be reduced by 25%.


S27 sequential circuit
Here S27 circuit is selected, which belongs to ISCAS 89 benchmark circuit family and It is a purely sequential circuit with four inputs. The circuit has been tested by using Built InSelf Test. Initially faults are inserted into the circuit, in the above circuit faults are inserted at a2,a9,a4 and a10 locations.
Fig : ISCAS 89Benchmark S27 circuit
For each and every fault pseudorandom patterns are applied corresponding test vector will be taken for four faults four test vectors are taken. These vectors are divided into two sub groups for the reduction of transitions. As number of transitions are reduced the power consumption is reduced. if output value of faulty S27,and normal S27 circuits are different then fault has been covered.

Experimental results and comparison:

simulated waveform of fault coverage for S27 circuit

simulated waveform of BitSwapping LFSR

Power analysis report of LTRTPG for S27 circuit:

Power analysis report for BitSwapping LFSR:

Synthesis report for LTRTPG:

5. Conclusion:
A lowtransition TPG that is based on some observations about transition counts at the output sequence of LFSRs has been presented. The proposed TPG is used to generate test vectors for testper scan BISTs in order to reduce the switching activity while scanning test vectors into the scan chain. The effect of the proposed design in the fault coverage, testapplication time, and hardware area overhead is negligible. Comparisons between the proposed design and other previously published methods show that the proposed design can achieve better results for most tested benchmark circuits.
Acknowledgment
N.Subhramanyam, Ambavaram poli reddy, J.Rajpraveen would like to thank the HOD, ECE Department and other Professors for extending their help & support in giving technical ideas about the paper and motivating to complete the work effectively & successfully.
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