 Open Access
 Total Downloads : 392
 Authors : Md Javeed Ahammed, M. Muzammil Parvez
 Paper ID : IJERTV3IS100349
 Volume & Issue : Volume 03, Issue 10 (October 2014)
 Published (First Online): 15102014
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Fast Performance of Parallel Adders using VLSI
Md Javeed Ahammed
Dept. of Electronics and Communication Engineering Nimra College of Engineering and Technology, Student Vijayawada, India
M. Muzammil Parvez
Dept. of Electronics and Communication Engineering Nimra College of Engineering and Technology, Assistant Professor
Vijayawada, India
Abstract In our daily life we use no of electronic devices such as calculators, computers etc. Every device needs arithmetic operations. This may create the complexity in the components. Now a days we have no of arithmetic operations which may reduce the complexity like KoggeStone, spars KoggeStone, and spanning tree adder and compares them to the simple Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). This paper presents an attractive structure of parallel adders which gives the better delay performance and area utilization. This structure and fast performance makes them particularly attractive for VLSI implementations.
Keywordsadder, koggestone adder, spars kogge stone adder, delay performance.
I INTRODUCTION
Arithmetic operations in every electronic device are major operation for the performance. Arithmetic operations such as addition, subtraction, multiplication, division, etc. addition operation are the major issue for every performance. So, no of adders have been implemented by which the complexity of the systems reduces such as area utilization, time delay. These are the main problems in each and every electronic device.
Area and Time consumed by the circuit are the basic and important requirements. Numbers can be represented in digital circuits in various ways. Hence, developing efficient adder architecture is crucial to improving the efficiency of the design. Generally ripple carry adder uses for binary addition. After the design of ripple carry adder several techniques are used for the computation of parallel adders. Carry look ahead adders are based on parallel prefix computation gives the better performance than ripple carry adder. After many years research continuous to be focused on improving the delay performance of the adder. As such, extensive research continues to be focused on improving the delay performance of the adder. Next, Brent and Kung (BK) design parallel prefix computation graph In an areaoptimal way and the koggestone (KS) architecture is optimized for
timing. This architecture is proposed based on KS and BK structures.
In this paper propose a new structure for parallel adders. Our proposed adder shows marginally faster performance than the regular koggestone adder with area saving.
II ADDERS

KoggeStone Adder
The 8bit KoggeStone adder will be explained in detail in this subsection. An 8bit KoggeStone adder is built from eight generate and propagate (GP) blocks, eight black cells (BC) blocks, eight gray cell (GC) blocks, and nine sum blocks as shown in the Figure. The details of the various blocks used in the structure of KoggeStone adder are discussed below.
GP block
The generate and propagate block takes a pair of operand bits (a, b) as inputs and computes a pair of generate and propagate signals (g, p) as output, as depicted in Figure. The output from this a block is shown in figure.
a b
GP block
(g, p)
Fig. Generate and propagate block
BC block
The black cell takes two pairs of generate and propagate signals (gi, pi) and (gj ,pj) as input and computes a pair of generate and propagate signals (g,p) as output. It is shown in Figure.
( gi, pi) ( gj,pj)
BLACK CELL
(g,p)
Fig. black cell
GC block
The gray cell takes two pairs of generate and propagate signals (gi,pi) and (gj,pj) as input and computes a pair of generate signal only. The output from this block is shown in figure.
(gi, pi) (gj, pj)
g
GRAY CELL
g
Fig. gray cell
KoggeStone adder design procedure
Step 1: First to generate propagation and generation signals for each bit.
Step 2: To generate black cell and gray cell equations.
Step 3: In each step gray cells are generated.
Step 4: By using gray cell equation to generate the carry bits directly.
Step 5: To combine propagation and carry bits for each step to generate sum.
The KoggeStone adder is a parallel prefix form Carrylook ahead adder. It generates the carry signals in (log n) time, and is widely considered the fastest adder design possible. It is the common design for highperformance adders. An example of a 8bit, 16bit KoggeStone adder structures are shown in the figures. Each vertical stage produces a "propagate" and a "generate" bits as shown. In each step radix2 gray cells are generated. By using the gray cells directly generate the carry values. The culminating generate bits (the carries) are produced in the last stage (vertically), and these bits are XOR with the initial propagate after the input to produce the sum bits. E.g., the first (leastsignificant) sum bit is calculated by XOR ing the propagate in the farthestright black box (a "1") with the carryin (a "0"), producing a "1". The second bit is calculated by XOR ing the propagate in second box from the right (a "0") with C0 (a "0"), producing a "0". It takes more area to implement than the BrentKung adder, but has a lower fanout at each stage, which increases performance. Wiring congestion is often a problem for KoggeStone adders as well.

Sparse KoggeStone Adder
Enhancements to the original implementation include increasing the radix and
sparsity of the adder. The radix of the adder refers to how many results from the previous level of computation are used to generate the next one. The original implementation uses radix2, although it's possible to create radix4 and higher. Doing so increases the power and delay of each stage, but reduces the number of required stages. While a complete adder would produce the output of all bits, this just outputs a series of carry bits at fixed intervals. These can be used as the carryin bits for a series of smaller adders. This is useful in particular for FPGAs, where small ripple carry adders can be much faster than generalpurpose logic thanks to fast connections between neighboring slices. This allows a large adder to be composed of many smaller adders by generating the intermediate carries quickly. The sparsity of the adder refers to how many carry bits are generated by the carrytree. Generating every carry bit is called sparsity1, where as generating every other is sparsity2 and every fourth is sparsity4. The resulting carries are then used as the carryin inputs for much shorter ripple carry adders or some other adder design, which generates the final sum bits. Increasing sparsity reduces the total needed computation and can reduce the amount of routing congestion. Above is an example of a KoggeStone adder with sparsity4 are shown in figure. It uses the combination of koggestone and ripple carry adder structures.
The Sparse KoggeStone adder consists of several smaller ripple carry adders (RCAs) on its lower half and a carry tree on its upper half. Thus, the Sparse KoggeStone adder terminates with RCAs. The number of carries generated is less in a Sparse KoggeStone adder compared to the regular KoggeStone adder. The functionality of the GP block, black cell and the gray cell remains exactly the same as in the regular KoggeStone adder. The schematic for a 16bit Sparse KoggeStoe adder is shown in Figure. Sparse and regular KoggeStone adders have essentially the same delay when implemented on an FPGA although the former utilizes much less resources.
Fig. Sparse KoggeStone adder
Proposed Adder
The proposed adder is based on the combination of BrentKung adder and Kogge Stone adder. The KoggeStone adder has maximum area and BrentKung adder has maximum delay. These two drawbacks are occurred in previously used adders. Proposed adder has to remove these drawbacks and it gives better area and delay results compared to koggestone adder. Flowchart for proposed adder is shown in figure.
The block diagram of proposed adder is shown in figure. In this diagram First taken the given inputs up to (a0, a1.a16) and (b0, b1..b16). By using these inputs to calculate the generation and propagation signals for (g0,p0),
Synthesis report for proposed adder
Selected Device: xa3s500eftg2564
Number of Slices: 145 out of 4656 3%
Number of 4 input LUTs: 252 out of 9312 2% Number of IOs: 443
Number of bonded IOBs: 443 out of 190 233% Maximum combinational path delay: 12.178ns
Adder name 
Area(slices ) 
Delay(ns) 
No of logic levels 
Ripple carry adder 16 bit 
15 
30.586 
16 
Carrylook ahead adder 16bit 
32 
29..613 
16 
Sparse Koggestone adder 16bit 
45 
14.85 
10 
Spanning tree adder 16bit 
42 
13.55 
10 
KoggeStone adder 16bit 
80 
10.72 
8 
Proposed adder 16bit 
60 
9.45 
7 
Ripple carry adder 32bit 
35 
42.69 
33 
Carrylook ahead adder 32bit 
70 
41.52 
33 
Sparse Koggestone adder 32bit 
105 
14.35 
11 
Spanning tree adder 32bit 
100 
12.65 
11 
KoggeStone adder 32bit 
190 
11.45 
8 
Proposed adder 32 bit 
142 
10.85 
7 
(g ,p )..(g ,p ). After the calculation of
1 1 16 16
generation and propagation signals using Kogge Stone ((KS) and BrentKung (BK) structures to perform Black cell and gray cell equations. In Koggestone structure each step gray cells are generated. BrentKung structure uses half of the gray cells are generated. To perform the generation of black cell and gray cell values to generate the carry values by using KoggeStone and BrentKung structures. After the calculation of all carry values these are combine with propagation signals with XOR operation to get sum(S) bits(S0,S1,S2,S3S16)
RESULTS
The synthesis results for proposed adder. Proposed adder uses no of slices, no of LUTS and no of bounded IOBs. The results for ripple carry adder, carrylook ahead adder, carrytree adders and our proposed adder.
These are Synthesis results for proposed adder. This report tells about selected device, Number of slices, Number of Look up tables (LUTs) and Delay. Area is represented in Number of slices and Delay is measured in nanoseconds (ns).
CONCLUSION
In this paper we have seen that the area utilization and delay performance of the field programming gate array (FPGA) kit has been reduced when compared to the proposed adders.
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