Encoding Technique for Low Power Design

Download Full-Text PDF Cite this Publication

Text Only Version

Encoding Technique for Low Power Design

Rajdip Das

Department of Electronics and Communication Engineering Supreme Knowledge Foundation Group of Institutions

1, Khan Road Mankundu, Hooghly, 712123, West Bengal, India

Abstract This research paper is a survey of the current status of research and practice in various disciplines of low power VLSI developments. The paper briefly discusses the rationale of the contemporary, and concentrates on low power design, it presents the metrics and techniques that are used to access the merits of the assorted proposed for the improved energy efficiency. Power dissipation [1], [5] has become an important consideration in terms of performance and scope for VLSI chip design. The research paper describes the varied strategies, methodology, and techniques for low power system design. Here also we have got to propose the encoding technique and compared with silent coding to scale back the transition state and conserved the power which is additionally described during this research.

KeywordsPower minimization, encoding technique, silent coding.

  1. INTRODUCTION

    More and more sophisticated signal processing systems are being introduced with a VLSI chip as the degree of integration continues to expand; these signal processing applications require not only high computing capabilities but also considerable energy consumption. The efficiency and field remain two key design objectives, electricity consumption in today's VLSI device design has become an important issue. Two main constrain are required for low power VLSI systems [2], [3]. Firstly, with the continuous increase in operating frequency and chip processing power, a big current is needed and thus the heat must be eliminated by proper cooling techniques because of its high energy consumption. Secondly, battery life is limited in handheld electronic devices; low power architecture ensures that these lightweight devices have an increased running period. Diwakar Tiwary [4] gave some ideas about different power management techniques which has opened up a new gateway in the field to meet futuristic challenges.

    However, the critical guiding force is that lack of adequate power to detect statistically significant change is becoming a major issue incorporating more transistors on a single chip or a module for multi-chip. Preliminary results have shown the feasibility of energy consumption that would significantly reduce the heat resulting from VLSI circuit packaging, which includes output processes and programs. After a few dormant years recently there has been a rapid turnover of designing a power reduction technique [6] for high-performance criteria. These strategies were able to yield a reduction in the severity of low power architecture, such as the clock gating for

    complex power reduction or several (multi-Vt) levels to minimize leakage current are the existing technologies [7] which are already well-established and funded.

    The main aim of this research is to reduce the no of transitions state. As we decrease the transitions we can conserve the power in a much more efficient way. In serial coding, SILENT coding is the most effective coding. In this paper, we have decreases the number of transitions more than the SILENT coding technique. The rest of the paper is organized as follows: The low power encoding and decoding methodology are presented in Section III, and experimental results in Section IV. Finally, the conclusion and future works are discussed in Section V.

  2. LITERATURE SURVEY

    There are different encoding techniques for low power design to scale back the transition, which means to cut back the switching activity so that we can conserve the power. Several techniques are accustomed which implements sequential data and a few are used for parallel data. Some of the examples of coding techniques are differential encoding techniques, sparse encoding, and limited-weight codes (LWC) are summarized below.

    1. Differential Encoding

      Differential encoding [8] comes under the algebraic encoding category which transmits XOR bit in between two consecutive values. In certain scenarios, its bus value shows a strong connection between them and due to this striking feature, the hamming distance (HD) between two successive values is either large or small. For example, most of the least significant bits (LSB) are identical, triggering a small HD for two succeeding values. On a similar scale, most significant bits (MSB) show a contrasting feature because of sign extension, which results in large HD. In both the situation, the use of differential encoding reduces bit transition state, as a result, almost all the bits within codeword (CW) become 0, and if delayed it becomes 1.

    2. Sparse Encoding and limited-weight codes(LWC)

    The Sparse Encoding technique offers an encoding scheme to reduce the number of 1s. A K-LWC is a sparse code illustration that corresponds to a community of CWs weighing up to K [9]. Note that in this term, the weight of a CW is the 1s number. We refer the reader to previous works [10], [11] for a statistical foundation of LWC. LWCs are constrained by the high logical complexity of their encoder and decoder and are not ideal for communication on the chip. The above encoding does not use any redundancy or metadata in either space or time. Space redundancy describes the use of additional bus lines and time redundancy demonstrates the use of extra transfer cycles.

  3. METHODOLOGY

    We proposed an encoding technique which helps to reduce the transition. Our encoding technique is applicable in sequential data. It helps to consume power as well as save battery life. We also found the decoding of our proposed encoding technique. We implemented this Technique in Xilinx. It briefly explains below.

    1. Proposed Encoding Technique

      In proposed encoding technique, as shown in Table I it checks every consecutive strings of length eight of each byte. First we take an arbitrary eight data bit like a0, a1, a2, a3, a4, a5, a6, a7. (e.g. – 11010010). At first we check two bit a7 and a6, if there is a transition then check the third bit i.e. a5. So if the transition likes 0 1 0 or 1 0 1 then last two bits are swapped.

      For example,

      010 001

      101 110

      Or else put a7 bit as it is and then the start checking from the next bit i.e. a6, and the process is being continued. Two additional lines L1 and L2 are introduced to check whether the swapping has done or not. First we divide the eight bit into four bit. If swapping is done in between a7 to a4 then L2 is considered as 1, otherwise L2 is considered as 0. If swapping happens in between a3 to a0 then L1 is considered as 1, otherwise L1 is considered as 0.

      TABLE I

      Fig 1. Example of encoding output

    2. Proposed Decoding Technique

      • Case 1: If L1 gets 1 then it will check from a0 to a4. When it will get different bit after two same bit then swapping occurs in that position.

      • Case 2: If L2 gets 1 then it will check from a3 to a7. When it will get different bit after two same bit then swapping occurs in that position.

      • Case 3: When L1 = L2=0 then the result will get after decoding will be same as encoding.

      • Case 4: When L1=L2=1 then checking occurs from a0 to a7.We summarized it in Table II, as shown below.

    3. Proposed Technique Implementation in Xilinx

    Xilinx is a synthesis tool that changes over Schematic/HDL design entry into practically proportional rationale logic gates on Xilinx FPGA, with streamlied speed and region. It has some unique features i.e. it has mixed mode HDL design entry, Xilinx ISE permits mix with different synthesis engine from mentor graphics/exemplar, synopsis, and simplicity (XST is restrictive Synthesis Tool of Xilinx.). We have selected Xilinx for speed, reliability, logic density and stability. We have also implemented the encoding, and decoding code in Xilinx. We have included a code of proposed encoding (Fig. 3) and decoding code (Fig. 4, 5) for reducing the transition state and data redundancy in Xilinx.

    Fig 3. Proposed Encoding Code

    TABLE II

    Fig 2. Example of decoding output

    Fig 4. Proposed Decoding Code (1)

    Fig 5. Proposed Decoding Code (2)

  4. EXPERIMENTAL RESULTS

    Preliminary functional experiments were performed to test the working functioning of CPU. Fig. 6 denotes the output of the encoding code which is simulated in the Xilinx ISE, and it is seen that when the reset signal is set to 1 value, it puts the CPU in the state of reset 1, which is the first condition of reset order. After the reset signal is fixed to 0, the CPU can have the ability to execute the reset_sequence. From the above factors it is concluded that there are two most excellent signals to watch out for, such as current_state and next_state. It was interesting to note that, when the reset input was set to 1, the CPU remained in reset 1 condition and when the signal reset is fixed to 0, on the rising boundary of the signal clock, current_state proceeds to reset 2 condition. At each signal clock rising edge which causes the CPU to proceed to the next step. A set of experiments were undertaken using different parameters each time until the source array is copied to the destination array. The simulator begins the simulation process. If the simulation is run ahead 100 nanoseconds, we observed that the CPU will start the reset sequence as the information is collected. This test is designed to verify the validity of functionality and the routed design. Note that, instead of one transition, the waveforms that are generated have number of transitions which are settled out. This transition encoding technique gives better results than other encoding techniques.

    TABLE III

    Fig 6. Output of Encoding reducing transtion state

    A. Comparison Between SILENT Coding And Proposed Encoding Technique

    We have compared SILENT coding and our proposed technique. It is known to all of us that SILENT coding reduces more transitions than any other serial encoding technique. So we compared with the technique to our proposed technique as shown in Table III. From the table, we can see that our proposed technique is much more efficient, and it reduces more transitions than SILENT coding.

  5. CONCLUSION & FUTURE WORKS

In our proposed encoding technique the main motto is to attenuate the number of transitions within the serial circuit to cut back dynamic power consumption because of switching activity within the capacitances. The proposed method has been compared with the SILENT encoding technique, which is merely effective for multimedia data applications. The encoding structure has been implemented that always ends up in a significant reduction within switching activity. The framework is tested for various sorts of data streams while accounting for the info correlations. It was observed that unlike the SILENT coding, power savings are achieved for all data types. However, the addition of two extra lines causes a touch area and power overhead and it requires special attention.

Future work should focus on the minimization of transition state by correct techniques of the region, and the overhead efficiency. We are still seeking to use such an encoding strategy that reduces the area overhead due to encoder and decoder circuit.

ACKNOWLEDGMENT

I want to acknowledge my deep sense of gratitude to my research guide Ms.Somrita Ghosh who directed and guided me with her timely advice and constant inspiration which eased the task of my research work.

REFERENCES

  1. An Implementation of Integrable Low Power Techniques for Modern Cell-Based VLSI Designs ,Ming-Chung Lee and Herming Chiueh ,doi 10.1109/ICECS.2006.379932.

  2. V. Sharma, S. Kumar,Low-Power 1-bit CMOS Full Adder using Subthreshold Conduction Region, International Journal of Scientific & Engineering Research, Vol. 2, June 2011.

  3. S. Hanson, B. Zhai, K. Bernstein, D.Blaauw, A. Bryant, L.Chang, K.

    K. Das, W. Haensch, E. J. Nowak, D. Sylvester, Ultra -Low Voltage, Minimum-Energy CMOS, IBM Journal of Research and Development, Vol. 50, No. 4-5, pp. 469-490, 2006.

  4. Power Management for Low Power VLSI design, Diwakar Tiwary,Mohd Javeed, 2018 IJCRT Volume 6, Issue 2 April 2018 | ISSN: 2320-2882.

  5. Various Methodologies for Low-Power VLSI designs, Dr. R. Prakash Rao, JASC: Journal of Applied Science and Computations Volume 5, Issue 10, October/2018, ISSN NO: 1076-5131.

  6. Rahul. M.Rao, Jeffery L.Burns, Richard B.Brown, Circuit Techniques for gate and subthreshold leakage minimization in future CMOS technologies Proc. ISLPED, pp70-73, 2002.

  7. Prasad Subramanian, Power management for optimal power design, ESILICON, Corp.2010.

  8. D. Jahier Pagliari, E. Macii, and M. Poncino, Approximate differential encoding for energy-efficient serial communication, in Great Lakes Symposium on VLSI. ACM, 2016, pp. 421426.

  9. M. R. Stan and W. P. Burleson, Limited-weight codes for low-power I/O, in International Workshop on low power design, vol. 6, no. 3, 1994, pp. 68.

  10. M. Choudhury, K. Ringgenberg, S. Rixner, and K. Mohanram, Single- ended Coding Techniques for Off-chip Interconnects to Commodity Memory, in Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE07. IEEE, 2007, pp.16.

  11. Y. Song, M. N. Bojnordi, and E. Ipek, Energy-efficient data movement with sparse transition encoding, in Computer Design (ICCD), 2015 33rd IEEE International Conference on, 2015, pp. 399 402.

Leave a Reply

Your email address will not be published. Required fields are marked *