Electrostatic Field Effects in Hardware Module Interface in Automotive Application

DOI : 10.17577/IJERTV2IS90032

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Electrostatic Field Effects in Hardware Module Interface in Automotive Application

Tamilarasu.S1, P.Thirunavukkarasu2, N.Sethupathi3

1 Research Scholar, Bharathiar University, Coimbatore, India. 2 Associate Professor, Dept of Electronics, SRMV College, Coimbatore, India. 3 Asst Professor, Dept of Physics, A.A.Govt Arts College, Namakkal, India.

Abstract Electrostatic Discharge (ESD) causes electrostatic field effect, charge injection effects, and effects due to fields generated by ESD currents. Proper system cable design can help combat and reduce the failure effects. Effects will be classified in to two categories, due to radiated noise & due to conducted noise. Radiated noise included the effects of both electrostatic filed electronic and magnetic fields generated by the discharge current. Conducted noise includes direct charge injection and current inducted by electronic and magnetic fields. We cant eliminate these effects in the system, but we can minimize the risk by design and configuration.

Index Item EMC, ESD effects, Module Interface, Interface cables

  1. Introduction

    Today many automotive applications comes with lot of features including, car entertainment, automotive networking, automotive immobilizers and keyless entry & start and etc. The inputs and outputs of all these modules will be connected via cables. Many of those are not different from non-automotive, especially with respect to ESD. Once installed into the system, the components inside the modules are not threatened anymore. In the automotive world, product pins directly interfacing with the outside world (battery monitors, airbag sensors) may see another type of ESD threat. This is the so-called system level ESD. At 20KV an arc can jump 2cm through air. And cables between modules can easily be efficient antennas at a frequency of few hertz to few megahertz.

  2. Module Interfaces

    The main function of the interface circuit is to provide a data link between different systems or subsystems. There are a number of interface standards that cover different data link and signal specifications for transmitting through a cable, from several inches within the same system block to several meters between systems within the same vehicle.

    Example, In comparison with DAC, one the major specifics of advanced interface products is the high speed of the data transmission. From an ESD specific point of view, a typical requirement may include on-chip system-level pins. Typically, the cable discharge event protection level is specified. Another peculiarity of the interface circuit is the presence of high common-mode voltages in the input signal.

    Just like RF-amplifiers, the high-speed input interface pins require broadband characteristics. This eliminates the possibility of application of a number of narrow band, LNA-specific input solutions that rely on ESD pulse bandwidth filtering. Over recent years, interface applications are heading toward few Gbps links. Achieving these goals requires not only increase of speed but also corresponding reduction in power consumption and noise.

  3. Representation

    Interface parameters are related to the power moving in the network and in and out of the integrated circuits. The interface characteristics are often described in terms of the equivalent S-parameters.

    Input Signal Conditioning

    Input Signal Conditioning

    The transducer gain parameter GT is the ratio of the power delivered by a network to a load (Pdl) to the power available from the source (Pas). Transducer gain is a function of the source and load reflection coefficients and the networks-parameters.

    matching. A functional block diagram an interface application is presented in Fig.1.

    Processing Unit

    Processing Unit

    Processing Unit

    Processing Unit

    O/P 1

    Input Signal Conditioning

    Input Signal Conditioning

    I/P 1

    This can be expressed as shown in the following formula:





    G Pdl as

    The maximum power-transfer theorem

    says that to transfer the maximum amount of power from a source to a load, the load impedance should match the source impedance. In the basic circuit, a source

    I/P 2

    I/P 3

    I/P 4

    I/P 5



    Interface Cables


    O/P 2

    Output Switching Control

    Output Switching Control

    O/P 3

    O/P 4

    O/P 5

    may be dc or ac, and its internal resistance (RI) or generator output impedance (ZS) drives a load resistance (RL) or impedance (ZL).

    At matching load and source impedance,

    ZL=ZS=50 /100 and GT =|S21|

    The operating power gain parameter GP represents the ratio of the power delivered to the load to the power delivered to the network.

    The operating power gain parameter GP represents the ratio of the power delivered to the load to the power delivered to the network. The power delivered to the network is dependent on the S11 parameter. In this case, GP > GT and GT is closer to GP with better input matching.

    The available power gain GA is the ratio of the power available at the output of a network (Pao) to the power available from the source to the source (Pas). This can be expressed as shown in the following formula:





    G Pao


    Since the power available from the network is dependent on S22, GA > GT, while GT approaches GA with better load

    Fig. 1 Function block diagram, for example, module interface solution

    In terms of the ESD protection challenge, the interface application requires the CDE protection for the selected pins directly interfacing with cable. To address the design specific, the next section presents the CDE test methodology.

  4. ESD Protection for Cable Interface

    External cabling is a greater problem. Due to their direct illumination during ESD, cables become unintentional, but efficient antennas, converting the radiated field into induced voltages and currents. Fig.2 shows a summary of what happens to external cables during an ESD event. To combat the effects of this ESD coupling, two approaches are available, which depend on the nature of the external cables and of the equipment enclosure.

    If the external cables are shielded (maybe for other EMC reasons, and probably not just against ESD), they will perform efficiently against ESD, provided some precautions are taken, the same as those used for good RF shielding results.

    ESD 1 B



    H(A/m) = I/(2d) ———- Eq1


    A I = ESD current in amperes

    2 2 d = distance from ESD path to victim circuit

    D C


    Fig.2 External cables to ESD coupling

    If the system external cables are not normally planned to be shielded, and the equipment box is eventually plastic, there is no sense in shielding them for meeting an ESD immunity level. In this case, the ESD-induced pulses could penetrate the equipment by the external cable conductors, and they must be filtered, or eventually clamped, at the cable entry port.

  5. Magnetic Field Coupling

Figure 3 shows a simplified model of this phenomenon, based on the discharge current only. A first thing to point out is that the dimensions of the ESD generating circuit are large compared to its distance to the receiving circuit. Therefore, it cannot be treated as a punctual source. Simple solutions of Maxwells equation for small electric or magnetic doublets with their

resulting (1/d)2 and (1/d)3 ield-to-distance dependency cannot be straightforwardly applied.

A rigorous approach would be to apply the method of moments to the current path, broken down in small filaments. The much simpler model shown assimilates the ESD current path to a long radiating wire for which the resulting magnetic field is easily calculated from the Biot and Savart law. The ESD drain path to ground being long versus the distance of observation the magnetic field is given by:




Fig. 3 ESD coupling by radiation.

Simplified model: the H field is modeled from an infinite straight wire, carrying IESD

Amperes law: H = I /2 R

Example: IESD = 15 A (from a 4 kV simulated ESD)

Distance R



Voltage Induced in 1 cm2 loop

Rise time 1ns

Rise time 10ns

3 cm





10 cm





30 cm

8 A/m



If the area of the circuit illuminated by the ESD field is known, a derivation of the field over the rise time gives an approximation of the open-loop voltage induced, generally sufficient for a quick prediction.

V d

i dt



——– Eq2

interfaces. A good ESD performance built upon an intensive use of well-shielded cables and capacitive decoupling of I/O


Vi = Induced voltage in V

A = Victim circuit area in m2

B = Induction in teslas, with 1 tesla = 104 gauss = 80 × 104 A/m

Rearranging Eqs (1) and (2) and using more convenient units, we end up with:

ports may deteriorate when the unit is not equipped with all these cables, or some unit(s) at the other end presents higher common mode impedance to ground than what was used as a test vehicle. To reduce the time-to-market for such R&D work, physical device and mixed-mode simulations are critically important tools.

VII. Reference




Vi td

——– Eq3

  1. Boissieres, F. Electrical Interface


    I = Change in ESD current in A

    A = Victim circuit loop area in cm2

    t = Rise time of the ESD current in ns d = Distance from ESD path to victim circuit in cm

    Fig.3 gives the results in voltages induced per centimeter squared of victim area, for three distances from the ESD path, assuming rise times of:

    • 1 ns typical of the fast precursor peak with a hand/tool discharge 8 kV

    • 10 ns more typical of simple hand discharge or air discharge above 8 kV

    VI. Summary

    In this paper, ESD protection challenges and solutions have been discussed. When a unit is designed (and/or hardened) to meet a given ESD severity criteria, it must be checked, during design and testing face. The level that has been achieved for the maximum system configuration (all possible cables, features, and peripherals installed) is still met for the minimum size or, eventually, a stand-alone configuration. Immunity does not rely exclusively on a drastic treatment of the I/O cables and

    Presentation. ST MiCroElectronics Corp. 2008.

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