Electronics Properties of Si Nanocrystals Mixed-LaF3 layer produced by a novel chemical bath deposition technique

DOI : 10.17577/IJERTV2IS90698

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Electronics Properties of Si Nanocrystals Mixed-LaF3 layer produced by a novel chemical bath deposition technique

Sheikh Rashel Al Ahmed 1 and Abu Bakar Md. Ismail 2

1Department of Electronic and Telecommunication Engineering, Pabna University of Science and Technology, Pabna 6600, Bangladesh.

2Department of Applied Physics and Electronic Engineering, Rajshahi University, Rajshahi 6202, Bangladesh.


Electronic properties of Si-nanocrystal (Si-NCs) mixed in Lanthanum Fluoride (LaF3) layer fabricated using a novel chemical bath deposition technique has been reported here. The Si-NCs was fabricated by sonicating porous silicon. Thin layer LaF3 containing Si-nanocrystals was deposited by a novel chemical method. Scanning electron microscopy (SEM) confirmed the presence of Si- NCs and energy-dispersive X-ray (EDX) analysis of the deposited layer revealed a non- stoichiometric LaF3 layer embedding Si-NCs. Electronic properties of the deposited layer were investigated using the capacitance-voltage (C-V) and conductancevoltage (GV) measurement of MIS device fabricated in [Ag/LaF3/Si-NCs/Si/Ag] structure. Capacitance-voltage (C-V) study revealed that resonant tunneling of electron and charge storage was there. The effect of thermal annealing on the electronic properties was also studied. The Size uniformity of the Si-NCs can be improved by annealing.

Keywords: Silicon nanocryatals, Capacitance, Conductance, Metal-insulator-semiconductor (MIS) device, chemical bath deposition

  1. Introduction

    In the last few years, metalinsulator semiconductor (MIS) devices with semiconductor nanocrystals embedded in insulating layers have attracted in nanoscale electronic and optoelectronic devices [1-3]. Such nanoscale quantum structures are also excellent candidates for investigations of fundamental physical properties and for potential applications in next-generation memory devices [4- 6]. The physical phenomenon of the constructed MIS [Ag/LaF3/Si-NCs/Si/Ag] structures is the direct tunneling of electron through the ultra-thin insulating layers (LaF3) into the NCs. The NCs act as charge storage centres whose charge state may be influenced by application of a DC bias voltage across the device. Therefore, the formation of the silicon nanocrystals (NCs) and the ultrathin LaF3

    layers is a key technology to ensure the operation of such charge storage elements based MIS devices. Good size uniformity for Si-NCs and high quality for ultrathin LaF3 layer is an important feature for such MIS structures. Several studies reports the use of different high-k materials such as SiO2 [4], Si3N4 [7], HfO2 [8], ZrO2 [9], etc.

    Researcher have been developed for nanocrystal

    formation in a dielectric matrix, such as electron beam evaporation [10], low-energy ion implantation [11-14], chemical vapor deposition [15-18], or ion beam co-sputtering [19], [20]. In this work, the use of silicon nanocrystals (Si-NCs) embedded lanthanum fluoride (LaF3) insulating layer in MIS device fabricated for the first time by using a novel chemical bath deposition (CBD) technique. LaF3 has been chosen as alternative candidates for gate insulator because of their large band gap, high dielectric constant, and large refractive index. Moreover, the lanthanide fluorides (LaF3) show good characteristics without pre- formed interfacial layer, and regarded as high-k dielectrics [21]. The structural and electrical properties on a novel chemical bath deposited Si- NCs-embedded LaF3 for MIS device have been analyzed in this paper. The focus of this work is the experimental (CV) and conductancevoltage (G

    V) characteristics of Ag/LaF3/Si-NCs/Si/Ag structures at different annealing temperatures.

  2. Experimental methods

    MIS device containing a layer of Si-NCs embedded in LaF3 were fabricated on a p-type <111> single crystal silicon substrates. Device fabrication began with Ultrasonic cleaning of the substrate and formation of porous silicon (PS) & silicon nanocrystals (Si-NCs).

    Porous silicon sample were prepared by standard electrochemical etching of p-type <111> Si wafers in a homemade double tank cell at different current densities for 30 minutes under room light illumination. Etching was done in a 2.5:1 (v/v) solution of 48% HF and absolute ethanol. Colloidal suspensions of silicon nanocrystals were prepared from as made porous silicon in hydrofluoric (HF) acid by Ultrasonic Vibration (sonication) at a frequency of 40 kHz. After the etching process, the

    PS samples were immersed in hydrofluoric acid (HF) in a small plastic container and this container was immersed in water. Ultrasonic wave was applied to the water through the ultrasonic probe to vibrate the PS layer for about 60 minutes. The sonication was done at various ultrasonic powers of 12, 18 and 32 W. The sonication crumbles the top layer of the as made PS, a weakly interconnected nanostructures network into ultra-small particles and produces a luminescent and reddish, colloidal suspensions of Si-NCs.

    After formation of the colloidal suspensions of silicon nanocrystals in HF, using a novel chemical bath (CBD) deposition technique, warm 0.6M- lanthanum chloride (LaCl3) solution in HCL was allowed to react with the HF of the colloidal solution that contains Si-NCs. Due to high solubility of LaCl3 in HCL solution, HCL was chosen as a solvent of LaCl3. The solubility of LaCl3 in HCl solution depends on temperature [22] and why the solution was heated at 45C for 20 minutes before reacting with the colloidal solution. The chemical reaction was done on a Si substrate and the possible chemical reaction of the of HF in the colloidal solution, LaCl3 and hydrochloric (HCl) could be,

    HF + LaCl3.7H2O LaF3 + HCl + H2O

    The samples were annealed at 100°C 400°C for 10 min.

    A schematic diagram of a completed Si:NC-MIS [Ag/LaF3/Si-NCs/Si/Ag] device is depicted in figure 1. SEM observations were performed in a JEOL-JSM-6490LA scanning electron microscope operating at 30 kV. C-V and G-V measurements were performed by using an impedance analyzer at different frequency. Ohmic contacts were fabricated by silver (Ag) evaporation on both sides of the prepared samples.

    Figure 1: Schematic diagram of a fabricated Si:NC- MIS [Ag/LaF3/Si-NCs/Si/Ag] structure.

  3. Experimental results and discussion

    SEM photograph as shown in figure 1 clearly depicts the presence of silicon nanoparticles.

    Various sizes of nanoparticles were viewed there. The smallest size was found to be of the order of 50 nm. The average size of the Si-NCs was dependent on the anodization current during the fabrication of porous silicon and sonication power.

    Figure 2. SEM image of silicon nanocrystals.

    EDX studies were used to analyze the elemental composition of the Si-NCs embedded in lanthanum fluoride deposited Si films. As shown in figure 5, the EDX spectrum revealed small carbon in the system because carbon tape were used for contact the sample with the sample stage. The elemental composition of above mention samples are shown in Table 1.

    Table 1 shows the atom and weight percentage of various elements in the LaF3/Si-NCs/Si system which confirms the non-stoichiometric nature of LaF3 deposited sample.

    Figure 3: EDX spectrum of the LaF3/Si-NCs/Si system.




















    Figure 3 shows the Capacitance-Voltage (C-V) curves of the Ag /LaF3/Si:NCs/Si/Ag configuration act as Si:NC-MIS device samples for various frequencies (from 100 Hz to 1MHz). Figure 3(a) and 3(b) shows the C-V characteristics of the sample annealed at 100°C or 10 min and 400°C for 10 min. Capacitance-Voltage (C-V) measurements were performed at room temperature using a standard C-V measurement setup. The measurements were obtained by sweeping the bias from -2V to +2V and back to -2V. The DC voltage was applied to the top Ag electrode with respect to the back Ag contact and superposed with various frequencies with the signal amplitude of 50mV.

    1. Annealed at 100°C

    2. Annealed at 400°C

      Figure 3. The Capacitance-Voltage (C-V) characteristics of the annealed sample at 100°C for 10 min (a) and 400°C for 10 min (b), respectively.

      From the C-V curves, clear capacitance peaks were observed in the inversion region at the lower frequencies, while for the reference sample (that is, the MIS structure not containing Si-NCs), no peaks were observed in the C-V characteristics. The capacitance peaks were attributed to carrier exchange between the semiconductor substrate and

      bound states quantum confinement of carriers in the Si-NCs.

      The capacitance peaks indicate the results from the size fluctuation of the Si-NCs. The variations of capacitance peak with annealing temperature are shown in Figure 4. Enhanced peak was observed for higher annealing temperature (400°C) than that at a lower annealing temperature (100°C) for the same annealing time. These manifest that annealing can improve the size uniformity of the Si-NCs. At the higher temperature, the size of the Si-NCs becomes more uniform than that at the lower temperature.

      Figure 4: Variation of capacitance with annealing temperature.

      From the capacitance- frequency (C-f) characteristics in Figure 5, it is apparent that the capacitance value does not change with frequency when the frequency higher than 500 kHz, and the capacitance value increases with decreasing frequency when the frequency is lower than 500 kHz. These are related to the different tunneling ability of the electrons at the different frequencies. At lower frequencies, electrons have more time to tunnel into Si-NCs; while higher frequencies, electrons cannot follow ac modulation and cannot tunnel into Si-NCs.

      Figure 5: The capacitance-frequency characteristics for the annealed samples.

      Figure 6(a) shows the conductance voltage (GV) curves of the Si:NC-MIS devices, were measured at room temperature for various signal frequencies of 1 kHz, 10 kHz, 50 kHz, 100kHz, 500kHz and 1 MHz with bias voltage (Forward Scan). The voltage was applied to the top Ag electrode with respect to the back Ag contact and the bias voltage was swept from negative to positive. One can be seen in the conductance voltage (G-V) measurements of Figure 6 for the 100°C annealed sample, a conductance peak can be observed due to the electron charging into the Si-NCs in the region where the capacitance peak appear, as shown by curve in Figure 4(a).



      Figure 6. ConductanceVoltage (G-V) characteristics for the 100°C annealed sample at different frequencies (a), and Variation of conductance peak magnitude with frequency (b)

      The G-V peak curve reports the displacement current in the sample and thus the conductance increases, causes of electrons in the substrate tunnel through the ultrathin LaF3 layer into the Si- NCs. It is also observed from the G-V

      characteristics that conductance peaks whose magnitude and position are highly dependent on frequency which attribute two features: (a) Increases in the small signal frequency shift the peak to less negative bias voltage; (b) the magnitude of the conductance peak increase linearly with frequency, as shown in Figure 6(b).

  4. Conclusion

    In summary, silicon nanocrystals embedded in a LaF3 layer for metal-insulator-semiconductor (MIS) device have been successfully fabricated by a novel chemical bath deposition (CBD) technique. The SEM image also confirmed the presence of silicon nanocrystals and it has been obtained various sizes of the Si-NCs during sonication. From the EDX spectrum, it was observed that the deposited LaF3 layer was non-stoichiometric. By C-V and G-V measurements, resonant tunneling of electron and charge storage was observed in silicon nanocrystals at room temperature. The size uniformity of the Si-NCs can be improved by high temperature annealing. The C-V curve for Ag/LaF3/Si-NCs/Si/Ag capacitors showed an MIS behavior with capacitance peak due to the quantum-confinement effect of the silicon nanocrystals in spite of the possible existence of the ultrathin LaF3 layer. The G-V curve also showed a conductance peak due to the electron charging into the Si-NCs in the region close to the capacitance peak.

    It can be concluded from this present result that MIS device containing silicon nanocrystals in the LaF3 insulating layer fabricated by a very simple CBD technique can be of enormous interest in future silicon nanoelectronic devices such as nonvolatile memory devices.

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