Design of Low-Power Hybrid Full Adders using Full-Swing XOR–XNOR Gates

Design of Low-Power Hybrid Full Adders using Full-Swing XORXNOR Gates

Dasari Yugandhar (1), Agatamudi Harsha Vardhini (2)

Electronics and Communication Engineering / Aditya Institute of Technology and Management/ Tekkali, India Corresponding author: MIG-199, APHB Colony, Opposite ZP Office, Srikakulam, Andhra Pradesh-532001

Abstract: This paper presents a family of hybrid 1-bit full-adder circuits based on full-swing XOR/XNOR and simultaneous XOR XNOR logic. The proposed architecture combines the XORXNOR block with transmission-gate-based 2:1 multiplexers to generate the Sum and Carry outputs. Six hybrid full-adder variants are described: HFA-20T, HFA-17T, HFA-B-26T, HFA-NB-26T, HFA-22T, and

HFA-19T. The designs target low power dissipation, reduced propagation delay, low output capacitance, full-swing operation, and improved driving capability. The manuscript also considers the use of the proposed full-adder cells in ripple-carry structures. The study reports circuit-level simulation and investigates the effects of supply voltage, output capacitance, threshold voltage, input noise, and transistor sizing. The proposed structures are intended for low-power VLSI applications such as arithmetic units, digital signal processing, and microprocessors. Quantitative power, delay, and power-delay- product results should be inserted after final verification of the simulation setup.

Keywords: full adder; XOR; XNOR; XORXNOR; hybrid logic; transmission gate; low-power VLSI; power-delay product; ripple- carry adder

1. INTRODUCTION

   Arithmetic circuits are fundamental components of digital systems, and adders form an important building block for arithmetic and data-processing operations. Full adders are used in arithmetic logic units, multipliers, address-generation circuits, digital signal processors, and related VLSI systems. As integration density increases and portable electronics demand lower energy consumption, full-adder implementations must balance power, propagation delay, area, output swing, and driving capability.

   The proposed study identifies XOR/XNOR logic as a major contributor to the power and delay of a full-adder cell. Conventional implementations based on CMOS, complementary pass-transistor logic, transmission-gate logic, and hybrid approaches provide different trade-offs. In particular, non-full-swing internal nodes, excessive output capacitance, and NOT gates on critical paths can degrade the overall performance of a hybrid adder.

   The objective of this work is to develop and organize a family of hybrid full-adders around a full-swing XOR/XNOR or simultaneous XORXNOR circuit and a transmission-gate 2:1 multiplexer. The resulting designs are intended to reduce power and delay while retaining full-swing outputs and practical driving capability.

2. MATERIALS AND METHODS

   A 1-bit full adder has three inputs, A, B, and Cin, and two outputs, Sum (S) and Carry-out (Cout). The Boolean equations used in the source manuscript are:

   The functional truth table of the 1-bit full adder is presented as Table 1

   .Table 1: Truth table of the 1-bit full adder.

   A	B	Cin	Cout	S
   0	0	0	0	0
   1	0	0	0	1
   0	1	0	0	1
   1	1	0	1	0
   0	0	1	0	1
   1	0	1	1	0
   0	1	1	1	0
   1	1	1	1	1

   The proposed family uses a hybrid logic structure in which a full- swing XOR/XNOR or simultaneous XORXNOR circuit supplies the data inputs of transmission-gate 2:1 multiplexers. The carry input is used as a selection signal. This organization follows the functional relationships identified in the source manuscript: when Cin = 0, the Sum output follows A B and the Carry output follows A · B; when Cin = 1, the corresponding data functions are A XNOR B and A + B.

   Fig 1: Block diagram of the hybrid full-adder architecture based on XOR/XNOR logic and transmission-gate multiplexers.

   The XORXNOR block described in the manuscript uses six transistors, consisting of three PMOS and three NMOS devices. The design generates complementary XOR and XNOR outputs with full voltage swing. The proposed full-adder variants then modify buffering, critical-path inversion, and the use of the carry signal to control internal capacitance and output drive.

   1. PROPOSED FULL-ADDER VARIANTS

      HFA-20T: The HFA-20T uses the six-transistor XORXNOR block and two 2:1 transmission-gate multiplexers. The design contains 20 transistors and provides full-swing outputs. The HFA- 20T has reduced output driving capability in chain applications as a limitation when no output buffering is used.

      HFA-17T: The HFA-17T reduces the transistor count to 17 by generating one of the complementary signals through an inverter.

      This reduces the number of transistors but places an inverter on the critical path, which can increase latency and short-circuit power.

      HFA-B-26T: The HFA-B-26T introduces output buffers at the Sum and Carry outputs. The buffers improve the ability of the cell to drive practical loads, although the reported design analysis indicates an associated increase in delay and power relative to the smaller unbuffered cells.

      HFA-NB-26T: The HFA-NB-26T places buffers at the data inputs of the 2:1 multiplexers. According to the manuscript, this arrangement can stabilize the multiplexer data nodes before the XOR/XNOR signals are generated. Its critical path contains the XORXNOR block and a 2:1 multiplexer, while its output driving capability is influenced by the multiplexer resistance.

      HFA-22T and HFA-19T: These variants add the carry signal to the Sum-generation structure so that the XOR and XNOR nodes do not directly drive the Sum output. The study states that the resulting reduction in XOR/XNOR-node capacitance is expected to improve delay and power relative to the corresponding HFA-20T and HFA- 17T structures, while the additional transistors can improve driving capability.

      Table 2: Structural summary of the proposed full-adder cells.

      transition time, output load capacitance, simulation duration, and measurement definitions.

      The study reports Tanner simulation with a 45-nm CMOS technology model in its abstract and earlier sections. The conclusion additionally reports Microwind simulations using 90-nm and 180-nm CMOS technology. Because these statements are not internally consistent, the final manuscript must identify one verified simulation flow or clearly separate multiple experimental setups before publication.

      The principal metrics should be defined as follows: average power consumption, worst-case propagation delay, and power-delay product. For a consistent comparison, all competing cells should be simulated under identical supply voltage, technology, input activity, load capacitance, and transistor-sizing assumptions.

      PDP = Pavg × tpd

      The manuscript also discusses sensitivity to supply voltage threshold voltage, output capacitance, input noise, and transistor sizing. These analyses should be reported using clearly specified parameter ranges and a consistent baseline configuration.

      The final experimental description should state the simulator, CMOS technology node, supply voltage, load capacitance, input conditions, transistor dimensions, and measurement procedure consistently.

      Cell	T	Main structural feature
      HFA-20T	20	XORXNOR + two TG 2:1 MUXs
      HFA-17T	17	XOR/XNOR with inverter-generated complement
      HFA-B-26T	26	Output buffers at Sum and Cout
      HFA-NB-26T	26	Buffers at MUX data inputs
      HFA-22T	22	HFA-20T with carry-assisted Sum path
      HFA-19T	19	HFA-17T with carry-assisted Sum path

      Fig 2: Six proposed hybrid full-adder circuits: HFA-20T, HFA-17T, HFA-B-26T, HFA-NB-26T, HFA-22T, and HFA-19T.

   2. SIMULATION AND EVALUATION METHODOLOGY

   The study describes transistor-level evaluation of the proposed circuits and discusses power consumption, propagation delay, power- delay product (PDP), output capacitance, supply voltage, threshold voltage, input noise immunity, and transistor sizing. A journal submission should report the exact simulator version, CMOS model, technology node, supply-voltage range, transistor dimensions, input

3. RESULTS

   The truth table in Table 1 verifies the intended full-adder functionality. The proposed architecture derives the Sum and Carry outputs from complementary data functions selected by Cin, consistent with the full-adder equations given in Section 3.

   The study also considers a ripple-carry implementation in which the carry output of one full-adder stage drives the carry input of the next stage. This structure is useful for assessing the driving capability and cumulative delay of the proposed cell.

   Fig 3: Four-bit ripple-carry adder structure using the proposed full-adder cell.

   The supplied manuscript does not contain a complete extractable numerical table for power, delay, PDP, area, and technology node. These values should be inserted from the verified simulation outputs before submission.

4. DISCUSSION

   The architectural discussion indicates several design trade-offs. Reducing transistor count can reduce circuit complexity, but adding an inverter to the critical path can increase delay and short-circuit power. Output buffering can improve load-driving capability but introduces additional capacitance and switching activity. Conversely, reducing the capacitance of internal XOR/XNOR nodes can improve the delay and power characteristics of the overall full-adder cell. These trade-offs should be demonstrated quantitatively using a

   common simulation environment rather than only qualitative statements.

   For journal publication, the comparison should include representative conventional and hybrid full-adders from the cited literature. The comparison must use equivalent technology and test conditions, or the differences in technology and loading must be explicitly stated.

   The proposed full-adder structures are intended for arithmetic and data-processing blocks in low-power VLSI systems. Potential application areas identified in the source manuscript include arithmetic logic units, digital signal processing, microprocessors, multipliers, address-generation circuits, comparators, parity circuits, and related arithmetic structures.

5. CONCLUSION

A family of six hybrid full-adder cells based on full-swing XOR/XNOR and simultaneous XORXNOR logic has been organized and described. The proposed architecture combines a compact XORXNOR block with transmission-gate multiplexers and optional buffering or carry-assisted signal routing. The six variants provide different trade-offs among transistor count, critical-path complexity, output driving capability, internal capacitance, power, and delay. The study indicates that these structures are intended for low-power and high-speed VLSI applications.

ACKNOWLEDGMENT

The authors may acknowledge institutional support, funding agencies, laboratory facilities, and technical assistance, where applicable.

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CONFLICT OF INTEREST

The authors should declare any financial or personal relationships that could have influenced the work. If none, state: The authors declare that they have no conflict of interest.

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