 Open Access
 Total Downloads : 20
 Authors : S. Eswari, A. Raj Kumar
 Paper ID : IJERTCONV1IS06146
 Volume & Issue : ICSEM – 2013 (Volume 1 – Issue 06)
 Published (First Online): 30072018
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Design of Low Error and Power Fixed Width Multiplier by Using Dual Tree Error Compensation
S. ESWARI, A. RAJ KUMAR

(VLSI Design), Associate Professor (ECE)
Srinivasan Engineering Colleg1, Srinivasan Engineering College,
eswarivlsime@gmail.com, arkumar77@gmail.com
AbstractIn this paper, a new errorcompensation network for fixedwidth multiplier is proposed. The error compensation block is composed of dual trees which are optimally chosen in order to minimize either the meansquare error or the maximum absolute error. The new technique significantly improves error performance with respect to previous approaches. Simulation results show that new fixedwidth multipliers exhibit significant improvements both in mean square error and in power dissipation with respect to previous solutions. As compared with the stateoftheart , the proposed fixedwidth multiplier performs not only with lower compensation error but also with lower hardware complexity, especially as multiplier input bits increases.
Index TermsDigital integrated circuits, Fixedwidth multipliers, hardwareefficient, lowerror.

INTRODUCTION
In many highspeed digital signal processing (DSP) and multimedia applications, the multiplier plays a very important role because it dominates the chip power consumption and operation speed. In DSP applications, in order to avoid infinite growth of multiplication bit width, we usually have to reduce the number of multiplication products. Cutting off nbit less significant bit (LSB) output can construct a fixedwidth multiplier with nbit input and nbit output. However, truncating the LSB part leads to a large number of truncation errors.
Many truncation error compensation techniques [1][10] have been presented to design an error compensation circuit with less truncation error and less hardware overhead. The compensation methods can be divided into two categories: compensation with constant correction value [1][3] and compensation with variable correction value [4][10]. The circuit complexity to compensate with constant corrected value can be simpler than that of variable correction value; however, the variable correction approaches usually can be more precise.
Many techniques have been proposed which exploit the fixedwidth property to reduce hardware complexity with respect to rounded fullwidth multiplier [12], [15][18]. In order to simplify the review and the comparison of these
techniques, let us subdivide the partial products in the three subsets most significant part (MSP), input correction vector (IC), and less significant part (LSP) shown in Fig. 1.
The approximation error of fixed bias correction (13) is investigated in [16] by Lim. It is shown that the error rapidly increases with multiplier size. The error can be reduced by retaining more partial products (for instance the IC partial products) before adding the fixed bias K. Obviously, this results in a tradeoff between precision and hardware complexity.
In [15], Kidambi et al. simplify the multiplier by deleting both IC and LSP partial products. A precomputed constant is added to the final output in order to compensate for the introduced error. The fixedwidth multiplication is hence approximated as follows in (1):
(1)
This technique provides a hardware complexity about halved with respect to a full multiplier. However, the introduced error is high, reducing practical applications.
A multiplier calculates P=X.Y as weighted sum of partial products xiyj
(2)
Full multiplier partial product matrix

FIXEDWIDTH MULTIPLIERS ERRORS


Error Metric
Fig.1.
proposed in [16].This algorithm, basically, exploits the correlation between the IC partial products and the sum of LSP partial products. Neither algorithm hardware implementation nor circuit performance analysis is given in [16].
The conditional correction algorithm is further developed in [17] by Jou et al.. In the Jou architecture, the IC partial products are summed to compute an intermediate quantity SIC
SIC = x1.yn+x2.yn1++xn.y1 (3)
The sum SIC is then used to calculate a correction factor that estimates the sum of dropped partial products.
In this paper, a new approach to design high performance unsigned fixedwidth multipliers is proposed. The multiplier is based on multipleinput errorcompensation architecture, like [12], [18]. A new errorcompensation function f ( ) is developed, that can be optimized in order to minimize either the maximum absolute error or the meansquare error. Our errorcompensation function, moreover, can be implemented by using only a few gates, with tree architecture. As a consequence, proposed approach is ideally suited for fast tree based multipliers [14].
The Results for a circuit implementation in 0.35 m technology and a comprehensive comparison with previously proposed techniques are also reported in the paper.
The accuracy of a fixedwidth multiplier can be evaluated
considering the introduced error with respect to the output of the bit complete multiplier:
Â£=PPt (4)
where is the output of the complete multiplier given by (2), and is the output of the fixedwidth multiplier. As error metric we consider either the normalized maximum absolute error (Â£max) or the normalized meansquare error (Â£ms) defined as
Â£max =max (Â£)/LSB (5)
}/LSB
Â£ms =E {Â£2 2 (6)
Where E{} is the average operator, while LSB=2n is the weight of the less significant bit at the output of the multiplier. Another parameter useful to characterize fixedwidth multipliers accuracy is the normalized mean error (Â£m), given by
}/LSB
Â£m =E {Â£ 2 (7)
An improved fixedwidth multiplication algorithm, named partial product conditional correction, is also

Errors in Rounded FullWidth Multipliers
The simplest way to obtain a fixedwidth multiplier is through a rounded, fullwidth multiplier. Rounding introduces a quantization error, that is well known to provide Â£max =1/2 and
Â£ms=1/12 [16]. These values are a lower bound for the errors achievable with any fixedwidth multiplier, since fullwidth multiplier rounding is the most accurate fixedwidth technique.

Error Bounds for FixedWidth Multipliers with Multiple Input Error Compensation
Let us consider a fixedwidth multiplier design is given
by
Â£=PPt =s(x1,.,xn:y1,.yn)f(IC) (8)
where s(x1,.,xn:y1,.yn)=s(x;y) is the sum of the IC and LSP partial products The accuracy of fixedwidth multipliers with multipleinput error compensation depends on the choice of errorcompensation function. The electrical performance depends on implementation of errorcompensation function.
TABLE I
PERFORMANCES OF FIXEDWIDTH MULTIPLIERS BY USING DUAL TREE ERROR COMPENSATION
N
Architecture
Error (%)
Area 103 um2
Power um/MHZ
12
Rounded
9.098
68.60
112.89
12
Existing fixed width
3.04
45.90
70.90
12
Proposed fixed width
2.11
33.94
55.89
16
Rounded
16.181
120.28
198.64
16
Existing fixed width
2.30
80.80
112.01
16
Proposed fixed width
2.0
59.86
99.90
Fig.2. Block diagram for fixed width multiplier
The block diagram show that once multiplication is completed .The partial product is divided into most significant part, input correction and least significant part. The least significant part is truncated from most significant part and input correction vector. The number of partial product items with higher weight will increase with the number of bits, while the number of partial product items with lower weight is fixed.Table1 describe the performances of fixedwidth multipliers by using dual tree error compensation.

Dual Tree Architecture
The architecture of proposed errorcompensation block is shown in Fig. 3. To take into account different weights of IC partial products, we divide the
input correction vector in two disjoined sets and use two addition trees to compute the error compensation.
The optimal IC subdivision (between standard and modified summation trees) and the optimal mixing block configuration have been obtained through exhaustive search. We realized two optimizations. In the first one, we assumed as a goal function the absolute error (Â£max), whereas the second optimization was carried out to minimize the meansquare error (Â£ms). This second addition tree uses modified half adders (mHAs) to take into account the contribution of partial products with higher weights.
The dualtree architecture has been obtained heuristically, after observing that the error compensation function can be approximated as a weighted sum of input correction vector partial products. In order to introduce our approach with the help of an example, let us consider a 6bit fixedwidth multiplier, with optimized meansquare error. we can eliminate the modified tree altogether, by sending the partial products originally assigned to the modified tree directly to the carrysave adder, with a weight LSB.
For this type architecture, it can be demonstrated that the final subtraction and the mixing block correspond to the inclusion of a NOR and an AND gate as shown in Fig. 4.
The best accuracy is obtained by designing the error compensation function according to either (16) or (21). This solution, however, calls for a lookup table to implement either the or functions. Lookup table complexity grows exponentially with, rapidly becoming an impractical solution.
II. CIRCUITS PERFORMANCES
We implemented rounded fullwidth multipliers, Jou [17], Curticapean [12], and the optimize dualtree fixed width multipliers proposed in this paper using a three metal 0.35 m technology with 3.3V supply voltage. In order to have a realistic and accurate indication of the architectures performances, we implemented the carrysave tree of all multipliers using the threedimensional reduction method (TDM) proposed in [19]. TDM is a state of the art technique to add elements of partial products matrix with a tree based carrysave approach, compensating for different delays in partial products generation, and exploiting delays asymmetries in fulladders to improve overall timing. Silicon area of developed dualtree multipliers is slightly reduced with respect
Fig.3. Architecture of dualtree error compensation block
Fig.4. Optimized implementation of dualtree errorcompensation blocks
to Jou and Curicapean solutions, with an area reduction of about 6% for n=16. Obviously, the advantage with respect to
complete rounded multiplier is much more evident, with area reduction of about 50%.
According to table 1, due to the reduced glitching in the partial products generation, the proposed circuits exhibit a lower power dissipation with respect to Jou and Curticapean solutions for n>4 . For instance, power saving is about 11% for n equal to 16. Power dissipation is almost halved with respect to the complete rounded multiplier.
The slope of transistor count increasing as the fixed width multiplier input number increases is gentler in our proposed design. Though in our proposed design we must spend more transistor count in the 8bit fixedwidth multiplier, we spend less transistor count in the cases of input bit number are larger than eight. The superiority in areaefficiency in our design is more obvious as input number increases.
IV SIMULATION RESULT AND DISCUSSION
Based on the concept in the previous section, we have designed a FWM for 16bit with reduced error and low power. The FWM was analyzed using Modelsim simulator at the system level. Modelsim is a simulation and debugging environment created by Mentor Graphics. Modelsim allows you to check the syntax and verify the functionality of VHDL programs.
Modelsim uses libraries in two ways:

As a local working library that contains the compiled version of your design;

As are source library. A common example of using both a working library and a resource library is one where your gate level design and test bench are compiled into the working library and the design references gatelevel models in a separate resource library.
Fig.2. Simulated Result
V CONCLUSION
In this paper, a lowerror and areaefficient fixedwidth multiplier by using the dual group minor input correction
vector is presented. As compared with the stateoftheart design in [8], the proposed fixedwidth multiplier improves accuracy, silicon area, timing performances and power dissipation. Simulation results for a 0.35Âµm technology show a decrease of the propagation delay up to 20%, with more than 10% power dissipation reduction.
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1.) ESWARI.S,
IIM.E (VLSI DESIGN),
Srinivasan Engineering College, Perambalur – 621 212.
Email.id: eswarivlsime@gmail.com Mobile No: +919698362951.
2.) RAJ KUMAR.A, ASSOCIATE PROFESSOR,
Srinivasan Engineering College, Perambalur 621 212.
Email id: arkumar77@gmail.com