 Open Access
 Total Downloads : 36
 Authors : Sarang. S. Karale , Dhanashri. M. Hogale
 Paper ID : IJERTV8IS060613
 Volume & Issue : Volume 08, Issue 06 (June 2019)
 Published (First Online): 28062019
 ISSN (Online) : 22780181
 Publisher Name : IJERT
 License: This work is licensed under a Creative Commons Attribution 4.0 International License
Design of 876 MSPS, 2.5v, 250nm, 4Bit Flash ADC using Quantum Voltage Comparator and Pseudo Logic Encoder
Sarang. S. Karale1

College of Engineering & Management Research,
Pune, India
Abstract: – Nowadays, there is the highest use of converters in the industries. The degradation of power consumption by these converters has great importance. This paper represents a new method to decrease the power consumption of the flash type analog to digital converter with 250 nm CMOS technology by using frequency which is of 1MHz. Flash type ADC requires 2n1 Comparator and its power supply voltage 2.5V. The proposed design of ADC using the Quantum Voltage Comparator eliminates the resistor ladder circuit and improves linearity of ADC. For the encoding process, the Pseudologic encoder has been used and it provides higher data conversion rate and maintain low power consumption. The proposed 4bit flash ADC paper having 876 MSPS speed and optimized power consumption by using the pseudologic encoder and Quantum Voltage Comparator.
Keywords: – 4Bit, Flash type ADC, Quantum Voltage Comparator, CMOS, Pseudo logic Encoder, TANNER EDA.

INTRODUCTION
An ADC is a very important feature that converts an analog signal to a digital signal. It provides the bridge between the analog and digital world. There are different types of ADCs pipelined ADC, Sigmadelta ADC, counter type ADC, etc which are affected by noise and power consumption. With the implementation of various technologies in the analog to digital circuits, the noise and power consumption can vary simultaneously [7]. There are three types of technologies used in data converters which are CMOS technology, bipolar technology, and gallium arsenide technology (GaAs) [4]. Among this CMOS technology having a high noise immunity and low static power consumption.
One problem with TIQ is that is noise susceptibility [5]. TIQ has a singleended input, the comparator is very sensitive to power supply noise and power supply voltage. To overcome this problem, we use a new comparator called Quantum Voltage (QV). It does not use the resistor ladder circuit. The QV comparator is derived from differential comparator [5]. There are different types of encoder like Wallace tree encoder, PLA/ROM and XOR encoders. We use a pseudologic encoder which directly converts the thermometer code to binary code. It also provides high conversion data rates while maintaining low power consumption [8].
Dhanashri. M. Hogale2
K.J. College of Engineering & Management Research,
Pune, India
Thus, we propose a paper with 2.5v, 4bit flash ADC using the pseudo logic encoder and QV comparator having a speed of 876 MSPS. 4bit flash ADC has been designed and implemented on the 250nm CMOS process with the help of TANNER EDA tool.

PROBLEM STATEMENT
In various types of ADC, it is necessary to optimize the parameters like speed, power consumption, noise sensitivity, and size. The TIQ comparator and FAT Tree Encoder based flash type ADC provides improvement in static power consumption, size, and speed. But Further improvement is necessary for low power devices and SoC applications.

FLASH TYPE ADC WITH QUANTUM VOLTAGE COMPARATOR AND PSEUDO LOGIC ENCODER
Fig.1: Basic block diagram of ADC
The flash type ADC with Quantum voltage comparator is described in above Fig.1, it encompassed Quantum voltage comparator, gain booster, and Pseudo logic encoder. The quantum voltage comparator induces thermometer code, this code is in the form of 0s and 1s which are then hand over to pseudo logic encoder. There are numerous encoders available, in this paper pseudo logic encoder replaces other encoders as it provides direct conversion of thermometer code to binary code with low power consumption.

QUANTUM VOLTAGE COMPARATOR
The TIQ comparator eliminates the resistor ladder network in conventional ADC as it generates reference voltage internally, it gives the improvement in static power consumption of a circuit. But the main problem regarding TIQ comparator is noise susceptibility [5]. As it has a singleended structure, it is more sensitive to power supply noise as well as temperature variation makes the DNL and the INL increased in the TIQ comparator.
To overcome this disadvantage of TIQ comparator, Quantum voltage comparator is introduced. The Quantum voltage comparator uses the same technique as that of TIQ to generate the internal reference voltage.
Fig.2: Quantum Voltage Comparator
The Quantum voltage comparator is derived from Differential comparator. In TIQ comparator, the different switching voltages are obtained by changing the size of transistors. This concept of generating reference voltage is used in Quantum voltage comparator. The following fig.2 shows Quantum voltage comparator. Design of various comparator carried out by changing the width of NMOS pair Q3, Q4 while keeping Q1, Q2 selfsame. The mismatch in size of transistor provides different switching voltages for different comparators. For 4Bit ADC 2n1 (i.e.

different size comparators are designed with different switching voltages. The input analog signal is applied to the Vin terminal of the comparator while keeping Va and Vb constant [6]. Inverter followed by quantum voltage comparator is used to get sharper voltage transfer characteristics curve.


GAIN BOOSTER
Fig.3: Schematic of Gain Booster
The gain booster circuit uses two inverters which are connected in series as shown in fig.3. The gain booster circuit increases voltage gain of comparator output which provides full digital output voltage swing [7]. The size of both inverters is small and both inverters are selfsame. It also provides the sharper switching voltages. For 4Bit ADC, there is a necessity of 2n1 i.e.15 different comparators, hence 15 gain boosters are also required.

PSEUDO LOGIC ENCODER
The Pseudo logic encoder is executed the same as that of PLA design logic. This Encoder design uses AND OR logic to convert the Thermometer code to Binary code. The encoder logic design for various bits is shown in figures 4, 5 and 6. The basic dissimilarity between PLA design and pseudo logic design is, PLA design gives output bit by making use of all bits of thermometer code but this pseudologic encoder makes use of only selective code bits.
Fig.4: Implementation Schematic of LSB bit
do the AND operation of selective bits these are connected in series.
Fig.5: Implementation Schematic of BIT 0
Fig.6: Implementation Schematic of BIT 1
The presented encoder is implemented using the following expressions:
LSB = I0I1+ I2I3+ I4I5+ I6I7 +I8I9+ I10I11+ I12I13+
I14.
BIT 0 = I1I3+ I5I7+ I9I11+ I13. BIT 1 = I3I7+ I11.
MSB = I7.
For an Nbit flash ADC, the most significant bit of binary output is logic high if thermometer code traverse half of the length of thermometer code. Therefore, MSB bit is the same as that of I7. The presented Encoder is executed using NMOS transistors and PMOS are used to the selective discharge of the output node.
Table 1 indicates the truth table of a pseudo logic encoder. The expressions of LSB, BIT0, BIT1, and MSB is obtained by using the following truth table [TABLE 1]. The circuit consists of clock driven PMOS. Inputs that are selective bits of thermometer codes are to be ORed using NMOS design logic which is connected in parallel and to
TABLE 1: TRUTH TABLE OF ENCODER
THERMOMETER CODES [I14 TO I0]
ENCODE OUTPUT
000000000000000
0000
000000000000001
0001
000000000000011
0010
000000000000111
0011
000000000001111
0100
000000000011111
0101
000000000111111
0110
000000001111111
0111
000000011111111
1000
000000111111111
1001
000001111111111
1010
000011111111111
1011
000111111111111
1100
001111111111111
1101
011111111111111
1110
1111111111111111
1111

RESULT AND DISCUSSION
The design and simulation are done by using TANNER EDA tools. The designing of 4bit ADC in the SEdit window of TANNER EDA tool is shown in fig.6. The process used for designing ADC is 250nm, which is compatible with the manufacturing of various ICs or microchips. The encoder circuit has a composition of PMOS transistor which driven by clock along with a block of NMOS logic which defines the logic operations.
The Quantum Voltage comparator compares the input voltage with an internally induced reference voltage. The pseudologic encoder is realized with ANDOR logic. At the output of Pseudo logic encoder, digital data bits are observed as display in fig.8.
Fig.7: output VTC of corresponding analog signal
The conversion of an analog input sinusoidal wave signal to digital binary bits in the form of a graph is achieved on Wedit. The following Fig.8 represents a prosperous conversion of the analog signal. The TANNER EDA tool is used as a simulation tool because it provides full design flow from schematic design to layout verifications.
Fig.6: Schematic of 4Bit ADC using QVC and Pseudo Logic encoder
The simulation results are noticed when the supply voltage VDD is equal to 2.5v. The frequency of input sinusoidal wave signal is 1MHz with input voltage having the amplitude of 750mv (Vin = 1.5VPP). The fig.7 shows output voltage transfer curves which are observed on W edit window of the simulation tool.
Fig.8: Transient output of 4Bit ADC

CONCLUSION

The corresponding technique of reducing power consumption and improvement in the speed is carried out on 250nm CMOS technology and simulated on TANNER EDA tool. The demonstrated pseudo logic encoder with Quantum Voltage Comparator increases the speed and downgrades the power consumption. The Quantum Voltage comparator gives an efficient way to generate reference voltage internally as well as it effectively compares the input analog signal with a reference voltage. The result summary is shown in TABLE 2 which indicates the transistor count of presented design is reduced to 221 and the speed of 876 MSPS is successfully achieved by means of Quantum voltage comparator and Pseudologic encoder.
Architecture 
[3]  [4]  [4] 
Proposed 
Resolution (no. of output bits) 
4Bit 
4Bit 
4Bit 
4Bit 
CMOS technology 
250nm 
250nm 
250nm 
250nm 
Transistor count 
– 
436 
436 
221 
Power supply (VDD) 
2.5v 
2.5 
3.3 
2.5v 
Average power consumed 
1.9mW 
4.0890 mW 
9.98 mW 
6.65mW 
Speed 
3.0 MSPS 
555 MSPS 
690 MSPS 
876 MSPS 
Input Frequency 
1MHz 
1MHz 
1MHz 
1MHz 
Architecture 
[3]  [4]  [4] 
Proposed 
Resolution (no. of output bits) 
4Bit 
4Bit 
4Bit 
4Bit 
CMOS technology 
250nm 
250nm 
250nm 
250nm 
Transistor count 
– 
436 
436 
221 
Power supply (VDD) 
2.5v 
2.5 
3.3 
2.5v 
Average power consumed 
1.9mW 
4.0890 mW 
9.98 mW 
6.65mW 
Speed 
3.0 MSPS 
555 MSPS 
690 MSPS 
876 MSPS 
Input Frequency 
1MHz 
1MHz 
1MHz 
1MHz 
TABLE 2: RESULT SUMMARY
ACKNOWLEDGMENT
The authors are thankful to Dr. S.S. Khot, Principal of KJ College of Engineering and Management Research for his valuable guidance, support and continuous encouragement during completion of this paper. I am thankful to Prof. Rahimraja Shaikh, BEProject Co ordinator of our college for his valuable support, guidance and constant encouragement.
Lastly, we thanks to KJ College of Engineering and Management Research, Pune and wellwishers who have contributed directly or indirectly for successful completion of this paper. This is an explore to prove our technical skill for the advancement of social lifestyle.
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